CN106849946A - A kind of fractional frequency division frequency synthesizer and decimal frequency dividing method - Google Patents
A kind of fractional frequency division frequency synthesizer and decimal frequency dividing method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
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Abstract
The present invention provides a kind of fractional frequency division frequency synthesizer and decimal frequency dividing method, wherein, the fractional frequency division frequency synthesizer includes being sequentially connected and constituting voltage controlled oscillator, pre- frequency dividing circuit, multi-modulus frequency divider, the jittered circuit of clock, phase frequency detector, charge pump and the loop filter of phaselocked loop.In the two paths of signals of the pre- frequency dividing circuit output, all the way in multi-modulus frequency divider described in signal input, another road signal is input into the jittered circuit of clock as sampling trigger signal；The output signal of the jittered circuit of clock is input into the phase frequency detector jointly with preset reference clock signal；The output signal of the phase frequency detector controls the charge pump that electric current is injected or collected to the loop filter.Fractional frequency division frequency synthesizer and decimal frequency dividing method that the present invention is provided, can suppress the fractional stray in link, so as to improve the quality of output spectrum.
Description
Technical field
The present invention relates to radio-frequency front-end technical field, and in particular to a kind of fractional frequency division frequency synthesizer and fractional frequency division side
Method.
Background technology
As phaselocked loop is in RFIC at this stage (Radio Frequency Integrated Circuit, the integrated electricity of radio frequency
Road) and SoC (System on Chip, system level chip) in application it is more and more extensive, high accuracy, the phaselocked loop of low-power consumption exists
Recent decades have obtained development at full speed.Currently, output frequency is usually required that for measuring the high performance signal generator of calibration
Resolution ratio reaches a hertz magnitude.However, traditional integer type phaselocked loop is due to its own electric circuit characteristic, its output frequency resolution
It is relatively low, it is impossible to meet the system requirements higher to output frequency precision requirement.Fractional frequency division frequency synthesizer is with same ginseng
Examine and be capable of achieving the advantage of frequency resolution higher and instead of traditional integral frequency divisioil frequency synthesizer under frequency.But existing
Under some technical conditions, fractional frequency division cannot be also directly realized by, a kind of average method can only be used with variable integer frequency divider
To realize fractional frequency division function.Although but fractional frequency-division phase-locked loop can reach frequency modulation precision very high, itself there is also scarce
Fall into：Fractional stray is often higher, so as to influence the quality of phaselocked loop output spectrum.
The content of the invention
The purpose of the embodiment of the present invention is to provide a kind of fractional frequency division frequency synthesizer and decimal frequency dividing method, can be pressed down
Fractional stray in link processed, so as to improve the quality of output spectrum.
To achieve the above object, on the one hand the embodiment of the present invention provides a kind of fractional frequency division frequency synthesizer, including successively
Connect and constitute voltage controlled oscillator, pre- frequency dividing circuit, multi-modulus frequency divider, the jittered circuit of clock, phase frequency detector, the electricity of phaselocked loop
Lotus pump and loop filter；Wherein, in the two paths of signals of the pre- frequency dividing circuit output, multimode described in signal input is divided all the way
In frequency device, another road signal is input into the jittered circuit of clock as sampling trigger signal；The jittered circuit of clock it is defeated
Go out signal to be input into jointly in the phase frequency detector with preset reference clock signal；The output signal control of the phase frequency detector
Electric current is injected or collected to the charge pump to the loop filter, and the control electricity of the voltage controlled oscillator is supplied to adjust
Pressure.
Further, the fractional frequency division frequency synthesizer also includes the Delta- being connected with the multi-modulus frequency divider
Sigma modulators, the Delta-sigma modulators use MASH1-1 structures, to control the frequency dividing of the multi-modulus frequency divider
Than.
Further, in the two paths of signals of multi-modulus frequency divider output, the jittered circuit of clock described in signal input all the way
In, another road signal is used as in Delta-sigma modulators described in clock signal input.
Further, the jittered circuit of the clock includes pseudo-random sequence generator, multi-channel gating device and is sequentially connected
Predetermined number d type flip flop, wherein, first input of d type flip flop of signal input all the way of multi-modulus frequency divider output
End and the input of the pseudo-random sequence generator；Each D triggerings of signal input all the way of the pre- frequency dividing circuit output
The triggering end of device；In two neighboring d type flip flop, the output end of previous d type flip flop and the latter input phase of d type flip flop
Even；The signal of each d type flip flop output is input into the gating port of the multi-channel gating device respectively；The pseudo-random sequence is produced
The output signal of device is input into the control port of the multi-channel gating device；The output signal of the multi-channel gating device is input into the mirror
In frequency phase discriminator.
To achieve the above object, the embodiment of the present application also provides a kind of decimal frequency dividing method, and methods described includes：By piezoelectricity
The feedback signal of oscillator output carries out scaling down processing by pre- frequency dividing circuit, obtains the first sub-frequency clock signal；By described
One sub-frequency clock signal carries out scaling down processing again by multi-modulus frequency divider, obtains the second sub-frequency clock signal；By described first
Sub-frequency clock signal and second sub-frequency clock signal add respectively as sampling trigger signal and pending signal input clock
Twitter circuit, obtains by the output clock signal of jittered treatment；The output clock signal and preset reference clock signal are total to
With input phase frequency detector in, and using the phase frequency detector output signal control charge pump to loop filter inject or
Person collects electric current, and the control voltage of the voltage controlled oscillator is supplied to adjust.
Further, methods described also includes：By second sub-frequency clock signal input and the multi-modulus frequency divider phase
In Delta-sigma modulators even, the Delta-sigma modulators use MASH1-1 structures, to control the multimode point
The frequency dividing ratio of frequency device.
Further, the step of frequency dividing ratio for controlling the multi-modulus frequency divider, includes：The Delta-sigma modulators will
Preset fraction frequency regulation control word is converted to two dynamic control words；The Delta-sigma modulators are dynamic by described two
State control word is added with default integer frequency regulation control word, and the result that will add up is input into the control of the multi-modulus frequency divider
Word port processed so that the multi-modulus frequency divider determines current frequency dividing ratio according to the result of the addition.
Further, the jittered circuit of the clock includes pseudo-random sequence generator, multi-channel gating device and is sequentially connected
Predetermined number d type flip flop；Correspondingly, determine in the following manner by the output clock signal of jittered treatment：Will be described
The input of the second sub-frequency clock signal first d type flip flop of input and the input of the pseudo-random sequence generator；Will
First sub-frequency clock signal is input into the triggering end of each d type flip flop；The signal that each d type flip flop is exported is input into institute respectively
In stating the gating port of multi-channel gating device；The output signal of the pseudo-random sequence generator is input into the multi-channel gating device
In control port, to select the signal of one of d type flip flop output as the output clock signal by jittered treatment.
Further, inject or receive to loop filter using the output signal control charge pump of the phase frequency detector
Obtaining current is specifically included：The phase frequency detector is according to the phase between the output clock signal and preset reference clock signal
Difference, generates control signal identical with the phase difference polarity and being directly proportional to the phase difference；According to the control signal
Polarity and absolute value, control the charge pump that electric current is injected or collected to the loop filter.
Further, according to the polarity and absolute value of the control signal, the charge pump is controlled to the loop filtering
Device injects or collects electric current and specifically includes：When the polarity of the control signal is timing, the charge pump is controlled to the ring
Path filter injects the electric current into preset ratio with the absolute value of the control signal；When the polarity of the control signal is negative
When, control the charge pump that the electric current with the absolute value of the control signal into preset ratio is collected to the loop filter.
Using above-mentioned technical proposal, the present invention can at least obtain following technique effects：
The jittered circuit of clock adds randomized jitter by the output clock to multi-modulus frequency divider, such that it is able to reduce frequency discrimination mirror
The periodicity of phase error in phase device output signal, so as to suppress the decimal on fractional frequency division frequency synthesizer output clock spectrum
It is spuious, improve the quality of output spectrum, improve because fractional stray is excessively serious to fractional frequency division frequency synthesizer should
With the limitation for bringing.
Brief description of the drawings
Technical scheme in order to illustrate more clearly the embodiments of the present invention, institute in being described to the embodiment of the present invention below
The accompanying drawing for needing to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also implement according to the present invention
The content and these accompanying drawings of example obtain other accompanying drawings.
Fig. 1 is the structural representation of the fractional frequency division frequency synthesizer described in the present embodiment；
Fig. 2 is the schematic diagram of the jittered circuit of clock in the present embodiment；
Fig. 3 is the flow chart of the decimal frequency dividing method described in the present embodiment.
Through accompanying drawing, it should be noted that similar label is used to describe same or analogous element, feature and structure.
Specific embodiment
The disclosure for providing description referring to the drawings to help comprehensive understanding to be limited by claim and its equivalent
Various embodiments.Hereinafter description includes the various details for helping understand, but these details will be considered as only being example
Property.Therefore, it will be appreciated by those of ordinary skill in the art that do not depart from the scope of the present disclosure and spirit in the case of, can be right
Various embodiments described herein makes various changes and modifications.In addition, in order to clear and succinct, known function and construction are retouched
Stating to be omitted.
Term and vocabulary used in following description and claims are not limited to document implication, but only by inventor
For enabling the disclosure clearly and as one man to be understood.Therefore, to those skilled in the art it should be apparent that carrying
The description of various embodiments of this disclosure is merely to exemplary purpose under being provided with, and it is unrestricted by appended claims and its
The purpose of the disclosure that equivalent is limited.
It should be understood that unless context is clearly indicated in addition, otherwise singulative also includes plural.Thus, for example,
Reference to " assembly surface " includes the reference to one or more such surfaces.
Fig. 1 is referred to, the embodiment of the present application provides a kind of fractional frequency division frequency synthesizer.The fractional frequency division frequency synthesis
Device includes that being sequentially connected and constitute the voltage controlled oscillator 100 of phaselocked loop, pre- frequency dividing circuit 200, multi-modulus frequency divider 300, clock adds
Twitter circuit 400, phase frequency detector 500, charge pump 600 and loop filter 700.
In the present embodiment, in the two paths of signals of the pre- frequency dividing circuit 200 output, multimode described in signal input all the way
In frequency divider 300, another road signal is input into the jittered circuit 400 of clock as sampling trigger signal.The clock is jittered
The output signal of circuit 400 is input into the phase frequency detector 500 jointly with preset reference clock signal Ref_clk.In this reality
Apply in mode, the output signal of the phase frequency detector 500 can control the charge pump 600 to the loop filter 700
Electric current is injected or collected, the control voltage of the voltage controlled oscillator 100 is supplied to adjust.
Fig. 2 is referred to, the jittered circuit 400 of clock can include pseudo-random sequence generator 401, multi-channel gating device
402 and the d type flip flop 403 of the predetermined number being sequentially connected, wherein, in two neighboring d type flip flop, previous d type flip flop
Output end is connected with the input of latter d type flip flop.Below by taking 4 d type flip flops as an example, in the elaboration jittered circuit 400 of clock
Annexation and operation principle.
In the present embodiment, the div_clk of signal all the way of the output of the multi-modulus frequency divider 300 is input into first D triggering
The input of the input of device and the pseudo-random sequence generator 401.The signal all the way of the output of pre- frequency dividing circuit 200
Ctrl_clk is input into the triggering end of each d type flip flop.The signal of each d type flip flop output is input into the multi-channel gating device respectively
In 402 gating port.The output signal of the pseudo-random sequence generator 401 is input into the control of the multi-channel gating device 402
In port.Finally, the output signal of the multi-channel gating device 402 can be input into the phase frequency detector 500.
In the present embodiment, 4 d type flip flops may be constructed time delay chain, and the signal div_clk to being input into prolongs successively
When.The purpose of so treatment is that the phase of signal after time delay can introduce random shake, so just can finally reduce frequency discrimination
The periodicity of phase error in the output signal of phase discriminator 500 such that it is able to suppress fractional stray.In the present embodiment, it is pseudo- with
Machine sequence generator 401 can produce two pseudo noise codes.This two pseudo noise codes may be constructed four kinds of different control signals
00、01、10、11.These four different control signals can respectively correspond to four output signals of d type flip flop.So, by puppet
The pseudo noise code of the generation of random sequence generator 401 such that it is able to select the output signal of one of d type flip flop to pass through multichannel
Gate is exported.In the present embodiment, the pseudo-random sequence generator 401 can be made up of shift register.
In the present embodiment, the fractional frequency division frequency synthesizer also includes what is be connected with the multi-modulus frequency divider 300
Delta-sigma modulators 800.The Delta-sigma modulators 800 can use MASH1-1 structures, such that it is able to control
The frequency dividing ratio of the multi-modulus frequency divider 300.Specifically, the multi-modulus frequency divider 300 can export two paths of signals, the two of output
In the signal of road, signal can be input into the jittered circuit 400 of the clock all the way, and another road signal then can be defeated as clock signal
Enter in the Delta-sigma modulators 800, to drive, the Delta-sigma modulators 800 are normal to be run.
In the present embodiment, the Delta-sigma modulators 800 can turn preset fraction frequency regulation control word
It is changed to two dynamic control words.Specifically, Digital High Pass Filter can be carried out by adjusting control word to preset fraction frequency, from
And it is converted to two dynamic control words.Then, the Delta-sigma modulators can by two dynamic control words with
Default integer frequency regulation control word is added, and the result that will add up is input into the control word end of the multi-modulus frequency divider 300
Mouthful so that the multi-modulus frequency divider 300 determines current frequency dividing ratio according to the result of the addition.Specifically, the multimode point
Frequency device 300 can generally carry out 2 frequency dividings and 3 frequency dividings.For example, the control received when the control word port of multi-modulus frequency divider 300
When word is 0,2 frequency dividings can be carried out；When the control word that control word port receives is 1,3 frequency dividings can be carried out.
In the present embodiment, two dynamic control words for example can be 0 and 1, the default integer frequency regulation
Control word for example can be 0, then after adding, can obtain 0 or 1.The result being added is asked by following period of time
Average, just can obtain control fractional frequency division than control word.
Fig. 3 is referred to, the embodiment of the present application also provides a kind of decimal frequency dividing method.It should be noted that, although hereafter retouching
The flow stated includes the multiple operations occurred with particular order, but it should be clearly understood that these processes can include it is more or
Less operation, these operations can be performed sequentially or executed in parallel (for example using parallel processor or multi-thread environment).Institute
The method of stating is comprised the following steps.
S1：The feedback signal that piezoelectric oscillator is exported is carried out into scaling down processing by pre- frequency dividing circuit, the first frequency dividing is obtained
Clock signal；
S2：First sub-frequency clock signal is carried out into scaling down processing again by multi-modulus frequency divider, the second frequency dividing is obtained
Clock signal；
S3：Using first sub-frequency clock signal and second sub-frequency clock signal as sampling trigger signal and
The pending jittered circuit of signal input clock, obtains by the output clock signal of jittered treatment；
S4：The output clock signal and preset reference clock signal are input into phase frequency detector jointly, and utilize institute
Electric current is injected or collected to the output signal control charge pump for stating phase frequency detector to loop filter, is supplied to regulation described
The control voltage of voltage controlled oscillator.
In the application one embodiment, methods described also includes：
In the Delta-sigma modulators that second sub-frequency clock signal input is connected with the multi-modulus frequency divider,
The Delta-sigma modulators use MASH1-1 structures, to control the frequency dividing ratio of the multi-modulus frequency divider.
Include in the application one embodiment, the step of the frequency dividing ratio for controlling the multi-modulus frequency divider：
Preset fraction frequency regulation control word is converted to two dynamic control words by the Delta-sigma modulators.So
Afterwards, with default integer frequency regulation control word be added two dynamic control words by the Delta-sigma modulators,
And the result that will add up is input into the control word port of the multi-modulus frequency divider so that the multi-modulus frequency divider is according to the addition
Result determines current frequency dividing ratio.
In the application one embodiment, the jittered circuit of clock includes pseudo-random sequence generator, multi-channel gating device
And the d type flip flop of the predetermined number being sequentially connected；Correspondingly, by jittered treatment output clock signal in the following manner
It is determined that：
The input and the pseudo-random sequence of second sub-frequency clock signal, first d type flip flop of input are produced
The input of device；
First sub-frequency clock signal is input into the triggering end of each d type flip flop；
The signal that each d type flip flop is exported is input into the gating port of the multi-channel gating device respectively；
The output signal of the pseudo-random sequence generator is input into the control port of the multi-channel gating device, to select
The signal of one of d type flip flop output is used as the output clock signal by jittered treatment.
In the application one embodiment, charge pump is controlled to loop filtering using the output signal of the phase frequency detector
Device injects or collects electric current and specifically includes：
The phase frequency detector is according to the phase difference between the output clock signal and preset reference clock signal, generation
Control signal that is identical with the phase difference polarity and being directly proportional to the phase difference.
Specifically, a proportionality coefficient can be pre-set between the phase difference and control signal, the proportionality coefficient can
To be greater than 0 integer.Being multiplied by the proportionality coefficient using phase difference just can obtain the control signal.Just can so ensure
Phase difference is identical with the polarity of control signal.
It is then possible to according to the polarity and absolute value of the control signal, control the charge pump to the loop filtering
Device injects or collects electric current.
Specifically, in the application one embodiment, according to the polarity and absolute value of the control signal, the electricity is controlled
Lotus pump injects to the loop filter or collects electric current and specifically includes：
When the polarity of the control signal is timing, the charge pump is controlled to be injected and the control to the loop filter
Electric current of the absolute value of signal processed into preset ratio；
When the polarity of the control signal is to bear, the charge pump is controlled to be collected and the control to the loop filter
Electric current of the absolute value of signal processed into preset ratio.
In the present embodiment, the preset ratio can also be an integer more than 0.So, control signal is exhausted
Bigger to being worth, the magnitude of current for injecting or collecting is just bigger such that it is able to which real-time adjustment loads on the control on voltage controlled oscillator
Voltage.
Using above-mentioned technical proposal, the present invention can at least obtain following technique effects：
The jittered circuit of clock adds randomized jitter by the output clock to multi-modulus frequency divider, such that it is able to reduce frequency discrimination mirror
The periodicity of phase error in phase device output signal, so as to suppress the decimal on fractional frequency division frequency synthesizer output clock spectrum
It is spuious, improve the quality of output spectrum, improve because fractional stray is excessively serious to fractional frequency division frequency synthesizer should
With the limitation for bringing.
It should be noted that the various embodiments of the disclosure as described above are generally related to input data to a certain extent
Treatment and output data generation.The treatment of this input data and output data generation can be in hardware or soft with combination of hardware
Realized in part.For example, can in mobile device or similar or related circuit using specific electronic components for realize with
The function of the various embodiments association of the disclosure as described above.Alternatively, according to the instruction for being stored operate one or more
Multiple processors can realize the function of being associated with the various embodiments of the disclosure as described above.If it is, then these instructions
Can be stored on one or more non-transitory processor readable mediums, this is in the scope of the present disclosure.Processor can
The example for reading medium includes read-only storage (ROM), random access memory (RAM), CD-ROM, tape, floppy disk and optics number
According to storage device.In addition, for realizing that functional computer program, instruction and the instruction segment of the disclosure can be by disclosure arts
Programmer easily explain.
Each implementation method in this specification is described by the way of progressive, identical similar between each implementation method
Part mutually referring to what each implementation method was stressed is the difference with other embodiment.
Although the various embodiments with reference to the disclosure have shown and described the disclosure, those skilled in the art will manage
Solution, in the case where the spirit and scope of the present disclosure being defined by the appended claims and the equivalents thereof are not departed from, can enter to it
Various changes in row form and details.
Claims (10)
1. a kind of fractional frequency division frequency synthesizer, it is characterised in that including being sequentially connected and constitute phaselocked loop voltage controlled oscillator,
The jittered circuit of pre- frequency dividing circuit, multi-modulus frequency divider, clock, phase frequency detector, charge pump and loop filter；Wherein, it is described
In the two paths of signals of pre- frequency dividing circuit output, all the way in multi-modulus frequency divider described in signal input, another road signal is touched as sampling
Signal and be input into the jittered circuit of clock；The output signal of the jittered circuit of clock is common with preset reference clock signal
It is input into the phase frequency detector；The output signal of the phase frequency detector controls the charge pump to be noted to the loop filter
Enter or collect electric current, the control voltage of the voltage controlled oscillator is supplied to adjust.
2. fractional frequency division frequency synthesizer according to claim 1, it is characterised in that the fractional frequency division frequency synthesizer
Also include the Delta-sigma modulators being connected with the multi-modulus frequency divider, the Delta-sigma modulators use MASH1-
1 structure, to control the frequency dividing ratio of the multi-modulus frequency divider.
3. fractional frequency division frequency synthesizer according to claim 2, it is characterised in that the two of the multi-modulus frequency divider output
In the signal of road, all the way in the jittered circuit of clock described in signal input, another road signal is used as Delta- described in clock signal input
In sigma modulators.
4. fractional frequency division frequency synthesizer according to claim 1, it is characterised in that the jittered circuit of clock includes puppet
The d type flip flop of random sequence generator, multi-channel gating device and the predetermined number being sequentially connected, wherein, the multi-modulus frequency divider
The input and the input of the pseudo-random sequence generator of first d type flip flop of signal input all the way of output；It is described
The triggering end of the signal input all the way of pre- frequency dividing circuit output each d type flip flop；In two neighboring d type flip flop, previous D triggerings
The output end of device is connected with the input of latter d type flip flop；The signal of each d type flip flop output is input into the multichannel choosing respectively
In the gating port of logical device；The output signal of the pseudo-random sequence generator is input into the control port of the multi-channel gating device
In；The output signal of the multi-channel gating device is input into the phase frequency detector.
5. the decimal frequency dividing method in a kind of fractional frequency division frequency synthesizer being applied to as described in any in Claims 1-4,
Characterized in that, methods described includes：
The feedback signal that piezoelectric oscillator is exported is carried out into scaling down processing by pre- frequency dividing circuit, the first frequency-dividing clock letter is obtained
Number；
First sub-frequency clock signal is carried out into scaling down processing again by multi-modulus frequency divider, the second frequency-dividing clock letter is obtained
Number；
Using first sub-frequency clock signal and second sub-frequency clock signal as sampling trigger signal and pending
The jittered circuit of signal input clock, obtains by the output clock signal of jittered treatment；
The output clock signal and preset reference clock signal are input into phase frequency detector jointly, and using frequency discrimination mirror
Electric current is injected or collected to the output signal control charge pump of phase device to loop filter, and the VCO is supplied to adjust
The control voltage of device.
6. decimal frequency dividing method according to claim 5, it is characterised in that methods described also includes：
It is described in the Delta-sigma modulators that second sub-frequency clock signal input is connected with the multi-modulus frequency divider
Delta-sigma modulators use MASH1-1 structures, to control the frequency dividing ratio of the multi-modulus frequency divider.
7. decimal frequency dividing method according to claim 6, it is characterised in that the frequency dividing ratio of the control multi-modulus frequency divider
Step includes：
Preset fraction frequency regulation control word is converted to two dynamic control words by the Delta-sigma modulators；
Two dynamic control words are carried out phase by the Delta-sigma modulators with default integer frequency regulation control word
Plus, and the result that will add up is input into the control word port of the multi-modulus frequency divider so that the multi-modulus frequency divider is according to the phase
Plus result determine current frequency dividing ratio.
8. decimal frequency dividing method according to claim 5, it is characterised in that the jittered circuit of clock includes pseudorandom sequence
The d type flip flop of row generator, multi-channel gating device and the predetermined number being sequentially connected；Correspondingly, by the output of jittered treatment
Clock signal determines in the following manner：
Second sub-frequency clock signal is input into the input and the pseudo-random sequence generator of first d type flip flop
Input；
First sub-frequency clock signal is input into the triggering end of each d type flip flop；
The signal that each d type flip flop is exported is input into the gating port of the multi-channel gating device respectively；
The output signal of the pseudo-random sequence generator is input into the control port of the multi-channel gating device, to select wherein
One signal of d type flip flop output is used as the output clock signal by jittered treatment.
9. decimal frequency dividing method according to claim 5, it is characterised in that using the output signal of the phase frequency detector
Control charge pump is injected or collects electric current and specifically includes to loop filter：
The phase frequency detector is according to the phase difference between the output clock signal and preset reference clock signal, generation and institute
State that phase difference polarity is identical and control signal that be directly proportional to the phase difference；
According to the polarity and absolute value of the control signal, the charge pump is controlled to inject or collect to the loop filter
Electric current.
10. decimal frequency dividing method according to claim 9, it is characterised in that polarity according to the control signal and absolutely
To value, control the charge pump to be injected to the loop filter or collect electric current and specifically include：
When the polarity of the control signal is timing, the charge pump is controlled to be injected and the control letter to the loop filter
Number absolute value into preset ratio electric current；
When the polarity of the control signal is to bear, the charge pump is controlled to be collected to the loop filter and the control letter
Number absolute value into preset ratio electric current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611143304.9A CN106849946A (en) | 2016-12-13 | 2016-12-13 | A kind of fractional frequency division frequency synthesizer and decimal frequency dividing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611143304.9A CN106849946A (en) | 2016-12-13 | 2016-12-13 | A kind of fractional frequency division frequency synthesizer and decimal frequency dividing method |
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| CN106849946A true CN106849946A (en) | 2017-06-13 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109150177A (en) * | 2018-06-26 | 2019-01-04 | 杭州雄迈集成电路技术有限公司 | A kind of fractional frequency division implementation method of the jittered mechanism of band |
| CN109936363A (en) * | 2019-03-06 | 2019-06-25 | 北京中创锐科信息技术有限公司 | Broadband fractional frequency-division phase-locked loop system and its spuious optimization method |
| CN110190847A (en) * | 2019-04-26 | 2019-08-30 | 西安邮电大学 | A kind of fractional-N divide circuit and method applied to frequency synthesizer |
| CN112803945A (en) * | 2021-01-06 | 2021-05-14 | 昆腾微电子股份有限公司 | Method and device for acquiring decimal frequency division clock signal |
| CN114421967A (en) * | 2022-01-24 | 2022-04-29 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic device |
| CN114726365A (en) * | 2022-06-06 | 2022-07-08 | 深圳市德兴达科技有限公司 | Low-noise phase-locked loop control circuit, device and method |
| CN116094527A (en) * | 2023-04-07 | 2023-05-09 | 核芯互联科技(青岛)有限公司 | Integral differential modulator for eliminating walk-around spurious |
| CN116647233A (en) * | 2023-05-18 | 2023-08-25 | 成都电科星拓科技有限公司 | Multimode frequency divider, phase-locked loop and chip for reducing phase difference of different frequency division ratios |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1361592A (en) * | 2002-01-29 | 2002-07-31 | 东南大学 | Device to realize Pascal's triangle numerical operation |
| US20030137359A1 (en) * | 2002-01-18 | 2003-07-24 | Nokia Corporation | Fractional-n frequency synthesizer with sine wave generator |
| US20080024240A1 (en) * | 2006-07-28 | 2008-01-31 | Mstar Semiconductor, Inc. | Delta-sigma modulated fractional-n pll frequency synthesizer |
| CN102684686A (en) * | 2012-05-09 | 2012-09-19 | 上海宏力半导体制造有限公司 | Phase-locked loop with reduced in-band phase noise and corresponding working method thereof |
| CN102882520A (en) * | 2012-09-28 | 2013-01-16 | 兆讯恒达微电子技术(北京)有限公司 | Device and method for clock frequency division based on sigma-delta phase locked loop |
| CN104467826A (en) * | 2014-12-18 | 2015-03-25 | 中国电子科技集团公司第五十四研究所 | Delta-sigma fractional frequency synthesizer with dithering shaping function |
| CN204290940U (en) * | 2014-07-24 | 2015-04-22 | 江苏星宇芯联电子科技有限公司 | The clock of fractional frequency division frequency synthesizer adds twitter circuit |
| CN105049039A (en) * | 2015-07-08 | 2015-11-11 | 中国电子科技集团公司第四十一研究所 | Fractional frequency division circuit for spur suppression |
| CN105577178A (en) * | 2015-12-11 | 2016-05-11 | 中国航空工业集团公司西安航空计算技术研究所 | Broadband low-phase noise Sigma-Delta phase-locked loop |
-
2016
- 2016-12-13 CN CN201611143304.9A patent/CN106849946A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030137359A1 (en) * | 2002-01-18 | 2003-07-24 | Nokia Corporation | Fractional-n frequency synthesizer with sine wave generator |
| CN1361592A (en) * | 2002-01-29 | 2002-07-31 | 东南大学 | Device to realize Pascal's triangle numerical operation |
| US20080024240A1 (en) * | 2006-07-28 | 2008-01-31 | Mstar Semiconductor, Inc. | Delta-sigma modulated fractional-n pll frequency synthesizer |
| CN102684686A (en) * | 2012-05-09 | 2012-09-19 | 上海宏力半导体制造有限公司 | Phase-locked loop with reduced in-band phase noise and corresponding working method thereof |
| CN102882520A (en) * | 2012-09-28 | 2013-01-16 | 兆讯恒达微电子技术(北京)有限公司 | Device and method for clock frequency division based on sigma-delta phase locked loop |
| CN204290940U (en) * | 2014-07-24 | 2015-04-22 | 江苏星宇芯联电子科技有限公司 | The clock of fractional frequency division frequency synthesizer adds twitter circuit |
| CN104467826A (en) * | 2014-12-18 | 2015-03-25 | 中国电子科技集团公司第五十四研究所 | Delta-sigma fractional frequency synthesizer with dithering shaping function |
| CN105049039A (en) * | 2015-07-08 | 2015-11-11 | 中国电子科技集团公司第四十一研究所 | Fractional frequency division circuit for spur suppression |
| CN105577178A (en) * | 2015-12-11 | 2016-05-11 | 中国航空工业集团公司西安航空计算技术研究所 | Broadband low-phase noise Sigma-Delta phase-locked loop |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109150177B (en) * | 2018-06-26 | 2022-07-19 | 杭州雄迈集成电路技术股份有限公司 | Decimal frequency division implementation method with dithering mechanism |
| CN109150177A (en) * | 2018-06-26 | 2019-01-04 | 杭州雄迈集成电路技术有限公司 | A kind of fractional frequency division implementation method of the jittered mechanism of band |
| CN109936363A (en) * | 2019-03-06 | 2019-06-25 | 北京中创锐科信息技术有限公司 | Broadband fractional frequency-division phase-locked loop system and its spuious optimization method |
| CN109936363B (en) * | 2019-03-06 | 2023-08-04 | 北京中创锐科信息技术有限公司 | Broadband fractional frequency division phase-locked loop system and spurious optimization method thereof |
| CN110190847A (en) * | 2019-04-26 | 2019-08-30 | 西安邮电大学 | A kind of fractional-N divide circuit and method applied to frequency synthesizer |
| CN112803945A (en) * | 2021-01-06 | 2021-05-14 | 昆腾微电子股份有限公司 | Method and device for acquiring decimal frequency division clock signal |
| CN112803945B (en) * | 2021-01-06 | 2023-06-30 | 昆腾微电子股份有限公司 | Method and device for acquiring decimal frequency division clock signal |
| CN114421967A (en) * | 2022-01-24 | 2022-04-29 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic device |
| CN114421967B (en) * | 2022-01-24 | 2024-05-31 | 高澈科技(上海)有限公司 | Phase interpolation circuit, phase-locked loop, chip and electronic equipment |
| CN114726365A (en) * | 2022-06-06 | 2022-07-08 | 深圳市德兴达科技有限公司 | Low-noise phase-locked loop control circuit, device and method |
| CN114726365B (en) * | 2022-06-06 | 2022-08-19 | 深圳市德兴达科技有限公司 | Low-noise phase-locked loop control circuit, device and method |
| CN116094527A (en) * | 2023-04-07 | 2023-05-09 | 核芯互联科技(青岛)有限公司 | Integral differential modulator for eliminating walk-around spurious |
| CN116647233A (en) * | 2023-05-18 | 2023-08-25 | 成都电科星拓科技有限公司 | Multimode frequency divider, phase-locked loop and chip for reducing phase difference of different frequency division ratios |
| CN116647233B (en) * | 2023-05-18 | 2024-04-02 | 成都电科星拓科技有限公司 | Multimode frequency divider, phase-locked loop and chip for reducing phase difference of different frequency division ratios |
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