CN116647233A - Multimode frequency divider, phase-locked loop and chip for reducing phase difference of different frequency division ratios - Google Patents

Multimode frequency divider, phase-locked loop and chip for reducing phase difference of different frequency division ratios Download PDF

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Publication number
CN116647233A
CN116647233A CN202310564237.1A CN202310564237A CN116647233A CN 116647233 A CN116647233 A CN 116647233A CN 202310564237 A CN202310564237 A CN 202310564237A CN 116647233 A CN116647233 A CN 116647233A
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electrically connected
divider
stage
frequency
phase
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CN202310564237.1A
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CN116647233B (en
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张磊
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Chengdu Cetc Xingtuo Technology Co ltd
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Chengdu Cetc Xingtuo Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention discloses a multi-mode frequency divider, a phase-locked loop and a chip for reducing phase difference of different frequency dividing ratios, wherein the multi-mode frequency divider comprises a multi-stage two/three frequency divider, a delay circuit, an inverter, a multiplexer, a buffer and a D type trigger, wherein the D type trigger is electrically connected with each stage of two/three frequency divider and performs sampling integration, so that control signals of each stage of two/three frequency divider are synchronously switched to avoid burrs; the delay circuit is configured to compensate for an excess delay of the final divide-by-two/three divider to compensate for a phase difference between an integer divide ratio and a fractional divide ratio produced by the multiple divide-by-two/three divider. The invention can reduce the phase difference between the integer frequency division ratio and the decimal frequency division ratio, thereby avoiding burrs and avoiding the influence on jitter.

Description

Multimode frequency divider, phase-locked loop and chip for reducing phase difference of different frequency division ratios
Technical Field
The present invention relates to the field of clock/interface chip design technology, and in particular, to a multi-mode frequency divider, a phase-locked loop, and a chip for reducing phase differences at different frequency division ratios.
Background
With the expansion of the demands of domestic data centers, vehicle-mounted electronic chips and other chips, many clock chips, interface chips and the like are needed. The phase-locked loop is used as a necessary system for signal processing, and has wide application, wherein any frequency division mode of a Spread Spectrum Clock (SSC) is supported, the frequency division mode is a place with a relatively large application scene, and a multi-mode frequency divider (MMD) provides a comparison clock for a frequency-discrimination phase detector (PFD) to compare and output up-down pulse signals after frequency division of a voltage-controlled oscillator (VCO).
The multimode divider needs to support the division frequency required by the DSM (Delta Sigma modulation) module to achieve the fractional division and spread spectrum clock, but any fractional division causes corresponding problems: when the frequency division is switched, phase differences occur in different frequency division ratios, so that jitter increases, and the requirement of PCIE5.0 cannot be met.
Disclosure of Invention
In order to solve the above problems, the present invention provides a multi-mode frequency divider, a phase-locked loop and a chip for reducing the phase difference between the integer frequency division ratio and the fractional frequency division ratio, thereby avoiding the glitch and the influence on the jitter.
The technical scheme adopted by the invention is as follows:
a multi-mode frequency divider for reducing phase difference of different frequency dividing ratios comprises a multi-stage two/three frequency divider, a delay circuit, an inverter, a multiplexer, a buffer and a D-type trigger; the multistage two/three frequency dividers are connected in series, and the first stage two/three frequency dividers are electrically connected with an external signal input end; the signal input end of the delay circuit is electrically connected with the signal output end of the penultimate two/three frequency divider, the signal input end of the inverter is electrically connected with the signal output end of the final two/three frequency divider, the signal output ends of the delay circuit and the inverter are electrically connected with the signal input end of the multiplexer, the signal output end of the multiplexer is electrically connected with the buffer, and the buffer is electrically connected with the external signal output end; the D-type trigger is electrically connected with each stage of the two/three frequency dividers and performs sampling integration, so that control signals of each stage of the two/three frequency dividers are synchronously switched to avoid burrs; the delay circuit is configured to compensate for an excess delay of the final divide-by-two/three divider to compensate for a phase difference between an integer divide ratio and a fractional divide ratio produced by the multi-stage divide-by-two/three divider.
Further, the delay circuit comprises a two-stage built-in buffer and a two-stage built-in inverter, wherein a first-stage built-in buffer, a second-stage built-in buffer, the first-stage built-in inverter and the second-stage built-in inverter are sequentially and electrically connected, the first-stage built-in buffer is electrically connected with a signal output end of the penultimate two/three frequency divider, and the second-stage built-in inverter is electrically connected with a signal input end of the multiplexer.
A charge pump phase locked loop with spread spectrum clock function includes the multi-modulus divider that reduces phase difference between different division ratios.
Further, the charge pump phase-locked loop further comprises a frequency-discrimination phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, an output frequency divider, a spread spectrum clock circuit and a Delta-Sigma modulation circuit, wherein the frequency-discrimination phase detector, the charge pump, the loop filter, the voltage-controlled oscillator and the output frequency divider are sequentially and electrically connected, the multi-mode frequency divider is respectively and electrically connected with the frequency-discrimination phase detector, the voltage-controlled oscillator and the Delta-Sigma modulation circuit, and the spread spectrum clock circuit is electrically connected with the Delta-Sigma modulation circuit.
A clock chip comprising the charge pump phase-locked loop with spread spectrum clock function.
An interface chip comprises the charge pump phase-locked loop with a spread spectrum clock function.
A phase locked loop includes the multi-modulus divider that reduces the phase difference of different division ratios.
A clock chip comprising the phase locked loop.
An interface chip includes the phase-locked loop.
The invention has the beneficial effects that:
1. the invention can reduce the phase difference between the integer frequency division ratio and the decimal frequency division ratio, thereby avoiding burrs and avoiding the influence on jitter;
2. the invention integrates the sampling with the two/three frequency dividers of each stage through the D-type trigger, and ensures the synchronous switching of the control signals of the two/three frequency dividers of each stage, thereby avoiding the generation of burrs;
3. the invention compensates the redundant delay of the final-stage two/three frequency divider through the delay circuit, thereby compensating the phase difference between the integer frequency division ratio and the decimal frequency division ratio generated by the multi-stage two/three frequency divider, and avoiding the new problem possibly caused by the complex structure.
Drawings
FIG. 1 is a schematic diagram of a conventional divide-by-two/three circuit.
FIG. 2 is a schematic diagram of a conventional divide-by-two circuit.
FIG. 3 is a schematic diagram of a conventional divide by three circuit waveform.
Fig. 4 is a schematic diagram of an integer and fractional division ratio circuit waveform.
Fig. 5 is a schematic diagram of a multi-modulus divider for reducing phase difference of different division ratios according to embodiment 1 of the present invention.
Fig. 6 is a waveform diagram of a D-type flip-flop of embodiment 1 of the present invention.
Fig. 7 is a schematic diagram of the internal frame of the delay circuit of embodiment 1 of the present invention.
Fig. 8 is a waveform diagram of a delay circuit according to embodiment 1 of the present invention.
Fig. 9 is a waveform diagram of the output detection and automatic adjustment of the output impedance of embodiment 1 of the present invention.
Fig. 10 is a block diagram of a charge pump pll implementation with spread spectrum clock SSC function according to embodiment 2 of the present invention.
Reference numerals: a ctl-control signal, a cko-clock signal, a div 23-di/tri-divider, a mux-multiplexer, an inv-inverter, a Delay-Delay circuit, a Buf-buffer, a dff-D type flip-flop; the circuit comprises a PFD-phase frequency detector, a CP-charge pump, an LPF-loop filter, a VCO-voltage controlled oscillator, a div-output frequency divider, a mmd-multi-mode frequency divider, an SSC-spread spectrum clock circuit and a DSM-Delta-Sigma modulation circuit.
Detailed Description
Specific embodiments of the present invention will now be described in order to provide a clearer understanding of the technical features, objects and effects of the present invention. It should be understood that the particular embodiments described herein are illustrative only and are not intended to limit the invention, i.e., the embodiments described are merely some, but not all, of the embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Example 1
Fig. 1 is a schematic diagram of a conventional divide-by-two/three circuit, wherein when the control signal ctl=0, the divide-by-two/three divider div23 is in a divide-by-two mode; when the control signal ctl=1, the divide-by-two/divide-by-three divider div23 is in the divide-by-three mode. 3 divide-by-two/three dividers div23 are omitted from fig. 1, and a total of 7 divide-by-two/three dividers div23 are omitted, wherein when the control signal ctl <6:0> = 0111111, the output division ratio is 63; when the control signal ctl <6:0> =1000000, the output frequency division ratio is 64 frequency division.
As shown in fig. 1-4, there is a D-like flip-flop circuit inside the divide-by-63 and divide-by-64, which has the effect that there is a phase difference that is produced by a D-like flip-flop when the divide ratio is 63 and the divide ratio is 64.
As shown in fig. 5, the present embodiment provides a multi-modulus divider for reducing phase difference of different division ratios, which includes a multi-stage divide-by-two/three divider, a delay circuit, an inverter, a multiplexer, a buffer, and a D-type flip-flop; the multistage two/three frequency dividers are connected in series, and the first stage two/three frequency dividers are electrically connected with an external signal input end; the signal input end of the delay circuit is electrically connected with the signal output end of the penultimate two/three frequency divider, the signal input end of the inverter is electrically connected with the signal output end of the final two/three frequency divider, the signal output ends of the delay circuit and the inverter are electrically connected with the signal input end of the multiplexer, the signal output end of the multiplexer is electrically connected with the buffer, and the buffer is electrically connected with the external signal output end.
The D-type flip-flop is electrically connected to each stage of the divide-by-two/three frequency dividers and performs sampling integration, so that the control signals of each stage of the divide-by-two/three frequency dividers are synchronously switched to avoid generating glitches, as shown in fig. 6, which is a waveform schematic diagram of the D-type flip-flop. The delay circuit is configured to compensate for an excess delay of the final divide-by-two/three divider to compensate for a phase difference between an integer divide ratio and a fractional divide ratio produced by the multiple divide-by-two/three divider.
Preferably, as shown in fig. 7, the delay circuit includes a two-stage built-in buffer and a two-stage built-in inverter, wherein a first-stage built-in buffer, a second-stage built-in buffer, a first-stage built-in inverter, and a second-stage built-in inverter are electrically connected in this order, the first-stage built-in buffer is electrically connected to a signal output terminal of the penultimate two/three frequency divider, and the second-stage built-in inverter is electrically connected to a signal input terminal of the multiplexer. Fig. 7 shows a waveform diagram of the delay circuit.
As can be seen from fig. 5 to 9, the delay of the divide-by-two/three frequency divider between cko <1> and cko <0> can be reduced by a delay circuit that compensates for the excess delay of the final divide-by-two/three frequency divider by a built-in buffer. Where cko <0>, cko <1>, and out, the waveform results are shown in FIG. 8.
Example 2
This example is based on example 1:
the present embodiment provides a charge pump phase locked loop with spread spectrum clock function, including the multi-modulus divider of embodiment 1 for reducing phase difference between different division ratios.
Preferably, as shown in fig. 10, the charge pump phase-locked loop further includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, an output frequency divider, a spread spectrum clock circuit, and a Delta-Sigma modulation circuit, where the phase frequency detector, the charge pump, the loop filter, the voltage controlled oscillator, and the output frequency divider are electrically connected in sequence, and the multi-modulus frequency divider is electrically connected to the phase frequency detector, the voltage controlled oscillator, and the Delta-Sigma modulation circuit, respectively, and the spread spectrum clock circuit is electrically connected to the Delta-Sigma modulation circuit. The multimode frequency divider, the spread spectrum clock circuit and the Delta-Sigma modulation circuit jointly realize the spread spectrum function.
Example 3
This example is based on example 2:
the present embodiment provides a clock chip including the charge pump phase locked loop with spread spectrum clock function of embodiment 2.
Example 4
This example is based on example 2:
the present embodiment provides an interface chip including the charge pump pll with spread spectrum clock function of embodiment 2.
Example 5
This example is based on example 1:
the present embodiment provides a phase locked loop including the multi-modulus divider of embodiment 1 that reduces the phase difference between different division ratios.
Example 6
This example is based on example 5:
the present embodiment provides a clock chip including the phase-locked loop of embodiment 5.
Example 7
This example is based on example 5:
the present embodiment provides an interface chip including the phase-locked loop of embodiment 5.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.

Claims (9)

1. A multi-mode frequency divider for reducing phase difference of different frequency dividing ratios, which is characterized by comprising a multi-stage two/three frequency divider, a delay circuit, an inverter, a multiplexer, a buffer and a D-type trigger; the multistage two/three frequency dividers are connected in series, and the first stage two/three frequency dividers are electrically connected with an external signal input end; the signal input end of the delay circuit is electrically connected with the signal output end of the penultimate two/three frequency divider, the signal input end of the inverter is electrically connected with the signal output end of the final two/three frequency divider, the signal output ends of the delay circuit and the inverter are electrically connected with the signal input end of the multiplexer, the signal output end of the multiplexer is electrically connected with the buffer, and the buffer is electrically connected with the external signal output end;
the D-type trigger is electrically connected with each stage of the two/three frequency dividers and performs sampling integration, so that control signals of each stage of the two/three frequency dividers are synchronously switched to avoid burrs; the delay circuit is configured to compensate for an excess delay of the final divide-by-two/three divider to compensate for a phase difference between an integer divide ratio and a fractional divide ratio produced by the multi-stage divide-by-two/three divider.
2. The multi-modulus divider for reducing phase difference at different division ratios according to claim 1, wherein the delay circuit comprises a two-stage built-in buffer and a two-stage built-in inverter, wherein a first-stage built-in buffer, a second-stage built-in buffer, a first-stage built-in inverter and a second-stage built-in inverter are electrically connected in this order, the first-stage built-in buffer is electrically connected to a signal output terminal of a penultimate divide-by-two/three divider, and the second-stage built-in inverter is electrically connected to a signal input terminal of the multiplexer.
3. A charge pump phase locked loop having spread spectrum clock function comprising a multi-modulus divider for reducing phase difference at different division ratios as claimed in claim 1 or 2.
4. The charge pump phase-locked loop with spread spectrum clock function as recited in claim 3, further comprising a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, an output frequency divider, a spread spectrum clock circuit, and a Delta-Sigma modulation circuit, wherein the phase frequency detector, the charge pump, the loop filter, the voltage controlled oscillator, and the output frequency divider are electrically connected in sequence, and wherein the multi-modulus frequency divider is electrically connected to the phase frequency detector, the voltage controlled oscillator, and the Delta-Sigma modulation circuit, respectively, and the spread spectrum clock circuit is electrically connected to the Delta-Sigma modulation circuit.
5. A clock chip comprising a charge pump phase locked loop with spread spectrum clock function as claimed in claim 3 or 4.
6. An interface chip comprising a charge pump phase locked loop with spread spectrum clock function as claimed in claim 3 or 4.
7. A phase locked loop comprising a multi-modulus divider for reducing phase difference at different division ratios as claimed in claim 1 or 2.
8. A clock chip comprising the phase locked loop of claim 7.
9. An interface chip comprising the phase-locked loop of claim 7.
CN202310564237.1A 2023-05-18 2023-05-18 Multimode frequency divider, phase-locked loop and chip for reducing phase difference of different frequency division ratios Active CN116647233B (en)

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