CN117997336A - Phase-locked loop and signal delay processing method - Google Patents

Phase-locked loop and signal delay processing method Download PDF

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Publication number
CN117997336A
CN117997336A CN202211379473.8A CN202211379473A CN117997336A CN 117997336 A CN117997336 A CN 117997336A CN 202211379473 A CN202211379473 A CN 202211379473A CN 117997336 A CN117997336 A CN 117997336A
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China
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delay
circuit
input control
clock signal
control codeword
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Inventor
陶婷婷
毛懿鸿
田洪亮
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN202211379473.8A priority Critical patent/CN117997336A/en
Priority to PCT/CN2023/103485 priority patent/WO2024093297A1/en
Publication of CN117997336A publication Critical patent/CN117997336A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop

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Abstract

The application provides a phase-locked loop and a signal delay processing method, wherein after a first delay circuit receives a reference clock signal and a first input control code word input by external equipment, the signal delay processing is carried out on the reference clock signal based on the first input control code word; after receiving the feedback clock signal and the first input control code word fed back by the negative feedback circuit based on the phase-locked loop through the second delay circuit, performing signal delay processing on the feedback clock signal based on the difference value between the first input control code word and the maximum control code word of the digital clock converter. The two paths of delay circuits respectively perform signal delay processing by ensuring the same delay precision of the two paths of delay circuits and determining a first input control code word by utilizing a feedback frequency divider in the negative feedback circuit based on the phase of a reference clock signal and the phase of a feedback clock signal, so that the problems of eliminating the power supply memory effect of the digital clock converter circuit and reducing the sensitivity of the digital clock converter circuit to power supply noise are solved.

Description

Phase-locked loop and signal delay processing method
Technical Field
The present application relates to the field of wireless communications technologies, and in particular, to a phase locked loop and a signal delay processing method.
Background
In wireless communication systems, frequency synthesizers based on a phase locked loop (phase locked loop, PLL) architecture are widely used to provide local oscillator signals. In data transmission systems, it is also common to provide a sampling clock based on a phase locked loop structure. The quality of the communication signal is directly influenced or the transmission quality of the data is influenced based on the quality of the clock signal output by the phase-locked loop structure.
In all-digital phase-locked loops (ALL DIGITAL PHASE pocked poop, ADPLL) and analog phase-locked loops (analog phase pocked poop, APLL), a frequency multiplier is typically used to boost the frequency of the reference clock, thereby enhancing the phase noise performance of the phase-locked loop output. In order to obtain a more accurate output frequency, a fractional frequency division technique is generally adopted, and an instantaneous frequency division value of a frequency multiplier is adjusted through a sigma-delta modulator (SIGMA DELTA module, SDM), so that the fractional frequency division is obtained. However, the application of SDM generates large quantization noise, and also causes a problem of fractional spurs (fractional spurs) in the output signal.
To solve the above problem caused by SDM, a digital-to-time converter (digital to time converter, DTC) circuit is generally added, and the delay of the DTC circuit is controlled by adjusting the input control code word of the DTC. However, in the prior art, the delay coverage of the DTC circuit is larger, the device noise and the power consumption of the DTC circuit are both increased along with the increase of the delay, and different power supply ripples can be caused by different delays, so that the whole circuit has a stronger power supply memory effect, and the quality of the output signal of the phase-locked loop is affected.
Disclosure of Invention
In view of the above, the present application provides a phase locked loop and a signal delay processing method, so as to eliminate the power memory effect of the digital clock converter circuit and reduce the sensitivity of the digital clock converter circuit to power noise.
In a first aspect, the present application provides a phase locked loop comprising at least: a digital clock converter circuit and a negative feedback circuit; wherein the digital clock converter circuit comprises: a first delay circuit and a second delay circuit; the delay precision of the first delay circuit and the delay precision of the second delay circuit are the same; the first delay circuit is used for receiving a reference clock signal and a first input control code word which are input by external equipment; performing signal delay processing on the reference clock signal based on the first input control codeword; the second delay circuit is used for receiving a feedback clock signal fed back by the negative feedback circuit based on the phase-locked loop and the first input control code word; performing signal delay processing on the feedback clock signal based on a difference value between the first input control codeword and a maximum control codeword of the digital clock converter; wherein the first input control codeword is determined by a feedback divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal.
Compared with the prior art, the application can obtain the first input control code word by utilizing the feedback frequency divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal under the condition of ensuring the same delay precision of the two paths of delay circuits, so that the two paths of coupled delay circuits respectively perform signal delay processing on the reference clock signal and the feedback clock signal, thereby realizing the elimination of the power memory effect of the digital clock converter circuit and reducing the sensitivity of the digital clock converter circuit to power noise.
In one possible design, the first delay circuit includes at least one first delay cell; each first delay unit is connected in series; the signal delay processing is performed on the reference clock signal based on the first input control codeword, and specifically is used for: determining a number of the first delay cells based on the first input control codeword; and carrying out signal delay processing on the reference clock signal by using the first delay units with the determined number. Wherein the total number of first delay units is determined based on a maximum control codeword of the digital clock converter.
The number of the first delay units can be accurately determined by setting the size of the first input control code word, and then signal adjustment is accurately performed on the reference clock signal.
In one possible design, the second delay circuit includes at least one second delay cell; each second delay unit is connected in series; the signal delay processing is performed on the feedback clock signal based on a difference value between the first input control codeword and a maximum control codeword of the digital clock converter, and the signal delay processing is specifically configured to: determining the number of the second delay units based on a difference between the first input control codeword and a maximum control codeword of the digital clock converter; and carrying out signal delay processing on the feedback clock signal by using the determined number of second delay units. Wherein the total number of second delay units is determined based on a maximum control codeword of the digital clock converter.
The number of the second delay units can be accurately determined by setting the size of the first input control code word, and then the feedback clock signal is accurately subjected to signal adjustment.
In one possible design, the first delay circuit includes a first drive unit, a second drive unit, a first resistor, and a first adjustable capacitance; the first end of the first driving unit is connected with the first end of the first resistor, the second end of the first resistor is connected with the first end of the second driving unit and the first end of the first adjustable capacitor, the second end of the first adjustable capacitor is grounded, the second end of the first driving unit is the input end of the first delay circuit, and the second end of the second driving unit is the output end of the first delay circuit; the signal delay processing is performed on the reference clock signal based on the first input control codeword, and specifically is used for: determining a first capacitance value of the first tunable capacitance based on the first input control codeword; and performing signal delay processing on the reference clock signal by using the first driving unit, the first resistor, the first capacitance value and the second driving unit. Wherein the capacitance value adjustment range of the first adjustable capacitance is determined based on a maximum control codeword of the digital clock converter.
By setting the size of the first input control code word, the capacitance value of the first adjustable capacitor can be accurately determined, and further signal adjustment is accurately performed on the reference clock signal.
In one possible design, the second delay circuit includes a third drive unit, a fourth drive unit, a second resistor, and a second adjustable capacitance; the first end of the third driving unit is connected with the first end of the second resistor, the second end of the second resistor is connected with the first end of the fourth driving unit and the first end of the second adjustable capacitor, the second end of the second adjustable capacitor is grounded, the second end of the third driving unit is the input end of the second delay circuit, and the second end of the fourth driving unit is the output end of the second delay circuit; the signal delay processing is performed on the feedback clock signal based on a difference value between the first input control codeword and a maximum control codeword of the digital clock converter, and the signal delay processing is specifically configured to: determining a second capacitance value of the second adjustable capacitance based on a difference between the first input control codeword and a maximum control codeword of the digital clock converter; and performing signal delay processing on the feedback clock signal by using the third driving unit, the second resistor, the second capacitance value and the fourth driving unit. Wherein the capacitance value adjustment range of the second adjustable capacitance is determined based on a maximum control codeword of the digital clock converter.
The capacitance value of the second adjustable capacitor can be accurately determined by setting the size of the first input control code word, and then the feedback clock signal is accurately subjected to signal adjustment.
In one possible design, the first input control codeword is any value from zero to the maximum control codeword of the digital clock converter.
By setting the size of the first input control code word, the signal delay processing can be further performed on the reference clock signal and the feedback clock signal by accurately utilizing two paths of coupled delay circuits.
In one possible design, the maximum control codeword is a, the offset control codeword is a/2, and the second input control codeword is any value (-a/2, a/2); a is a positive integer; the first delay circuit is further configured to perform signal delay processing on the reference clock signal based on a result of adding the second input control codeword and the offset control codeword; the second delay circuit is further configured to perform signal delay processing on the feedback clock signal based on a difference between the second input control codeword and the offset control codeword.
The application sets the same offset control code word for the two mutually coupled delay circuits, and ensures that the input control code words of the two mutually coupled delay circuits are opposite in number, thereby obtaining different realization modes of signal delay adjustment for the reference clock signal and the feedback clock signal by the two delay circuits respectively.
In a second aspect, the present application provides a chip comprising a phase locked loop as in the first aspect and any one of its designs; the digital clock converter circuit and the negative feedback circuit in the phase-locked loop are integrated on the same chip.
In a third aspect, the present application provides an electronic device comprising: a circuit board and a chip as in the second aspect and any one of the designs thereof, the chip being disposed on the circuit board.
In a fourth aspect, the present application provides a signal delay processing method applied to the phase-locked loop as set forth in the first aspect and any one of the designs thereof, the method comprising: after receiving a reference clock signal and a first input control code word input by external equipment, a first delay circuit carries out signal delay processing on the reference clock signal based on the first input control code word; after receiving a feedback clock signal and the first input control code word fed back by the negative feedback circuit of the phase-locked loop, the second delay circuit carries out signal delay processing on the feedback clock signal based on the difference value between the first input control code word and the maximum control code word of the digital clock converter; the delay precision of the first delay circuit is the same as that of the second delay circuit, and the first input control code word is determined by a feedback frequency divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal.
In one possible design, the first delay circuit includes at least one first delay cell; the first delay circuit performs signal delay processing on the reference clock signal based on the first input control codeword, and includes: the first delay circuit determines the number of the first delay cells based on the first input control codeword; and carrying out signal delay processing on the reference clock signal by using the first delay units with the determined number.
In one possible design, the total number of first delay units is determined based on a maximum control codeword of the digital clock converter.
In one possible design, the second delay circuit includes at least one second delay cell; the second delay circuit performs signal delay processing on the feedback clock signal based on a difference value between the first input control codeword and a maximum control codeword of the digital clock converter, and includes: the second delay circuit determines the number of the second delay units based on a difference value between the first input control codeword and a maximum control codeword of the digital clock converter; and carrying out signal delay processing on the feedback clock signal by using the determined number of second delay units.
In a possible design, the total number of second delay units is determined based on a maximum control codeword of the digital clock converter.
In one possible design, the first delay circuit includes a first drive unit, a second drive unit, a first resistor, and a first adjustable capacitance; the first delay circuit performs signal delay processing on the reference clock signal based on the first input control codeword, and includes: the first delay circuit determines a first capacitance value of the first tunable capacitance based on the first input control codeword; and performing signal delay processing on the reference clock signal by using the first driving unit, the first resistor, the first capacitance value and the second driving unit.
In one possible design, the capacitance value adjustment range of the first adjustable capacitance is determined based on a maximum control codeword of the digital clock converter.
In one possible design, the second delay circuit includes a third drive unit, a fourth drive unit, a second resistor, and a second adjustable capacitance; the second delay circuit performs signal delay processing on the feedback clock signal based on a difference value between the first input control codeword and a maximum control codeword of the digital clock converter, and includes: the second delay circuit determines a second capacitance value of the second adjustable capacitance based on a difference value of the first input control codeword and a maximum control codeword of the digital clock converter; and performing signal delay processing on the feedback clock signal by using the third driving unit, the second resistor, the second capacitance value and the fourth driving unit.
In one possible design, the capacitance value adjustment range of the second adjustable capacitance is determined based on a maximum control codeword of the digital clock converter.
In one possible design, the maximum control codeword is a, the offset control codeword is a/2, and the second input control codeword is any value (-a/2, a/2); a is a positive integer; the method further comprises the steps of: the first delay circuit performs signal delay processing on the reference clock signal based on the addition result of the second input control code word and the offset control code word; the second delay circuit performs signal delay processing on the feedback clock signal based on a difference value between the second input control codeword and the offset control codeword.
In a fifth aspect, the present application provides a computer readable storage medium storing computer instructions which, when executed by a digital clock converter circuit, cause the digital clock converter circuit to perform the method of any of the designs of the fourth aspect above.
In a sixth aspect, the application provides a computer program product comprising computer instructions which, when executed by a digital clock converter circuit, cause the digital clock converter circuit to perform the method of any of the designs of the fourth aspect above.
The technical effects that any one of the second aspect to the sixth aspect may be designed to achieve are described with reference to any one of the first aspect, and the description thereof is not repeated here.
Drawings
Fig. 1 is a schematic structural diagram of an all-digital phase-locked loop system according to an embodiment of the present application;
Fig. 2 is a schematic diagram of a digital clock converter circuit according to an embodiment of the present application;
Fig. 3 is a schematic diagram of a reference clock signal fref_in, a feedback clock signal fdiv_in, and delayed signals fref_out and fdiv_out according to an embodiment of the present application;
fig. 4a is a schematic diagram of a correspondence relationship between an operating current of a digital clock converter circuit and a first input control codeword according to an embodiment of the present application;
FIG. 4b is a schematic diagram showing the correspondence between the working current of the digital clock converter circuit and the input control codeword in the prior art;
FIG. 5 is a schematic diagram of a digital clock converter circuit according to an embodiment of the present application;
fig. 6 is a schematic diagram of a correspondence relationship between an operating current of a digital clock converter circuit and a second input control codeword according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a digital clock converter circuit according to an embodiment of the present application;
fig. 8 is a flow chart of a signal delay processing method according to an embodiment of the present application.
Detailed Description
In order to enable a person skilled in the art to better understand the technical solutions of the present application, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in other sequences than those illustrated or otherwise described herein. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
In a wireless communication system, a frequency synthesizer based on a phase-locked loop structure is widely used to provide a local oscillator signal. In data transmission systems, it is also common to provide a sampling clock based on a phase locked loop structure. The quality of the communication signal is directly influenced or the transmission quality of the data is influenced based on the quality of the clock signal output by the phase-locked loop structure.
In all-digital phase-locked loops and analog phase-locked loops, a frequency multiplier is generally adopted to raise the frequency of a reference clock, so that the output phase noise performance of the phase-locked loop is improved. In order to obtain a more accurate output frequency, a fractional frequency division technology is generally adopted, and an instantaneous frequency division value of a frequency multiplier is adjusted through a sigma-delta modulator, so that the fractional frequency division is obtained. The application of SDM, however, produces large quantization noise and also causes fractional spurious problems in the output signal.
To solve the above problem caused by SDM, it is common to add a digital-to-time converter circuit to control the delay of the DTC circuit by adjusting the input control codeword of the DTC. However, in the prior art, the delay coverage of the DTC circuit is larger, the device noise and the power consumption of the DTC circuit are both increased along with the increase of the delay, and different power supply ripples can be caused by different delays, so that the whole circuit has a stronger power supply memory effect, and the quality of the output signal of the phase-locked loop is affected.
In view of the above, the present application provides a phase locked loop and a signal delay processing method. In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings.
The phase-locked loop provided by the application at least comprises: a digital clock converter circuit and a negative feedback circuit, wherein the digital clock converter circuit may include: the delay circuit comprises a first delay circuit and a second delay circuit, and the delay precision of the first delay circuit and the delay precision of the second delay circuit are the same. For example, the digital clock converter circuit may include a two-way coupled delay chain circuit.
Taking an all-digital phase-locked loop as an example for illustration, as shown in fig. 1, the all-digital phase-locked loop system includes: a digital clock converter circuit 101, a clock-to-digital converter (time to digital converter, TDC) 102, a digital loop filter (digital loop filter, DLPF) 103, a digitally controlled oscillator (DIGITALLY CONTROLLED OSCILLATOR, DCO) 104, a feedback divider (feedback divider, NDIV) 105, and an SDM106. Here, the feedback divider 105 and the SDM106 may function as a negative feedback circuit of the all-digital phase-locked loop system.
The reference clock signal fref_in and the feedback clock signal fdiv_in are subjected to signal delay processing by two coupled delay circuits (i.e., the first delay circuit and the second delay circuit described above) in the digital clock converter circuit 101, respectively. The delayed signals corresponding to the reference clock signal fref_in and the feedback clock signal fdiv_in are input to the clock digital converter 102, so that the power memory effect of the digital clock converter circuit 101 is eliminated and the sensitivity problem of the digital clock converter circuit 101 to power noise is reduced in the all-digital phase-locked loop. It should be noted that the phase-locked loop of the present application may also be applied in different application scenarios such as analog phase-locked loop.
Fig. 2 is a schematic diagram illustrating a digital clock converter circuit according to an embodiment of the present application. As shown in fig. 2, the digital clock converter circuit includes: a first delay circuit 201 and a second delay circuit 202. Wherein the delay accuracy of the first delay circuit 201 and the second delay circuit 202 is the same.
The first delay circuit 201, after receiving the reference clock signal (i.e., fref_in in fig. 2) and the first input control codeword (i.e., din in fig. 2) input from the external device, performs signal delay processing on the reference clock signal based on the first input control codeword.
The second delay circuit 202 performs signal delay processing on the feedback clock signal based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter after receiving the feedback clock signal (i.e., fdiv_in in fig. 2) and the first input control codeword fed back by the negative feedback circuit.
Here, the first input control codeword is an arbitrary value among the maximum control codewords of the zero-to-digital clock converter, and the first input control codeword is determined by a feedback divider in the negative feedback circuit based on the phase of the reference clock signal, the phase of the feedback clock signal. Optionally, in the feedback frequency divider of the negative feedback circuit, the phase of the reference clock signal and the phase of the feedback clock signal may be infinitely close according to the quantization noise cancellation algorithm, so as to obtain the first input control codeword. The present application is not limited to a specific manner of determining the first input control codeword, but only one embodiment of determining the first input control codeword is illustrated herein.
For example, assuming that the maximum control codeword of the digital clock converter is Dm, after receiving the reference clock signal fref_in and the first input control codeword Din, the first delay circuit 201 performs signal delay processing on fref_in by using Din to obtain an output signal fref_out of the first delay circuit 201, that is, a signal in which fref_out is delayed by the fref_in signal. After receiving the feedback clock signals fdiv_in and Din, the second delay circuit 202 performs signal delay processing on the fdiv_in by using the difference between Dm and Din, so as to obtain an output signal fdiv_out of the second delay circuit 202, that is, the fdiv_out is a signal delayed by the fdiv_in signal.
In one embodiment, the first delay circuit 201 may include at least one first delay unit, each of which is connected in series. The second delay circuit 202 includes at least one second delay unit, each of which is connected in series.
Example 1a first delay circuit 201 as shown in fig. 2 includes a first delay cell 201-1, first delay cells 201-2, …, a first delay cell 201-n. The first delay units 201-1, 201-2, …, and 201-n are connected in series. The second delay circuit 202 includes a second delay unit 202-1, second delay units 202-2, …, and a second delay unit 202-n, where n is a positive integer. The second delay units 202-1, 202-2, …, 202-n are connected in series.
Wherein the total number of the first delay units and the total number of the second delay units are determined based on a maximum control codeword of the digital clock converter. When the maximum control codeword of the digital clock converter is Dm, the total number of the first delay units and the total number of the second delay units are Dm.
It should be noted that the delay accuracy of the first delay circuit 201 is correlated with the delay accuracy of each of the first delay cells in the first delay circuit 201, and similarly, the delay accuracy of the second delay circuit 202 is correlated with the delay accuracy of each of the second delay cells in the second delay circuit 202. For example, assuming that the delay accuracies of the first delay unit 201-1, the first delay units 201-2, …, the first delay unit 201-n, the second delay unit 202-1, the second delay units 202-2, …, and the second delay unit 202-n are all T0, the delay accuracies of the first delay circuit 201 and the second delay circuit 202 are both T0.
When the first input control codeword Din is any value from zero to the maximum control codeword Dm of the digital clock converter, the signal delay adjustment range that can be realized by the digital clock converter circuit is obtained by inputting different Din. As can be seen from the following equation one, when Din is 0, the signal delay difference between the first delay circuit 201 and the second delay circuit 202 is-dm×t0. When Din is Dm, the signal delay difference between the first delay circuit 201 and the second delay circuit 202 is dm×t0. That is, in the case where Din is within the (0, dm) range, the signal delay adjustment range that can be realized by the digital clock converter circuit is (-dm×t0, dm×t0). Here, tref denotes a signal delay of the first delay circuit 201, tdiv denotes a signal delay of the second delay circuit 202.
Tref-Tdiv =t0×din-t0×dm (Dm-Din) =2t0×din-t0×dm formula one
Alternatively, as shown in fig. 2, in the scenario of the above example 1, the first delay circuit 201 determines the number of first delay units based on the first input control codeword, and then performs signal delay processing on the reference clock signal using the determined number of first delay units. The second delay circuit 202 determines the number of second delay units based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter, and then performs signal delay processing on the feedback clock signal using the determined number of second delay units.
For example, assuming that the first input control codeword Din is 2 and the maximum control codeword Dm of the digital clock converter is 8, the first delay circuit 201 may include 8 first delay cells and the second delay circuit 202 may include 8 second delay cells. As can be seen from Din being 2, the number of first delay units in the normal operation state in the first delay circuit 201 is 2. In the first delay circuit 201, the reference clock signal fref_in is subjected to signal delay processing by 2 first delay units in an operating state, and a delayed signal fref_out is obtained. As can be seen from the difference between Din 2, dm 8, din and Dm, the number of the second delay units in the second delay circuit 202 in the normal operation state is 6. In the second delay circuit 202, the feedback clock signal fdiv_in is subjected to signal delay processing by 6 second delay units in an operating state, and a delayed signal fdiv_out is obtained. Fig. 3 shows a schematic diagram of the reference clock signal fref_in, the feedback clock signal fdiv_in, and the delay processed signals fref_out, fdiv_out.
As can be seen from the above description, assuming that the maximum control codeword of the digital clock converter is Dm, when the first delay circuit 201 and the second delay circuit 202 in the digital clock converter circuit perform the signal delay processing simultaneously, the total number of the first delay units operating in the first delay circuit 201 and the second delay units operating in the second delay circuit 202 is constant to Dm. If the working current of each first delay unit and each second delay unit is i0, the working current of the digital clock converter circuit is Dm x i0 and is kept constant. Therefore, the influence on the power supply is kept consistent in the working process of the digital clock converter circuit, and the memory effect of the power supply is effectively eliminated. Fig. 4a shows a schematic diagram of a correspondence between an operating current of a digital clock converter circuit and a first input control codeword according to an embodiment of the present application, and fig. 4b shows a schematic diagram of a correspondence between an operating current of a digital clock converter circuit and an input control codeword according to the prior art. As can be seen from fig. 4a and fig. 4b, compared to the prior art in which the operating current of the digital clock converter circuit varies within the range of (0, 2dm×i0), the present application achieves the elimination of the power memory effect problem by maintaining the constant current dm×i0.
In addition, the power supply noise in the digital clock converter circuit is in a common mode form, and thus the digital clock converter circuit is insensitive to the power supply noise. Assuming that the gain of each first delay unit and each second delay unit to the power supply noise is a and the low frequency noise of the power supply is σ 2, the noise difference between the first delay circuit 201 and the second delay circuit 202 is as shown in the following formula two. That is, compared to the prior art in which the maximum output noise of the digital clock converter circuit is 2dm×a×σ 2, the present application can also reduce the output noise of the digital clock converter circuit.
(Dm-Din) a σ 2-Din*A*σ2＝(Dm-2Din)*A*σ2 formula two
Under the condition that the delay precision of the two paths of delay circuits is the same, the first input control code word can be obtained by utilizing the feedback frequency divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal, so that the two paths of coupled delay circuits respectively perform signal delay processing on the reference clock signal and the feedback clock signal, and further the problems of eliminating the power supply memory effect of the digital clock converter circuit and reducing the sensitivity of the digital clock converter circuit to the power supply noise are realized.
Optionally, in the scenario of example 1 above, another implementation manner in which two mutually coupled delay circuits perform signal delay adjustment on the reference clock signal and the feedback clock signal respectively is described further: assuming that the maximum control codeword is a, the offset control codeword is a/2, and the second input control codeword is any value in (-a/2, a/2), the first delay circuit 201 performs signal delay processing on the reference clock signal based on the addition result of the second input control codeword and the offset control codeword; the second delay circuit 202 performs signal delay processing on the feedback clock signal based on the difference between the second input control codeword and the offset control codeword. Here, a is a positive integer.
As illustrated in fig. 5, it is assumed that the first delay circuit 201 includes a first delay unit 201-1, a first delay unit 201-2, a first delay unit 201-3, and a first delay unit 201-4, and the second delay circuit 202 includes a second delay unit 202-1, a second delay unit 202-2, a second delay unit 202-3, and a second delay unit 202-4.
When the maximum control code word is A, the offset control code word is A/2, and the second input control code word D 'in is any value in (-A/2, A/2), the signal delay adjustment range which can be realized by the digital clock converter circuit is obtained by inputting different D' in. As can be seen from the following equation three, when D' in is-a/2, the signal delay difference between the first delay circuit 201 and the second delay circuit 202 is-a×t0. When D' in is a/2, the signal delay difference between the first delay circuit 201 and the second delay circuit 202 is a×t0. That is, in the case where D' in is within the (-a/2, a/2) range, the digital clock converter circuit can realize a signal delay adjustment range of (-a×t0, a×t0). Here, T 'ref represents the signal delay of the first delay circuit 201, and T' div represents the signal delay of the second delay circuit 202.
T ' ref-T ' div=t0 (D ' in+a/2) -T0 (a/2-D ' in) =2t0D ' in equation three
As can be seen from the above description, when the first delay unit 201-1 and the first delay unit 201-2 in the first delay circuit 201 are in the operating state, the second delay unit 202-1 and the second delay unit 202-2 in the second delay circuit 202 are in the operating state. That is, the total number of the first delay units operating in the first delay circuit 201 and the second delay units operating in the second delay circuit 202 is constant to 4, and the constant current a×i0 can be maintained, so as to solve the problem of power memory effect. Fig. 6 is a schematic diagram showing a correspondence relationship between an operating current of a digital clock converter circuit and a second input control codeword according to an embodiment of the present application.
Likewise, the power supply noise in the digital clock converter circuit shown in fig. 5 is in a common mode form and is therefore insensitive to power supply noise.
In another embodiment of the present application, the above-mentioned scheme may be implemented by other internal structural connection manners of the first delay circuit 201 and the second delay circuit 202.
In one possible implementation, as shown in fig. 7, the first delay circuit 201 may include a first driving unit 203, a second driving unit 204, a first resistor 205, and a first tunable capacitor 206. The second delay circuit 202 includes a third drive unit 207, a fourth drive unit 208, a second resistor 209, and a second tunable capacitor 2020. Wherein, the capacitance value adjustment range of the first tunable capacitor 206 and the capacitance value adjustment range of the second tunable capacitor 2020 are determined based on the maximum control codeword of the digital clock converter.
The first end of the first driving unit 203 is connected to the first end of the first resistor 205, the second end of the first resistor 205 is connected to the first end of the second driving unit 204 and the first end of the first adjustable capacitor 206, the second end of the first adjustable capacitor 206 is grounded, the second end of the first driving unit 203 is the input end of the first delay circuit 201, and the second end of the second driving unit 204 is the output end of the first delay circuit 201. The first end of the third driving unit 207 is connected to the first end of the second resistor 209, the second end of the second resistor 209 is connected to the first end of the fourth driving unit 208 and the first end of the second adjustable capacitor 2020, the second end of the second adjustable capacitor 2020 is grounded, the second end of the third driving unit 207 is the input end of the second delay circuit 202, and the second end of the fourth driving unit 208 is the output end of the second delay circuit 202.
After determining the first capacitance value of the first adjustable capacitor 206 based on the first input control codeword, the signal delay processing is performed on the reference clock signal by using the first capacitance values of the first driving unit 203, the second driving unit 204, the first resistor 205 and the first adjustable capacitor 206. After determining the second capacitance value of the second adjustable capacitor 2020 based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter, the feedback clock signal is subjected to signal delay processing by using the second capacitance values of the third driving unit 207, the fourth driving unit 208, the second resistor 209 and the second adjustable capacitor 2020. The schematic diagram of the signal delay process may refer to fig. 3, and will not be described herein.
When the first input control codeword Din is any value from zero to the maximum control codeword Dm of the digital clock converter, the signal delay adjustment range that can be realized by the digital clock converter circuit is obtained by inputting different Din. Specific implementation may refer to a corresponding description of the above formula, and will not be described herein.
Assuming that the maximum control codeword of the digital clock converter is Dm, the capacitance adjustment range of the first adjustable capacitor 206 and the capacitance adjustment range of the second adjustable capacitor 2020 may be (C1, C2), and C2 is greater than C1. When the first delay circuit 201 and the second delay circuit 202 in the digital clock converter circuit perform the signal delay processing simultaneously, the first capacitance value of the first adjustable capacitor 206 in the first delay circuit 201 and the second capacitance value of the second adjustable capacitor 2020 in the second delay circuit 202 remain constant. If the operating currents of the first driving unit 203, the second driving unit 204, the first resistor 205, the third driving unit 207, the fourth driving unit 208, and the second resistor 209 are all i0, the operating current of the digital clock converter circuit is dm×i0, and remains constant. Therefore, the influence on the power supply is kept consistent in the working process of the digital clock converter circuit, and the memory effect of the power supply is effectively eliminated.
Likewise, the power supply noise in the digital clock converter circuit shown in fig. 7 is in a common mode form and is therefore insensitive to power supply noise.
Based on the above-mentioned phase-locked loop embodiment, the embodiment of the present application further provides a signal delay processing method, which is applied to the phase-locked loop, and the method can be executed by the digital clock converter circuit 101 in fig. 1. As shown in fig. 8, the method provided by the application comprises the following steps:
S801: after receiving a reference clock signal and a first input control code word input by external equipment, the first delay circuit performs signal delay processing on the reference clock signal based on the first input control code word;
S802: after receiving a feedback clock signal and a first input control code word fed back by a negative feedback circuit of the phase-locked loop, the second delay circuit carries out signal delay processing on the feedback clock signal based on the difference value between the first input control code word and the maximum control code word of the digital clock converter;
The delay precision of the first delay circuit is the same as that of the second delay circuit, and the first input control code word is determined by a feedback frequency divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal.
In one possible design, the first delay circuit includes at least one first delay cell;
in step S801, the first delay circuit performs signal delay processing on the reference clock signal based on the first input control codeword, including:
the first delay circuit determines the number of first delay cells based on the first input control codeword;
the reference clock signal is subjected to signal delay processing by using a determined number of first delay units.
In one possible design, the total number of first delay units is determined based on the largest control codeword of the digital clock converter.
In one possible design, the second delay circuit includes at least one second delay cell;
In step S802, the second delay circuit performs signal delay processing on the feedback clock signal based on a difference between the first input control codeword and a maximum control codeword of the digital clock converter, including:
The second delay circuit determines the number of second delay units based on the difference between the first input control code word and the maximum control code word of the digital clock converter;
and performing signal delay processing on the feedback clock signal by using the determined number of second delay units.
In one possible design, the total number of second delay units is determined based on the largest control codeword of the digital clock converter.
In one possible design, the first delay circuit includes a first drive unit, a second drive unit, a first resistor, and a first adjustable capacitance;
in step S801, the first delay circuit performs signal delay processing on the reference clock signal based on the first input control codeword, including:
The first delay circuit determines a first capacitance value of the first adjustable capacitance based on the first input control codeword;
And performing signal delay processing on the reference clock signal by using the first driving unit, the first resistor, the first capacitance value and the second driving unit.
In one possible design, the capacitance value adjustment range of the first adjustable capacitance is determined based on a maximum control codeword of the digital clock converter.
In one possible design, the second delay circuit includes a third drive unit, a fourth drive unit, a second resistor, and a second adjustable capacitance;
In step S802, the second delay circuit performs signal delay processing on the feedback clock signal based on a difference between the first input control codeword and a maximum control codeword of the digital clock converter, including:
The second delay circuit determines a second capacitance value of the second adjustable capacitor based on a difference value between the first input control codeword and a maximum control codeword of the digital clock converter;
And performing signal delay processing on the feedback clock signal by using the third driving unit, the second resistor, the second capacitance value and the fourth driving unit.
In one possible design, the capacitance value adjustment range of the second adjustable capacitance is determined based on a maximum control codeword of the digital clock converter.
In one possible design, the maximum control codeword is A, the offset control codeword is A/2, and the second input control codeword is any of (-A/2, A/2); a is a positive integer; the method further comprises the steps of:
the first delay circuit performs signal delay processing on the reference clock signal based on the addition result of the second input control code word and the offset control code word;
the second delay circuit performs signal delay processing on the feedback clock signal based on a difference value between the second input control codeword and the offset control codeword.
In one embodiment of the present application, a chip is provided, including a pll in any of the above possible designs; the digital clock converter circuit and the negative feedback circuit in the phase-locked loop are integrated on the same chip.
In an embodiment of the present application, there is also provided an electronic device including: the circuit board and the chips in any of the above possible designs are disposed on the circuit board.
Embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when executed by a digital clock converter circuit, cause the signal delay processing method shown in fig. 8 to be performed.
Embodiments of the present application also provide a computer program product comprising computer instructions which, when executed by a digital clock converter circuit, cause the signal delay processing method shown in fig. 8 to be performed.
That is, aspects of the signal delay processing method provided by the present application may also be implemented in the form of a program product comprising program code for causing a computer device to carry out the steps of the signal delay processing method described above in the present specification when the program code is run on the computer device or on a circuit product.
Furthermore, although the operations of the methods of the present application are depicted in the drawings in a particular order, this is not required or suggested that these operations must be performed in this particular order or that all of the illustrated operations must be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (15)

1. A phase locked loop, the phase locked loop comprising at least: a digital clock converter circuit and a negative feedback circuit; wherein the digital clock converter circuit comprises: a first delay circuit and a second delay circuit; the delay precision of the first delay circuit and the delay precision of the second delay circuit are the same;
The first delay circuit is used for receiving a reference clock signal and a first input control code word which are input by external equipment; performing signal delay processing on the reference clock signal based on the first input control codeword;
The second delay circuit is used for receiving a feedback clock signal fed back by the negative feedback circuit based on the phase-locked loop and the first input control code word; performing signal delay processing on the feedback clock signal based on a difference value between the first input control codeword and a maximum control codeword of the digital clock converter;
Wherein the first input control codeword is determined by a feedback divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal.
2. The phase-locked loop of claim 1, wherein the first delay circuit comprises at least one first delay cell; each first delay unit is connected in series;
the signal delay processing is performed on the reference clock signal based on the first input control codeword, and specifically is used for:
Determining a number of the first delay cells based on the first input control codeword;
And carrying out signal delay processing on the reference clock signal by using the first delay units with the determined number.
3. The phase locked loop of claim 2, wherein a total number of the first delay units is determined based on a maximum control codeword of the digital clock converter.
4. A phase locked loop as claimed in any one of claims 1 to 3, wherein said second delay circuit comprises at least one second delay element; each second delay unit is connected in series;
The signal delay processing is performed on the feedback clock signal based on a difference value between the first input control codeword and a maximum control codeword of the digital clock converter, and the signal delay processing is specifically configured to:
determining the number of the second delay units based on a difference between the first input control codeword and a maximum control codeword of the digital clock converter;
And carrying out signal delay processing on the feedback clock signal by using the determined number of second delay units.
5. The phase locked loop of claim 4 wherein a total number of the second delay cells is determined based on a maximum control codeword of the digital clock converter.
6. The phase-locked loop of claim 1, wherein the first delay circuit comprises a first drive unit, a second drive unit, a first resistor, and a first adjustable capacitance;
The first end of the first driving unit is connected with the first end of the first resistor, the second end of the first resistor is connected with the first end of the second driving unit and the first end of the first adjustable capacitor, the second end of the first adjustable capacitor is grounded, the second end of the first driving unit is the input end of the first delay circuit, and the second end of the second driving unit is the output end of the first delay circuit;
the signal delay processing is performed on the reference clock signal based on the first input control codeword, and specifically is used for:
determining a first capacitance value of the first tunable capacitance based on the first input control codeword;
And performing signal delay processing on the reference clock signal by using the first driving unit, the first resistor, the first capacitance value and the second driving unit.
7. The phase-locked loop of claim 6, wherein the capacitance value adjustment range of the first adjustable capacitance is determined based on a maximum control codeword of the digital clock converter.
8. A phase locked loop as claimed in any one of claims 1, 6 and 7, wherein the second delay circuit comprises a third drive unit, a fourth drive unit, a second resistor and a second adjustable capacitance;
The first end of the third driving unit is connected with the first end of the second resistor, the second end of the second resistor is connected with the first end of the fourth driving unit and the first end of the second adjustable capacitor, the second end of the second adjustable capacitor is grounded, the second end of the third driving unit is the input end of the second delay circuit, and the second end of the fourth driving unit is the output end of the second delay circuit;
The signal delay processing is performed on the feedback clock signal based on a difference value between the first input control codeword and a maximum control codeword of the digital clock converter, and the signal delay processing is specifically configured to:
determining a second capacitance value of the second adjustable capacitance based on a difference between the first input control codeword and a maximum control codeword of the digital clock converter;
and performing signal delay processing on the feedback clock signal by using the third driving unit, the second resistor, the second capacitance value and the fourth driving unit.
9. The phase-locked loop of claim 8, wherein the capacitance value adjustment range of the second adjustable capacitance is determined based on a maximum control codeword of the digital clock converter.
10. A phase locked loop as claimed in any one of claims 1 to 9, wherein said first input control codeword is any of zero to a maximum control codeword of said digital clock converter.
11. A phase locked loop as claimed in any one of claims 1 to 10, wherein said maximum control codeword is a, the offset control codeword is a/2, and said second input control codeword is any value (-a/2, a/2); a is a positive integer;
the first delay circuit is further configured to perform signal delay processing on the reference clock signal based on a result of adding the second input control codeword and the offset control codeword;
The second delay circuit is further configured to perform signal delay processing on the feedback clock signal based on a difference between the second input control codeword and the offset control codeword.
12. A chip, comprising: a phase locked loop as claimed in any one of claims 1 to 11; the digital clock converter circuit and the negative feedback circuit in the phase-locked loop are integrated on the same chip.
13. An electronic device, comprising: a circuit board and a chip as claimed in claim 12, said chip being disposed on said circuit board.
14. A signal delay processing method applied to a phase locked loop as claimed in any one of claims 1 to 11, the method comprising:
After receiving a reference clock signal and a first input control code word input by external equipment, a first delay circuit carries out signal delay processing on the reference clock signal based on the first input control code word;
After receiving a feedback clock signal and the first input control code word fed back by the negative feedback circuit of the phase-locked loop, the second delay circuit carries out signal delay processing on the feedback clock signal based on the difference value between the first input control code word and the maximum control code word of the digital clock converter;
The delay precision of the first delay circuit is the same as that of the second delay circuit, and the first input control code word is determined by a feedback frequency divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal.
15. The method of claim 14, wherein the maximum control codeword is a, the offset control codeword is a/2, and the second input control codeword is any value in (-a/2, a/2); a is a positive integer; the method further comprises the steps of:
The first delay circuit performs signal delay processing on the reference clock signal based on the addition result of the second input control code word and the offset control code word;
the second delay circuit performs signal delay processing on the feedback clock signal based on a difference value between the second input control codeword and the offset control codeword.
CN202211379473.8A 2022-11-04 2022-11-04 Phase-locked loop and signal delay processing method Pending CN117997336A (en)

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