WO2024093297A1

WO2024093297A1 - Phase-locked loop and signal delay processing method

Info

Publication number: WO2024093297A1
Application number: PCT/CN2023/103485
Authority: WO
Inventors: 陶婷婷; 毛懿鸿; 田洪亮
Original assignee: 华为技术有限公司
Priority date: 2022-11-04
Filing date: 2023-06-28
Publication date: 2024-05-10
Also published as: CN117997336A

Abstract

The present application provides a phase-locked loop and a signal delay processing method. After receiving a reference clock signal inputted by an external device and a first input control codeword, a first delay circuit performs signal delay processing on the reference clock signal on the basis of the first input control codeword; after receiving a feedback clock signal fed back by a negative feedback circuit on the basis of the phase-locked loop, and the first input control codeword, a second delay circuit performs signal delay processing on the feedback clock signal on the basis of a difference value between the first input control codeword and a maximum control codeword of a digital-to-time converter. By ensuring that the two delay circuits have the same delay precision, and determining the first input control codeword by using a feedback frequency divider in the negative feedback circuit on the basis of the phase of the reference clock signal and the phase of the feedback clock signal, the two delay circuits respectively perform signal delay processing, thereby eliminating a power supply memory effect of a digital-to-time converter circuit and reducing the sensitivity of the digital-to-time converter circuit to power supply noise.

Description

A phase-locked loop and a signal delay processing method

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to a Chinese patent application filed with the Chinese Patent Office on November 4, 2022, with application number 202211379473.8 and application name “A Phase-Locked Loop and Signal Delay Processing Method”, the entire contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of wireless communication technology, and in particular to a phase-locked loop and a signal delay processing method.

Background technique

In wireless communication systems, frequency synthesizers based on phase locked loop (PLL) structures are widely used to provide local oscillator signals. In data transmission systems, sampling clocks are generally provided based on phase locked loop structures. The quality of the clock signal output by the phase locked loop structure directly affects the quality of the communication signal or the quality of data transmission.

In all digital phase pocked poop (ADPLL) and analog phase pocked poop (APLL), frequency multipliers are usually used to increase the frequency of the reference clock, thereby improving the phase noise performance of the phase-locked loop output. In order to obtain a more accurate output frequency, fractional frequency division technology is generally used to adjust the instantaneous frequency division value of the frequency multiplier through a sigma-delta modulator (sigma delta modulation, SDM) to obtain fractional frequency division. However, the application of SDM will generate large quantization noise and also cause fractional spur problems in the output signal.

In order to solve the above problems caused by SDM, a digital to time converter (DTC) circuit is generally added, and the delay of the DTC circuit is controlled by adjusting the input control codeword of the DTC. However, the delay coverage of the DTC circuit in the prior art is relatively large, and the device noise and power consumption of the DTC circuit will increase with the increase of the delay, and different delays will lead to different power ripples, so that the overall circuit has a strong power memory effect, which affects the quality of the phase-locked loop output signal.

Summary of the invention

In view of this, the present application provides a phase-locked loop and a signal delay processing method to eliminate the power memory effect of a digital clock converter circuit and reduce the sensitivity of the digital clock converter circuit to power noise.

In a first aspect, the present application provides a phase-locked loop, which at least includes: a digital clock converter circuit and a negative feedback circuit; wherein the digital clock converter circuit includes: a first delay circuit and a second delay circuit; the delay accuracy of the first delay circuit and the second delay circuit is the same; the first delay circuit is used to receive a reference clock signal and a first input control codeword input by an external device; based on the first input control codeword, the reference clock signal is subjected to signal delay processing; the second delay circuit is used to receive a feedback clock signal and the first input control codeword fed back by the negative feedback circuit based on the phase-locked loop; based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter, the feedback clock signal is subjected to signal delay processing; wherein the first input control codeword is determined by a feedback divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal.

Compared with the prior art, the present application can obtain a first input control codeword based on the phase of a reference clock signal and a phase of a feedback clock signal by using a feedback divider in a negative feedback circuit while ensuring that the delay accuracy of the two delay circuits is the same, so that the two coupled delay circuits respectively perform signal delay processing on the reference clock signal and the feedback clock signal, thereby eliminating the power supply memory effect of the digital clock converter circuit and reducing the sensitivity of the digital clock converter circuit to power supply noise.

In one possible design, the first delay circuit includes at least one first delay unit; each first delay unit is connected in series; the signal delay processing of the reference clock signal based on the first input control codeword is specifically used to: determine the number of the first delay units based on the first input control codeword; and perform signal delay processing on the reference clock signal using the determined number of first delay units. The total number of the first delay units is determined based on the maximum control codeword of the digital clock converter.

By setting the size of the first input control codeword, the number of the first delay units can be accurately determined, thereby accurately performing signal adjustment on the reference clock signal.

In one possible design, the second delay circuit includes at least one second delay unit; each second delay unit is connected in series; the feedback clock signal is input based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter. The method is specifically used to: determine the number of the second delay units based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter; and perform signal delay processing on the feedback clock signal using the determined number of second delay units. The total number of the second delay units is determined based on the maximum control codeword of the digital clock converter.

By setting the size of the first input control codeword, the number of the second delay units can be accurately determined, thereby accurately performing signal adjustment on the feedback clock signal.

In a possible design, the first delay circuit includes a first driving unit, a second driving unit, a first resistor and a first adjustable capacitor; the first end of the first driving unit is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second driving unit and the first end of the first adjustable capacitor, the second end of the first adjustable capacitor is grounded, the second end of the first driving unit is the input end of the first delay circuit, and the second end of the second driving unit is the output end of the first delay circuit; the signal delay processing of the reference clock signal based on the first input control codeword is specifically used to: determine the first capacitance value of the first adjustable capacitor based on the first input control codeword; use the first driving unit, the first resistor, the first capacitance value and the second driving unit to perform signal delay processing on the reference clock signal. Wherein, the capacitance value adjustment range of the first adjustable capacitor is determined based on the maximum control codeword of the digital clock converter.

By setting the size of the first input control codeword, the capacitance value of the first adjustable capacitor can be accurately determined, thereby accurately adjusting the reference clock signal.

In a possible design, the second delay circuit includes a third driving unit, a fourth driving unit, a second resistor and a second adjustable capacitor; the first end of the third driving unit is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the fourth driving unit and the first end of the second adjustable capacitor, the second end of the second adjustable capacitor is grounded, the second end of the third driving unit is the input end of the second delay circuit, and the second end of the fourth driving unit is the output end of the second delay circuit; the signal delay processing of the feedback clock signal based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter is specifically used to: determine the second capacitance value of the second adjustable capacitor based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter; use the third driving unit, the second resistor, the second capacitance value and the fourth driving unit to perform signal delay processing on the feedback clock signal. Wherein, the capacitance value adjustment range of the second adjustable capacitor is determined based on the maximum control codeword of the digital clock converter.

By setting the size of the first input control codeword, the capacitance value of the second adjustable capacitor can be accurately determined, thereby accurately adjusting the feedback clock signal.

In one possible design, the first input control codeword is any value between zero and the maximum control codeword of the digital clock converter.

By setting the size of the first input control codeword, the two coupled delay circuits can be accurately utilized to perform signal delay processing on the reference clock signal and the feedback clock signal respectively.

In one possible design, the maximum control codeword is A, the offset control codeword is A/2, and the second input control codeword is any value in (-A/2, A/2); A is a positive integer; the first delay circuit is also used to perform signal delay processing on the reference clock signal based on the sum of the second input control codeword and the offset control codeword; the second delay circuit is also used to perform signal delay processing on the feedback clock signal based on the difference between the second input control codeword and the offset control codeword.

The present application sets the same offset control codeword for two mutually coupled delay circuits and ensures that the input control codewords of the two mutually coupled delay circuits are opposite numbers to each other, thereby obtaining different implementation methods in which the two delay circuits respectively perform signal delay adjustment on a reference clock signal and a feedback clock signal.

In a second aspect, the present application provides a chip, comprising a phase-locked loop as in the first aspect and any design thereof; the digital clock converter circuit and the negative feedback circuit in the phase-locked loop are integrated on the same chip.

In a third aspect, the present application provides an electronic device, comprising: a circuit board and a chip as described in the second aspect and any design thereof, wherein the chip is arranged on the circuit board.

In a fourth aspect, the present application provides a signal delay processing method, which is applied to a phase-locked loop as in the first aspect and any design thereof, the method comprising: after a first delay circuit receives a reference clock signal and a first input control codeword input by an external device, based on the first input control codeword, performing signal delay processing on the reference clock signal; after a second delay circuit receives a feedback clock signal fed back by a negative feedback circuit of the phase-locked loop based on the phase-locked loop and the first input control codeword, based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter, performing signal delay processing on the feedback clock signal; wherein, the delay accuracy of the first delay circuit and the second delay circuit is the same, and the first input control codeword is determined by a feedback divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal.

In one possible design, the first delay circuit includes at least one first delay unit; the first delay circuit is based on the first An input control codeword is used to perform signal delay processing on the reference clock signal, including: the first delay circuit determines the number of the first delay units based on the first input control codeword; and uses the determined number of first delay units to perform signal delay processing on the reference clock signal.

In one possible design, the total number of the first delay units is determined based on a maximum control codeword of the digital clock converter.

In one possible design, the second delay circuit includes at least one second delay unit; the second delay circuit performs signal delay processing on the feedback clock signal based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter, including: the second delay circuit determines the number of second delay units based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter; and uses the determined number of second delay units to perform signal delay processing on the feedback clock signal.

In one possible design, the total number of the second delay units is determined based on a maximum control codeword of the digital clock converter.

In one possible design, the first delay circuit includes a first driving unit, a second driving unit, a first resistor and a first adjustable capacitor; the first delay circuit performs signal delay processing on the reference clock signal based on the first input control codeword, including: the first delay circuit determines the first capacitance value of the first adjustable capacitor based on the first input control codeword; and uses the first driving unit, the first resistor, the first capacitance value and the second driving unit to perform signal delay processing on the reference clock signal.

In one possible design, a capacitance adjustment range of the first adjustable capacitor is determined based on a maximum control codeword of the digital clock converter.

In one possible design, the second delay circuit includes a third driving unit, a fourth driving unit, a second resistor and a second adjustable capacitor; the second delay circuit performs signal delay processing on the feedback clock signal based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter, including: the second delay circuit determines the second capacitance value of the second adjustable capacitor based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter; and uses the third driving unit, the second resistor, the second capacitance value and the fourth driving unit to perform signal delay processing on the feedback clock signal.

In one possible design, a capacitance adjustment range of the second adjustable capacitor is determined based on a maximum control codeword of the digital clock converter.

In one possible design, the maximum control codeword is A, the offset control codeword is A/2, and the second input control codeword is any value in (-A/2, A/2); A is a positive integer; the method also includes: the first delay circuit performs signal delay processing on the reference clock signal based on the sum of the second input control codeword and the offset control codeword; the second delay circuit performs signal delay processing on the feedback clock signal based on the difference between the second input control codeword and the offset control codeword.

In a fifth aspect, the present application provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed by a digital clock converter circuit, the digital clock converter circuit can execute any method designed in the above fourth aspect.

In a sixth aspect, the present application provides a computer program product, which includes computer instructions. When the computer instructions are executed by a digital clock converter circuit, the digital clock converter circuit can execute any method designed in the fourth aspect above.

For the technical effects that can be achieved by any possible design in any of the second to sixth aspects mentioned above, please refer to the description of the technical effects that can be achieved by any possible design in the first aspect mentioned above, and no further details will be given here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a fully digital phase-locked loop system provided in an embodiment of the present application;

FIG2 is a schematic diagram of the structure of a digital clock converter circuit provided in an embodiment of the present application;

3 is a schematic diagram of a reference clock signal Fref_in, a feedback clock signal Fdiv_in, and delayed signals Fref_out and Fdiv_out provided in an embodiment of the present application;

FIG4a is a schematic diagram showing the corresponding relationship between the operating current and the first input control codeword of the digital clock converter circuit provided in an embodiment of the present application;

FIG4b is a schematic diagram showing the corresponding relationship between the operating current and the input control codeword of the digital clock converter circuit in the prior art;

FIG5 is a schematic diagram of the structure of a digital clock converter circuit provided in an embodiment of the present application;

6 is a schematic diagram of the corresponding relationship between the operating current and the second input control codeword of the digital clock converter circuit provided in an embodiment of the present application;

FIG7 is a schematic diagram of the structure of a digital clock converter circuit provided in an embodiment of the present application;

FIG8 is a flow chart of a signal delay processing method provided in an embodiment of the present application.

Detailed ways

In order to enable ordinary persons in the art to better understand the technical solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

In wireless communication systems, frequency synthesizers based on phase-locked loop structures are widely used to provide local oscillator signals. In data transmission systems, sampling clocks are generally provided based on phase-locked loop structures. The quality of the clock signal output by the phase-locked loop structure directly affects the quality of the communication signal or the quality of data transmission.

In all-digital phase-locked loops and analog phase-locked loops, frequency multipliers are usually used to increase the frequency of the reference clock, thereby improving the phase noise performance of the phase-locked loop output. In order to obtain a more accurate output frequency, fractional frequency division technology is generally used to adjust the instantaneous frequency division value of the frequency multiplier through a sigma-delta modulator to obtain fractional frequency division. However, the application of SDM will generate large quantization noise and also cause fractional spurious problems in the output signal.

In order to solve the above problems caused by SDM, a digital time converter circuit is generally added to control the delay of the DTC circuit by adjusting the input control codeword of the DTC. However, the delay coverage of the DTC circuit in the prior art is relatively large, and the device noise and power consumption of the DTC circuit will increase with the increase of the delay, and different delays will cause different power ripples, so that the overall circuit has a strong power memory effect, which affects the quality of the phase-locked loop output signal.

In view of this, the present application provides a phase-locked loop and a signal delay processing method. In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

The phase-locked loop provided by the present application at least includes: a digital clock converter circuit and a negative feedback circuit, wherein the digital clock converter circuit may include: a first delay circuit and a second delay circuit, and the delay accuracy of the first delay circuit and the second delay circuit is the same. For example, the digital clock converter circuit may include a two-way coupled delay chain circuit.

Taking a fully digital phase-locked loop as an example, as shown in FIG1 , the fully digital phase-locked loop system includes: a digital clock converter circuit 101, a clock digital converter (time to digital converter, TDC) 102, a digital loop filter (digital loop filter, DLPF) 103, a digitally controlled oscillator (digitally controlled oscillator, DCO) 104, a feedback divider (feedback divider, NDIV) 105 and SDM 106. Here, the feedback divider 105 and SDM 106 can be used as a negative feedback circuit of the fully digital phase-locked loop system.

The two coupled delay circuits (i.e., the first delay circuit and the second delay circuit described above) in the digital clock converter circuit 101 are used to perform signal delay processing on the reference clock signal Fref_in and the feedback clock signal Fdiv_in, respectively. The delayed signals corresponding to the reference clock signal Fref_in and the feedback clock signal Fdiv_in are input to the clock digital converter 102, thereby eliminating the power supply memory effect of the digital clock converter circuit 101 in the fully digital phase-locked loop, and reducing the sensitivity of the digital clock converter circuit 101 to power supply noise. It should be known that the phase-locked loop in the present application can also be used in different application scenarios such as analog phase-locked loops.

For example, Fig. 2 shows a schematic diagram of the structure of a digital clock converter circuit provided in an embodiment of the present application. As shown in Fig. 2, the digital clock converter circuit includes: a first delay circuit 201 and a second delay circuit 202. The delay accuracy of the first delay circuit 201 and the second delay circuit 202 is the same.

After receiving the reference clock signal (ie, Fref_in in FIG. 2 ) and the first input control codeword (ie, Din in FIG. 2 ) inputted from the external device, the first delay circuit 201 performs signal delay processing on the reference clock signal based on the first input control codeword.

After receiving the feedback clock signal (i.e., Fdiv_in in FIG. 2 ) from the negative feedback circuit based on the phase-locked loop feedback and the first input control codeword, the second delay circuit 202 performs signal delay processing on the feedback clock signal based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter.

Here, the first input control codeword is any value from zero to the maximum control codeword of the digital clock converter, and the first input control codeword is determined by the feedback divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal. Optionally, in the feedback divider of the negative feedback circuit, the phase of the reference clock signal can be made infinitely close to the phase of the feedback clock signal according to the quantization noise elimination algorithm, thereby obtaining the first input control codeword. This is only an example of an implementation method for determining the first input control codeword, and the present application does not limit the specific determination method of the first input control codeword.

For example, assuming that the maximum control codeword of the digital clock converter is Dm, after the first delay circuit 201 receives the reference clock signal Fref_in and the first input control codeword Din, it uses Din to perform signal delay processing on Fref_in to obtain the output signal of the first delay circuit 201. After receiving the feedback clock signals Fdiv_in and Din, the second delay circuit 202 performs signal delay processing on Fdiv_in using the difference between Dm and Din to obtain the output signal Fdiv_out of the second delay circuit 202, that is, Fdiv_out is the signal after the Fdiv_in signal is delayed.

In one implementation, the first delay circuit 201 may include at least one first delay unit, each of which is connected in series. The second delay circuit 202 may include at least one second delay unit, each of which is connected in series.

Example 1: As shown in FIG. 2, the first delay circuit 201 includes a first delay unit 201-1, a first delay unit 201-2, ..., and a first delay unit 201-n. The first delay unit 201-1, the first delay unit 201-2, ..., and the first delay unit 201-n are connected in series. The second delay circuit 202 includes a second delay unit 202-1, a second delay unit 202-2, ..., and a second delay unit 202-n, where n is a positive integer. The second delay unit 202-1, the second delay unit 202-2, ..., and the second delay unit 202-n are connected in series.

The total number of the first delay units and the total number of the second delay units are both determined based on the maximum control codeword of the digital clock converter. When the maximum control codeword of the digital clock converter is Dm, the total number of the first delay units and the total number of the second delay units are both Dm.

It should be noted that the delay accuracy of the first delay circuit 201 is related to the delay accuracy of each first delay unit in the first delay circuit 201, and similarly, the delay accuracy of the second delay circuit 202 is related to the delay accuracy of each second delay unit in the second delay circuit 202. For example, assuming that the delay accuracy of the first delay unit 201-1, the first delay unit 201-2, ..., the first delay unit 201-n, the second delay unit 202-1, the second delay unit 202-2, ..., the second delay unit 202-n is T0, then the delay accuracy of the first delay circuit 201 and the delay accuracy of the second delay circuit 202 are both T0.

When the first input control codeword Din is any value between zero and the maximum control codeword Dm of the digital clock converter, the signal delay adjustment range that can be achieved by the digital clock converter circuit is obtained by inputting different Din. It can be seen from the following formula 1 that when Din is 0, the signal delay difference between the first delay circuit 201 and the second delay circuit 202 is -Dm*T0. When Din is Dm, the signal delay difference between the first delay circuit 201 and the second delay circuit 202 is Dm*T0. That is, when Din is in the range of (0, Dm), the signal delay adjustment range that can be achieved by the digital clock converter circuit is (-Dm*T0, Dm*T0). Here, Tref represents the signal delay of the first delay circuit 201, and Tdiv represents the signal delay of the second delay circuit 202.
Tref-Tdiv＝T0*Din-T0*(Dm-Din)＝2T0*Din-T0*Dm Formula 1

Optionally, as shown in FIG2 , in the scenario of Example 1 above, the first delay circuit 201 determines the number of first delay units based on the first input control codeword, and then uses the determined number of first delay units to perform signal delay processing on the reference clock signal. The second delay circuit 202 determines the number of second delay units based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter, and then uses the determined number of second delay units to perform signal delay processing on the feedback clock signal.

For example, assuming that the first input control codeword Din is 2 and the maximum control codeword Dm of the digital clock converter is 8, the first delay circuit 201 may include 8 first delay units and the second delay circuit 202 may include 8 second delay units. As Din is 2, it can be seen that the number of first delay units in the first delay circuit 201 that are in a normal working state is 2. In the first delay circuit 201, the reference clock signal Fref_in is subjected to signal delay processing by the two first delay units in a working state to obtain the delayed signal Fref_out. As Din is 2, Dm is 8, and the difference between Din and Dm, it can be seen that the number of second delay units in a normal working state in the second delay circuit 202 is 6. In the second delay circuit 202, the feedback clock signal Fdiv_in is subjected to signal delay processing by the six second delay units in a working state to obtain the delayed signal Fdiv_out. FIG3 shows a schematic diagram of the reference clock signal Fref_in, the feedback clock signal Fdiv_in, and the delayed signals Fref_out and Fdiv_out.

As can be seen from the above description, assuming that the maximum control codeword of the digital clock converter is Dm, when the first delay circuit 201 and the second delay circuit 202 in the digital clock converter circuit simultaneously perform the signal delay processing process, the total number of the first delay unit working in the first delay circuit 201 and the second delay unit working in the second delay circuit 202 is constant to Dm. If the operating current of each first delay unit and each second delay unit is i0, then the operating current of the digital clock converter circuit is Dm*i0, and remains constant. In this way, the influence on the power supply during the operation of the digital clock converter circuit can be kept consistent, and the power supply memory effect can be effectively eliminated. Figure 4a shows a schematic diagram of the corresponding relationship between the operating current of the digital clock converter circuit provided by an embodiment of the present application and the first input control codeword, and Figure 4b shows a schematic diagram of the corresponding relationship between the operating current of the digital clock converter circuit and the input control codeword in the prior art. It can be concluded from Figures 4a and 4b that, compared with the operating current of the digital clock converter circuit in the prior art that varies within the range of (0, 2Dm*i0), the present application eliminates the power supply memory effect problem by maintaining a constant current Dm*i0.

In addition, the power supply noise in the digital clock converter circuit is in common mode, so the digital clock converter circuit is insensitive to the power supply noise. Assuming that the gain of each first delay unit and each second delay unit to the power supply noise is A, and the low-frequency noise of the power supply is σ ² , then the noise difference between the first delay circuit 201 and the second delay circuit 202 is as shown in the following formula 2. That is, the maximum output noise of the digital clock converter circuit is The maximum output noise of the digital clock converter circuit is Dm*A*σ ² . Compared with the maximum output noise of the digital clock converter circuit in the prior art being 2Dm*A*σ ² , the present application can also reduce the output noise of the digital clock converter circuit.
(Dm-Din)*A*σ ² -Din*A*σ ² =(Dm-2Din)*A*σ ² Formula 2

In the present application, while ensuring that the delay accuracy of the two delay circuits is the same, a feedback divider in a negative feedback circuit can be used to obtain a first input control codeword based on the phase of a reference clock signal and the phase of a feedback clock signal, so that the two coupled delay circuits perform signal delay processing on the reference clock signal and the feedback clock signal respectively, thereby eliminating the power supply memory effect of the digital clock converter circuit and reducing the sensitivity of the digital clock converter circuit to power supply noise.

Optionally, in the scenario of Example 1 above, another implementation method of two mutually coupled delay circuits for signal delay adjustment of the reference clock signal and the feedback clock signal is further introduced: assuming that the maximum control codeword is A, the offset control codeword is A/2, and the second input control codeword is any value in (-A/2, A/2), the first delay circuit 201 performs signal delay processing on the reference clock signal based on the sum of the second input control codeword and the offset control codeword; the second delay circuit 202 performs signal delay processing on the feedback clock signal based on the difference between the second input control codeword and the offset control codeword. Here, A is a positive integer.

Exemplarily, as shown in FIG5 , it is assumed that the first delay circuit 201 includes a first delay unit 201-1, a first delay unit 201-2, a first delay unit 201-3, and a first delay unit 201-4, and the second delay circuit 202 includes a second delay unit 202-1, a second delay unit 202-2, a second delay unit 202-3, and a second delay unit 202-4.

When the maximum control codeword is A, the offset control codeword is A/2, and the second input control codeword D'in is any value in (-A/2, A/2), the signal delay adjustment range that can be achieved by the digital clock converter circuit is obtained by inputting different D'in. It can be seen from the following formula 3 that when D'in is -A/2, the signal delay difference between the first delay circuit 201 and the second delay circuit 202 is -A*T0. When D'in is A/2, the signal delay difference between the first delay circuit 201 and the second delay circuit 202 is A*T0. That is, when D'in is within the range of (-A/2, A/2), the signal delay adjustment range that can be achieved by the digital clock converter circuit is (-A*T0, A*T0). Here, T'ref represents the signal delay of the first delay circuit 201, and T'div represents the signal delay of the second delay circuit 202.
T'ref-T'div＝T0*(D'in+A/2)-T0*(A/2-D'in)＝2T0*D'in Formula 3

According to the above description, when the first delay unit 201-1 and the first delay unit 201-2 in the first delay circuit 201 are in working state, the second delay unit 202-1 and the second delay unit 202-2 in the second delay circuit 202 are in working state. That is, the total number of the first delay unit working in the first delay circuit 201 and the second delay unit working in the second delay circuit 202 is constant to 4, and the constant current A*i0 can also be maintained to eliminate the power supply memory effect problem. FIG6 shows a schematic diagram of the corresponding relationship between the working current and the second input control codeword of the digital clock converter circuit provided in an embodiment of the present application.

Likewise, the power supply noise in the digital clock converter circuit shown in FIG5 is in common mode, and therefore the circuit is insensitive to the power supply noise.

In another embodiment of the present application, the above solution may also be implemented through other internal structural connection modes of the first delay circuit 201 and the second delay circuit 202 .

In a possible implementation, as shown in FIG7 , the first delay circuit 201 may include a first driving unit 203, a second driving unit 204, a first resistor 205, and a first adjustable capacitor 206. The second delay circuit 202 includes a third driving unit 207, a fourth driving unit 208, a second resistor 209, and a second adjustable capacitor 2020. The capacitance adjustment range of the first adjustable capacitor 206 and the capacitance adjustment range of the second adjustable capacitor 2020 are both determined based on the maximum control codeword of the digital clock converter.

The first end of the first driving unit 203 is connected to the first end of the first resistor 205, the second end of the first resistor 205 is connected to the first end of the second driving unit 204 and the first end of the first adjustable capacitor 206, the second end of the first adjustable capacitor 206 is grounded, the second end of the first driving unit 203 is the input end of the first delay circuit 201, and the second end of the second driving unit 204 is the output end of the first delay circuit 201. The first end of the third driving unit 207 is connected to the first end of the second resistor 209, the second end of the second resistor 209 is connected to the first end of the fourth driving unit 208 and the first end of the second adjustable capacitor 2020, the second end of the second adjustable capacitor 2020 is grounded, the second end of the third driving unit 207 is the input end of the second delay circuit 202, and the second end of the fourth driving unit 208 is the output end of the second delay circuit 202.

After determining the first capacitance value of the first adjustable capacitor 206 based on the first input control codeword, the reference clock signal is subjected to signal delay processing using the first driving unit 203, the second driving unit 204, the first resistor 205, and the first capacitance value of the first adjustable capacitor 206. After determining the second capacitance value of the second adjustable capacitor 2020 based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter, the feedback clock signal is subjected to signal delay processing using the third driving unit 207, the fourth driving unit 208, the second resistor 209, and the second capacitance value of the second adjustable capacitor 2020. Here, the schematic diagram of signal delay processing can refer to FIG. 3, which will not be described in detail.

When the first input control codeword Din is any value between zero and the maximum control codeword Dm of the digital clock converter, the signal delay adjustment range that can be achieved by the digital clock converter circuit is obtained by inputting different Din. The specific implementation method can refer to the description corresponding to the above formula 1, which will not be repeated here.

Assuming that the maximum control codeword of the digital clock converter is Dm, then the capacitance adjustment range of the first adjustable capacitor 206 and the capacitance adjustment range of the second adjustable capacitor 2020 can both be (C1, C2), and C2 is greater than C1. When the first delay circuit 201 and the second delay circuit 202 in the digital clock converter circuit simultaneously perform the signal delay processing process, the first capacitance value of the first adjustable capacitor 206 in the first delay circuit 201 and the second capacitance value of the second adjustable capacitor 2020 in the second delay circuit 202 remain constant. If the operating currents of the first drive unit 203, the second drive unit 204, the first resistor 205, the third drive unit 207, the fourth drive unit 208, and the second resistor 209 are all i0, then the operating current of the digital clock converter circuit is Dm*i0, and remains constant. In this way, the influence on the power supply during the operation of the digital clock converter circuit can be kept consistent, and the power supply memory effect can be effectively eliminated.

Likewise, the power supply noise in the digital clock converter circuit shown in FIG. 7 is in common mode, and therefore the digital clock converter circuit is insensitive to the power supply noise.

Based on the above phase-locked loop embodiment, the embodiment of the present application further provides a signal delay processing method, which is applied to the phase-locked loop. The method can be performed by the digital clock converter circuit 101 in Figure 1. As shown in Figure 8, the method provided by the present application includes the following steps:

S801: After receiving a reference clock signal and a first input control codeword inputted from an external device, a first delay circuit performs signal delay processing on the reference clock signal based on the first input control codeword;

S802: After receiving the feedback clock signal fed back by the negative feedback circuit of the phase-locked loop based on the phase-locked loop and the first input control codeword, the second delay circuit performs signal delay processing on the feedback clock signal based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter;

The delay accuracy of the first delay circuit and the second delay circuit is the same, and the first input control codeword is determined by a feedback divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal.

In one possible design, the first delay circuit includes at least one first delay unit;

In step S801, the first delay circuit performs signal delay processing on the reference clock signal based on the first input control codeword, including:

The first delay circuit determines the number of first delay units based on the first input control codeword;

A signal delay process is performed on the reference clock signal by using a determined number of first delay units.

In one possible design, the total number of first delay units is determined based on a maximum control codeword of the digital clock converter.

In one possible design, the second delay circuit includes at least one second delay unit;

In step S802, the second delay circuit performs signal delay processing on the feedback clock signal based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter, including:

The second delay circuit determines the number of second delay units based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter;

The feedback clock signal is subjected to signal delay processing by utilizing a determined number of second delay units.

In one possible design, the first delay circuit includes a first driving unit, a second driving unit, a first resistor and a first adjustable capacitor;

The first delay circuit determines a first capacitance value of the first adjustable capacitor based on the first input control codeword;

The reference clock signal is subjected to signal delay processing by utilizing the first driving unit, the first resistor, the first capacitance and the second driving unit.

In a possible design, the capacitance adjustment range of the first adjustable capacitor is determined based on a maximum control code word of the digital clock converter.

In one possible design, the second delay circuit includes a third driving unit, a fourth driving unit, a second resistor, and a second adjustable capacitor;

The second delay circuit determines a second capacitance value of the second adjustable capacitor based on a difference between the first input control codeword and a maximum control codeword of the digital clock converter;

The third driving unit, the second resistor, the second capacitor and the fourth driving unit are used to perform signal delay processing on the feedback clock signal.

In a possible design, the capacitance adjustment range of the second adjustable capacitor is determined based on a maximum control code word of the digital clock converter.

In a possible design, when the maximum control codeword is A, the offset control codeword is A/2, and the second input control codeword is any value in (-A/2, A/2); A is a positive integer; the method further includes:

The first delay circuit performs signal delay processing on the reference clock signal based on the sum of the second input control codeword and the offset control codeword;

The second delay circuit performs signal delay processing on the feedback clock signal based on the difference between the second input control codeword and the offset control codeword.

In one embodiment of the present application, a chip is provided, comprising a phase-locked loop in any possible design described above; a digital clock converter circuit and a negative feedback circuit in the phase-locked loop are integrated on the same chip.

In one embodiment of the present application, an electronic device is further provided, comprising: a circuit board and a chip in any of the possible designs described above, wherein the chip is disposed on the circuit board.

An embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed by the digital clock converter circuit, the signal delay processing method shown in FIG. 8 can be executed.

The embodiment of the present application also provides a computer program product, including computer instructions. When the computer instructions are executed by the digital clock converter circuit, the signal delay processing method shown in Figure 8 can be executed.

That is to say, various aspects of the signal delay processing method provided in the present application can also be implemented in the form of a program product, which includes program code. When the program code is run on a computer device or a circuit product, the program code is used to enable the computer device to execute the steps in the signal delay processing method described above in this specification.

In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and/or one step may be decomposed into multiple steps.

Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

The present application is described with reference to the flowchart and/or block diagram of the method, device (system), and computer program product according to the present application. It should be understood that each process and/or box in the flowchart and/or block diagram, as well as the combination of the process and/or box in the flowchart and/or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one process or multiple processes in the flowchart and/or one box or multiple boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

A phase-locked loop, characterized in that the phase-locked loop at least comprises: a digital clock converter circuit and a negative feedback circuit; wherein the digital clock converter circuit comprises: a first delay circuit and a second delay circuit; the delay accuracy of the first delay circuit and the second delay circuit are the same;

The first delay circuit is used to receive a reference clock signal and a first input control codeword inputted from an external device; and perform signal delay processing on the reference clock signal based on the first input control codeword;

The second delay circuit is used to receive the feedback clock signal fed back by the negative feedback circuit based on the phase-locked loop and the first input control codeword; based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter, perform signal delay processing on the feedback clock signal;

The first input control codeword is determined by a feedback divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal.
The phase-locked loop according to claim 1, characterized in that the first delay circuit comprises at least one first delay unit; each of the first delay units is connected in series;

The performing signal delay processing on the reference clock signal based on the first input control codeword is specifically used for:

Determining the number of the first delay units based on the first input control codeword;

The reference clock signal is subjected to signal delay processing by using a determined number of first delay units.
The phase-locked loop of claim 2, wherein the total number of the first delay units is determined based on a maximum control codeword of the digital clock converter.
The phase-locked loop according to any one of claims 1 to 3, characterized in that the second delay circuit comprises at least one second delay unit; each second delay unit is connected in series;

The signal delay processing of the feedback clock signal based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter is specifically used for:

determining the number of the second delay units based on a difference between the first input control codeword and a maximum control codeword of the digital clock converter;

The feedback clock signal is subjected to signal delay processing by using a determined number of second delay units.
The phase-locked loop of claim 4, wherein the total number of the second delay units is determined based on a maximum control codeword of the digital clock converter.
The phase-locked loop according to claim 1, wherein the first delay circuit comprises a first driving unit, a second driving unit, a first resistor and a first adjustable capacitor;

A first end of the first driving unit is connected to a first end of the first resistor, a second end of the first resistor is connected to a first end of the second driving unit and a first end of the first adjustable capacitor, a second end of the first adjustable capacitor is grounded, a second end of the first driving unit is an input end of the first delay circuit, and a second end of the second driving unit is an output end of the first delay circuit;

The performing signal delay processing on the reference clock signal based on the first input control codeword is specifically used for:

Determining a first capacitance value of the first adjustable capacitor based on the first input control codeword;

The reference clock signal is subjected to signal delay processing by utilizing the first driving unit, the first resistor, the first capacitance and the second driving unit.
The phase-locked loop according to claim 6, wherein the capacitance adjustment range of the first adjustable capacitor is determined based on a maximum control codeword of the digital clock converter.
The phase-locked loop according to any one of claims 1, 6 and 7, characterized in that the second delay circuit comprises a third driving unit, a fourth driving unit, a second resistor and a second adjustable capacitor;

The first end of the third driving unit is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the fourth driving unit and the first end of the second adjustable capacitor, the second end of the second adjustable capacitor is grounded, the second end of the third driving unit is the input end of the second delay circuit, and the second end of the fourth driving unit is the output end of the second delay circuit;

The signal delay processing of the feedback clock signal based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter is specifically used for:

Determining a second capacitance value of the second adjustable capacitor based on a difference between the first input control codeword and a maximum control codeword of the digital clock converter;

The third driving unit, the second resistor, the second capacitance and the fourth driving unit are used to perform signal delay processing on the feedback clock signal.
The phase-locked loop according to claim 8, wherein the capacitance adjustment range of the second adjustable capacitor is determined based on a maximum control codeword of the digital clock converter.
The phase-locked loop according to any one of claims 1 to 9, characterized in that the first input control codeword is any value between zero and the maximum control codeword of the digital clock converter.
The phase-locked loop according to any one of claims 1 to 10, characterized in that when the maximum control codeword is A, the offset control codeword is A/2, and the second input control codeword is any value in (-A/2, A/2); A is a positive integer;

The first delay circuit is further used to perform signal delay processing on the reference clock signal based on the sum of the second input control codeword and the offset control codeword;

The second delay circuit is further used to perform signal delay processing on the feedback clock signal based on the difference between the second input control codeword and the offset control codeword.
A chip, characterized in that it comprises: a phase-locked loop as described in any one of claims 1 to 11; the digital clock converter circuit and the negative feedback circuit in the phase-locked loop are integrated on the same chip.
An electronic device, comprising: a circuit board and the chip according to claim 12, wherein the chip is arranged on the circuit board.
A signal delay processing method, characterized in that it is applied to a phase-locked loop as claimed in any one of claims 1 to 11, and the method comprises:

After receiving the reference clock signal and the first input control codeword inputted by the external device, the first delay circuit performs signal delay processing on the reference clock signal based on the first input control codeword;

After receiving the feedback clock signal fed back by the negative feedback circuit of the phase-locked loop based on the phase-locked loop and the first input control codeword, the second delay circuit performs signal delay processing on the feedback clock signal based on the difference between the first input control codeword and the maximum control codeword of the digital clock converter;

The delay accuracy of the first delay circuit and the second delay circuit is the same, and the first input control codeword is determined by the feedback divider in the negative feedback circuit based on the phase of the reference clock signal and the phase of the feedback clock signal.
The method according to claim 14, characterized in that when the maximum control codeword is A, the offset control codeword is A/2, and the second input control codeword is any value in (-A/2, A/2); A is a positive integer; the method further comprises:

The first delay circuit performs signal delay processing on the reference clock signal based on the sum of the second input control codeword and the offset control codeword;

The second delay circuit performs signal delay processing on the feedback clock signal based on a difference between the second input control codeword and the offset control codeword.