JP2006186576A - Phase-locked loop type frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase-locked loop type frequency synthesizer with a low noise while maintaining a high speed converging operation of phase synchronization. <P>SOLUTION: An adder 7 uses a setting signal of a local oscillation source 20 as a control signal given to a first voltage-controlled oscillator 4. The local oscillation source 20 comprises: a second reference oscillation source 11 for generating a second reference signal; a second voltage-controlled oscillator 14 for generating a local oscillation signal; a second variable frequency divider 15 for applying frequency-division to the local oscillation signal to provide an output of a second synchronizing signal; a second phase comparator 12 for receiving a second reference signal and the second synchronizing signal to output a second phase comparison signal; and a second loop filter 13 for smoothing the second phase comparison signal to provide an output of the smoothed second comparison signal to the second voltage-controlled oscillator 14 and the adder 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a phase-locked loop type frequency synthesizer used for a radio communication apparatus or the like.

  Conventionally, as a phase-locked loop type frequency synthesizer, a digital loop preset type frequency synthesizer including a PLL synthesizer circuit and a digital loop preset circuit for presetting a PLL loop phase and a frequency control voltage has been proposed (for example, non-patent). Reference 1). Such a frequency synthesizer is excellent in terms of price and size, and is said to be able to perform high-speed convergence operation with phase synchronization.

Taruzawa Yoshiaki et al., “Digital Loop Reset Type High-Speed Frequency Synthesizer”, IEICE Transactions B-II Vol. J75-B-II No. 6, pp. 345-353, 1992

  However, the conventional technique has the following problems. That is, in the conventional phase-locked loop type frequency synthesizer, a set voltage corresponding to a desired output frequency is obtained by digital calculation and applied to a voltage controlled oscillator, while high-speed frequency switching is realized, but the frequency of the output frequency. When the resolution is increased, it is necessary to increase the calculation accuracy, which increases the scale of the digital operation circuit and increases the power consumption. In addition, since noise caused by the digital arithmetic circuit is superimposed on the input terminal of the voltage controlled oscillator, there is a problem that the noise characteristics of the PLL synthesizer deteriorate.

  The present invention has been made to solve the above-described problems. A phase-locked loop type frequency synthesizer that achieves low noise while maintaining a high-speed phase-locked convergence operation without using a digital arithmetic circuit. The purpose is to obtain.

  A phase locked loop frequency synthesizer according to the present invention includes a first reference oscillation source that generates a first reference signal, a first voltage-controlled oscillator that generates a high-frequency signal, and a local oscillation source that generates a local oscillation signal. A high frequency signal and a local oscillation signal as input, a frequency converter that outputs a low frequency signal, a low frequency signal from the frequency converter as input, a frequency division of the low frequency signal, and a first synchronization signal as A first variable frequency divider for output, a first phase comparator for inputting a first reference signal and a first synchronization signal, and outputting a first phase comparison signal, and a first phase comparator A first loop filter that outputs an input and outputs a smoothed first phase comparison signal, an output signal of the first loop filter and a setting signal from a local oscillation source are input, and a first signal is generated based on these signals. Voltage control oscillator control In a configuration including an adder that outputs a signal, the local oscillation source is a second reference oscillation source that generates a second reference signal, a second voltage-controlled oscillator that generates a local oscillation signal, and a local oscillation A second variable frequency divider that inputs a signal, divides the frequency of the local oscillation signal and outputs a second synchronization signal, and receives a second reference signal and a second synchronization signal as inputs, and performs a second phase comparison A second phase comparator that outputs a signal, a second loop filter that receives the second phase comparison signal as an input, and outputs a smoothed second phase comparison signal to the second voltage controlled oscillator and the adder, respectively It is made up of.

  The phase-locked loop type frequency synthesizer of the present invention is controlled by adding a phase-locked loop type frequency synthesizer having a similar configuration to the phase-locked loop type frequency synthesizer. However, low noise can be realized.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram showing a phase-locked loop type frequency synthesizer (hereinafter referred to as a PLL synthesizer) according to Embodiment 1 of the present invention.
The PLL synthesizer of the present invention is capable of reducing noise while establishing high-speed phase synchronization by adding a PLL synthesizer to the conventional PLL synthesizer.

  The PLL synthesizer shown in FIG. 1 includes a first reference oscillation source 1, a first phase comparator 2, a first loop filter 3, a first voltage controlled oscillator 4, a first variable frequency divider 5, and a PLL control. Circuit 6, adder 7, frequency converter 8, filter 9, second reference oscillation source 11, second phase comparator 12, second loop filter 13, second voltage controlled oscillator 14, second variable The local oscillation source 20 is composed of the frequency divider 15 and the second reference oscillation source 11 to the second variable frequency divider 15.

  The first reference oscillation source 1 is an oscillation source that generates a first reference signal. The first phase comparator 2 receives the first reference signal output from the first reference oscillation source 1 and the first synchronization signal output from the first variable frequency divider 5 as inputs. 1 is a comparator that outputs a phase comparison signal of 1. The first loop filter 3 is a functional unit that receives the output of the first phase comparator 2 as an input and outputs a smoothed first phase comparison signal to the adder 7. The first voltage controlled oscillator 4 is an oscillator that generates a high frequency signal based on the output signal of the adder 7. The first variable frequency divider 5 is a functional unit that receives the low-frequency signal from the filter 9 and divides the frequency of the low-frequency signal to output a first synchronization signal.

  The PLL control circuit 6 is a functional unit that generates a control signal based on channel setting data from the outside and outputs the control signal to the first variable frequency divider 5 and the local oscillation source 20. The adder 7 is a functional unit that receives the output signal of the first loop filter 3 and the setting signal from the local oscillation source 20 and outputs the control signal of the first voltage controlled oscillator 4. The frequency converter 8 is a functional unit that inputs an external output oscillation signal from the first voltage controlled oscillator 4 and a local oscillation signal from the local oscillation source 20 and outputs a frequency mixed signal. The filter 9 is a filter that suppresses unnecessary frequency components from the frequency mixed signal from the frequency converter 8 and outputs the signal to the first variable frequency divider 5.

  Each configuration of the local oscillation source 20 is basically the same as the functions of the first reference oscillation source 1 to the first variable frequency divider 5 described above. That is, the second reference oscillation source 11 is an oscillation source that generates the second reference signal. The second phase comparator 12 receives the second reference signal output from the second reference oscillation source 11 and the second synchronization signal output from the second variable frequency divider 15 as inputs. 2 is a comparator that outputs two phase comparison signals. The second loop filter 13 is a functional unit that receives the output of the second phase comparator 12 as an input and outputs a smoothed second phase comparison signal to the second voltage controlled oscillator 14 and the adder 7.

Next, the operation of the first embodiment will be described.
The PLL control circuit 6 generates a control signal according to channel setting data corresponding to a desired oscillation frequency given from the outside, and outputs the control signal to the first variable frequency divider 5 and the local oscillation source 20, respectively. On the other hand, the first reference oscillator 1 generates a first reference signal (frequency fr) and outputs the first reference signal to the first phase comparator 2.

  The local oscillation source 20 generates a local oscillation signal (frequency fp) having a frequency corresponding to a control signal supplied from the PLL control circuit 6 and a set voltage, and the local oscillation signal is added to the frequency converter 8 and the set voltage Va is added to the adder. 7 respectively. Details of the set voltage Va output from the local oscillation source 20 will be described later.

  The frequency converter 8 inputs the external output oscillation signal (frequency fo) from the first voltage controlled oscillator 4 and the local oscillation signal (frequency fp) from the local oscillation source 20, and outputs the frequency mixed signal to the filter 9. . The filter 9 receives the frequency mixed signal from the frequency converter 8 and outputs an output signal in which unnecessary frequency components are suppressed to the first variable frequency divider 5. That is, the frequency converter 8 generates a signal having a difference frequency between the external output oscillation signal (frequency fo) and the local oscillation signal (frequency fp). Since this frequency mixed signal includes frequencies of various orders of frequency fo and frequency fp (m · fo ± n · fp: m and n are integers), the filter 9 suppresses unnecessary frequency components. To do. As a result, the frequency component of the signal output from the filter 9 is | fo-fp |.

  The first variable frequency divider 5 receives the output signal from the filter 9 and performs a first phase comparison of the first synchronization signal (frequency fv) frequency-divided according to the control signal from the PLL control circuit 6. To the device 2. The first phase comparator 2 receives the first reference signal (frequency fr) from the first reference oscillator 1 and the first synchronization signal (frequency fv) from the first variable frequency divider 5. Phase comparison is performed as a signal, and a phase comparison signal Vi corresponding to an amplitude value based on the difference phase is output to the first loop filter 3. The first loop filter 3 receives the phase comparison signal Vi from the first phase comparator 2 and outputs the smoothed signal Vo to the adder 7. The adder 7 receives the smoothed signal Vo from the first loop filter 3 and the set voltage Va from the local oscillation source 20, and outputs a voltage-added signal Vt to the first voltage controlled oscillator 4.

  The first voltage controlled oscillator 4 receives the voltage addition signal Vt from the adder 7 and outputs an external output oscillation signal (frequency fo) corresponding to the input to the outside. Further, the external output oscillation signal (frequency fo) is fed back to the frequency converter 8. In the first voltage controlled oscillator 4, the frequency fv of the first synchronization signal supplied from the first variable frequency divider 5 approaches the frequency fr of the first reference signal supplied from the first reference oscillation source 1. Operate in the direction. If the deviation between the frequency fv of the first synchronization signal and the frequency fr of the first reference signal falls within a certain frequency range, the signal Vo smoothed by the first loop filter 3 becomes stable, and the external The output oscillation signal is locked to the frequency fo, and a stable oscillation signal is output to the outside.

  In the local oscillation source 20, the local oscillation signal (frequency fp) from the second voltage controlled oscillator 14 is output to the frequency converter 8 and the second variable frequency divider 15, respectively. The second variable frequency divider 15 outputs a second synchronization signal frequency-divided according to the control signal from the PLL control circuit 6 to the second phase comparator 12. The second phase comparator 12 performs phase comparison between the second reference signal from the second reference oscillator 11 and the second synchronization signal, and outputs the result to the second loop filter 13. In the second loop filter 13, the comparison signal from the second phase comparator 12 is smoothed and output to the second voltage controlled oscillator 14 and the adder 7, respectively. The second voltage controlled oscillator 14 operates so that the frequencies of the second reference signal and the second synchronization signal match.

  The set voltage Va output from the local oscillation source 20 is the same as the control signal of the second voltage controlled oscillator 14 as described above. Therefore, the frequency fp and the set voltage Va of the local oscillation signal can be controlled by the control signal to the second variable frequency divider 15. By setting the setting voltage Va so that the frequency fo of the external output oscillation signal is in the vicinity of the control voltage of the first voltage controlled oscillator 4 at the desired frequency, high-speed frequency switching can be realized without using a digital arithmetic circuit. it can.

  Further, in the PLL synthesizer of the present embodiment, since the input frequency to the first variable frequency divider 5 can be lowered using the frequency converter 8, the frequency division number N of the first variable frequency divider 5 is conventionally set. Lower than the PLL synthesizer. By reducing the frequency dividing number of the variable frequency divider, the phase noise characteristic of the PLL synthesizer can be improved. That is, the phase noise characteristic of the PLL output is degraded and output at the frequency division number N of the phase comparator or variable frequency divider. This deterioration is expressed by 20 · log 10 (N) (dB). Therefore, as N is lowered, the amount of deterioration decreases, and the phase noise characteristics can be improved.

  In the circuit configuration described above, the first loop filter 3 is connected to the output of the first phase comparator 2, and the adder 7 is connected to the output of the first loop filter 3. However, the connection order of the first loop filter 3 and the adder 7 may be reversed, and even with such a configuration, an effect similar to that of the above-described circuit configuration is achieved.

FIG. 2 is a block diagram showing the circuit configuration.
As shown in the figure, an adder 7 is connected to the output of the first phase comparator 2, and a first loop filter 3 is connected to the output of the adder 7. That is, the adder 7 inputs the output signal of the first phase comparator 2 and the output signal of the second loop filter 13, and outputs a voltage-added signal to the first loop filter 3. The first loop filter 3 receives the output signal of the adder 7 as an input, and outputs the smoothed output signal of the adder 7 as a control signal of the first voltage controlled oscillator 4. Since other configurations and operations are the same as those of the circuit configuration shown in FIG. 1, the same reference numerals are given to corresponding portions, and description thereof is omitted.

  Further, in the circuit configuration shown in the first embodiment shown in FIG. 1 and FIG. 2, the configuration using two reference oscillators (the first reference oscillation source 1 and the second reference oscillation source 11) is shown. The output may be made from one reference oscillation source to the first phase comparator 2 and the second phase comparator 12.

  As described above, according to the phase-locked loop type frequency synthesizer of the first embodiment, the first reference oscillation source that generates the first reference signal, the first voltage-controlled oscillator that generates the high-frequency signal, and the local A local oscillation source that generates an oscillation signal, a high-frequency signal and a local oscillation signal as input, a frequency converter that outputs a low-frequency signal, a low-frequency signal from the frequency converter as input, and a low-frequency signal divided by frequency A first variable frequency divider that outputs a first synchronization signal; a first phase comparator that receives the first reference signal and the first synchronization signal and outputs a first phase comparison signal; The output of the first phase comparator is input, the first loop filter that outputs the smoothed first phase comparison signal, the output signal of the first loop filter and the setting signal from the local oscillation source are input. Add these signals to the voltage And an adder that outputs as a control signal for one voltage controlled oscillator, a local oscillation source, a second reference oscillation source that generates a second reference signal, and a second voltage controlled oscillator that generates a local oscillation signal A second variable frequency divider that inputs a local oscillation signal, frequency-divides the local oscillation signal and outputs a second synchronization signal, a second reference signal, and a second synchronization signal as inputs, The second phase comparator that outputs the phase comparison signal of 2 and the second phase comparison signal as inputs, and outputs the smoothed second phase comparison signal to the second voltage controlled oscillator and as the setting signal Since it is configured with the second loop filter that outputs, the PLL synthesizer has an effect of realizing low noise while establishing high-speed phase synchronization.

  Further, according to the phase-locked loop frequency synthesizer of the first embodiment, the first reference oscillation source that generates the first reference signal, the first voltage-controlled oscillator that generates the high-frequency signal, and the local oscillation signal A local oscillation source to be generated, a high frequency signal and the local oscillation signal as inputs, a frequency converter that outputs a low frequency signal, a low frequency signal from the frequency converter as an input, and the low frequency signal is frequency-divided, A first variable frequency divider that outputs a first synchronization signal; a first phase comparator that receives a first reference signal and a first synchronization signal and outputs a first phase comparison signal; The output signal of the phase comparator of 1 and the setting signal from the local oscillation source are input, and an adder that outputs a signal obtained by voltage-adding these signals, and the output signal of the adder that is smoothed by using the output signal of the adder as input Is controlled by the first voltage controlled oscillator. A local oscillation source, a second reference oscillation source for generating a second reference signal, a second voltage controlled oscillator for generating a local oscillation signal, and a local oscillation signal , The second variable frequency divider for frequency-dividing the local oscillation signal and outputting the second synchronization signal, the second reference signal and the second synchronization signal as inputs, and the second phase comparison signal A second phase comparator that outputs the second phase comparison signal, and a second phase comparison signal that has been smoothed is output to the second voltage controlled oscillator and is output as a setting signal. Since it is configured with a loop filter, similarly, as a PLL synthesizer, there is an effect that low noise can be realized while establishing high-speed phase synchronization.

Embodiment 2. FIG.
In the first embodiment, the configuration in which the control signal of the second voltage controlled oscillator used for the local oscillation source is used as the set voltage has been described. When an integer PLL synthesizer is used as the local oscillation source, the frequency resolution needs to be lowered in order to set the set voltage to an arbitrary value. In this case, there is a problem that the phase noise characteristic of the local oscillation source deteriorates and the phase noise characteristic of the entire PLL synthesizer deteriorates. In the second embodiment, another configuration that solves the above problem and establishes phase synchronization stably and at high speed will be described.

FIG. 3 is a block diagram showing a PLL synthesizer according to Embodiment 2 of the present invention.
In the figure, a delta sigma (ΔΣ) modulation circuit 16 receives a control signal from the PLL control circuit 6 as an input, and uses a signal from the second variable frequency divider 15 as a clock to generate a second delta sigma modulated control signal. Output to the variable frequency divider 15. The second variable frequency divider 15 receives a local oscillation signal (frequency fp) from the second voltage controlled oscillator 14 and receives a second frequency divided according to the control signal from the delta-sigma modulation circuit 16. Are output to the second phase comparator 12. Since each other configuration is the same as that of the first embodiment, the corresponding parts are denoted by the same reference numerals and description thereof is omitted.

  In the PLL synthesizer configured as described above, the second variable frequency divider 15 is controlled by delta-sigma modulation, so that a desired frequency resolution can be obtained without deteriorating the phase noise characteristic. Therefore, it is possible to realize a PLL synthesizer having low phase noise characteristics while setting the set voltage to an arbitrary value. That is, the second variable frequency divider 15 can be operated at a higher phase comparison frequency when the frequency of the output signal is set to the same value by the fractional operation by delta-sigma modulation. As described in the first embodiment, the phase noise characteristic of the PLL output is such that the noise characteristic of the phase comparator or variable frequency divider is degraded by the value of the variable frequency division number N. Noise characteristics can be improved. Since N is given by the output frequency fo / phase comparison frequency fr, the value of N can be reduced by increasing fr. Therefore, with such a fractional operation, the phase comparison frequency can be increased even if the same frequency resolution is realized, and as a result, the phase noise characteristics can be improved.

  In the circuit configuration described above, the first loop filter 3 is connected to the output of the first phase comparator 2, and the adder 7 is connected to the output of the first loop filter 3. However, the connection order of the first loop filter 3 and the adder 7 may be reversed, and even with such a configuration, an effect similar to that of the above-described circuit configuration is achieved.

FIG. 4 is a block diagram showing the circuit configuration.
As shown in the figure, an adder 7 is connected to the output of the first phase comparator 2, and a first loop filter 3 is connected to the output of the adder 7. That is, the adder 7 inputs the output signal of the first phase comparator 2 and the output signal of the second loop filter 13, and outputs a voltage-added signal to the first loop filter 3. The first loop filter 3 receives the output signal of the adder 7 as an input, and outputs the smoothed output signal of the adder 7 as a control signal of the first voltage controlled oscillator 4. Since other configurations and operations are the same as those of the circuit configuration shown in FIG. 3, the same reference numerals are given to corresponding portions, and description thereof is omitted.

  Further, in the circuit configuration shown in the second embodiment shown in FIGS. 3 and 4, a configuration using two reference oscillators (first reference oscillation source 1 and second reference oscillation source 11) is shown. The output may be made from one reference oscillation source to the first phase comparator 2 and the second phase comparator 12.

  As described above, according to the phase-locked loop frequency synthesizer of the second embodiment, the local oscillation source outputs a delta-sigma modulation signal corresponding to setting data given from the outside to the second variable frequency divider. A sigma modulation circuit, a second reference oscillation source for generating a second reference signal, a second voltage controlled oscillator for generating a local oscillation signal, a local oscillation signal, and the local oscillation signal as a delta sigma modulation signal And a second variable frequency divider that divides the frequency according to the output and outputs a second synchronization signal, a second reference signal and a second synchronization signal as inputs, and a second phase comparison signal that is output. 2 and a second loop filter that receives the second phase comparison signal and outputs a smoothed second phase comparison signal to the second voltage controlled oscillator and as a setting signal. Since it is configured, the embodiment In addition to the effects, without deteriorating the phase noise characteristics, it is possible to obtain a desired frequency resolution, and thus, it is possible to realize a PLL synthesizer having a low phase noise characteristic.

Embodiment 3 FIG.
In the first and second embodiments, the configuration in which the control voltage of the first voltage controlled oscillator is obtained by voltage addition of the set voltage from the local oscillation source and the smoothed signal from the first loop filter has been described. . The characteristics (VF characteristics) of the output frequency with respect to the control voltage of the first voltage controlled oscillator and the second voltage controlled oscillator vary depending on the individual variations of semiconductor devices used in the voltage controlled oscillator, and the desired V The -F characteristic is not always obtained. If the set voltage differs greatly from a desired value, there is a possibility that phase synchronization cannot be established stably. In the third embodiment, another configuration that solves the above problem and establishes phase synchronization stably and at high speed will be described.

FIG. 5 is a configuration diagram showing a PLL synthesizer according to the third embodiment of the present invention.
In the figure, the voltage amplifier 17 receives the set voltage (Va) from the local oscillation source 20 and outputs the set voltage (α · Va) amplified with a fixed voltage gain (α) to the adder 7. The offset voltage circuit 18 generates an offset voltage (Vs) and outputs it to the adder 7. The adder 7 receives the smoothed signal (Vo) from the first loop filter 3, the output voltage (α · Va) from the voltage amplifier 17, and the offset voltage (Vs) from the offset voltage circuit 18. The voltage added signal (Vt = Vo + α · Va + Vs) is output to the first voltage controlled oscillator 4. Since other configurations and operations are the same as those in the first and second embodiments, the corresponding parts are denoted by the same reference numerals and description thereof is omitted. The voltage gain (α) of the voltage amplifier 17 and the offset voltage (Vs) of the offset voltage circuit 18 are V−F of signals output from the first voltage controlled oscillator 4 and the second voltage controlled oscillator 14. It is appropriately set so that the characteristics are equivalent.

  In the PLL synthesizer configured as described above, the set voltage can be corrected by using the voltage amplifier 17 and the offset voltage circuit 18. That is, since the corrected set voltage can be made close to a desired value, stable phase synchronization can be established even when a voltage controlled oscillator that does not have a desired VF characteristic is used.

  In the circuit configuration described above, the first loop filter 3 is connected to the output of the first phase comparator 2, and the adder 7 is connected to the output of the first loop filter 3. However, the connection order of the first loop filter 3 and the adder 7 may be reversed, and even with such a configuration, an effect similar to that of the above-described circuit configuration is achieved.

FIG. 6 is a block diagram showing the circuit configuration.
As shown in the figure, an adder 7 is connected to the output of the first phase comparator 2, and a first loop filter 3 is connected to the output of the adder 7. That is, the adder 7 inputs the output signal of the first phase comparator 2, the output voltage from the voltage amplifier 17 and the offset voltage from the offset voltage circuit 18, and the signal obtained by voltage addition is input to the first loop filter. 3 is output. The first loop filter 3 receives the output signal of the adder 7 as an input, and outputs the smoothed output signal of the adder 7 as a control signal of the first voltage controlled oscillator 4. Since other configurations and operations are the same as those of the circuit configuration shown in FIG. 5, the same reference numerals are given to corresponding portions, and description thereof is omitted.

  Further, in the circuit configuration shown in the third embodiment shown in FIGS. 5 and 6, a configuration using two reference oscillators (first reference oscillation source 1 and second reference oscillation source 11) is shown. The output may be made from one reference oscillation source to the first phase comparator 2 and the second phase comparator 12.

  In addition, although the said Embodiment 3 demonstrated the case where it applied to the structure of the local oscillation source 20 of Embodiment 2, even if it applies to the structure of Embodiment 1, there exists the same effect.

  As described above, according to the phase-locked loop frequency synthesizer of the third embodiment, the setting signal output from the second loop filter is input, and the voltage that outputs the signal obtained by amplifying the setting signal with a predetermined voltage gain is output. An amplifier, an offset voltage circuit that generates and outputs a predetermined offset voltage, and an output signal of the voltage amplifier and an output signal of the offset voltage circuit are input instead of a setting signal from the local oscillation source, and a voltage-added signal is output. In addition to the effects of the first and second embodiments, a stable phase synchronization can be realized even when a voltage controlled oscillator that does not have a desired VF characteristic is used. effective.

1 is a configuration diagram of a phase-locked loop type frequency synthesizer according to Embodiment 1 of the present invention. FIG. It is a block diagram which shows the other example of the phase locked loop type | mold frequency synthesizer by Embodiment 1 of this invention. It is a block diagram of the phase locked loop type | mold frequency synthesizer by Embodiment 2 of this invention. It is a block diagram which shows the other example of the phase locked loop type | mold frequency synthesizer by Embodiment 2 of this invention. It is a block diagram of the phase locked loop type | mold frequency synthesizer by Embodiment 3 of this invention. It is a block diagram which shows the other example of the phase locked loop type | mold frequency synthesizer by Embodiment 3 of this invention.

Explanation of symbols

  1 first reference oscillation source 2 first phase comparator 3 first loop filter 4 first voltage controlled oscillator 5 first variable frequency divider 6 PLL control circuit 7 adder 8 Frequency converter, 11 second reference oscillation source, 12 second phase comparator, 13 second loop filter, 14 second voltage controlled oscillator, 15 second variable frequency divider, 16 delta-sigma modulation circuit, 17 Voltage amplifier, 18 Offset voltage circuit.

Claims (4)

A first reference oscillation source for generating a first reference signal;
A first voltage controlled oscillator for generating a high frequency signal;
A local oscillation source for generating a local oscillation signal;
The frequency converter that inputs the high-frequency signal and the local oscillation signal and outputs a low-frequency signal;
A first variable frequency divider that receives the low frequency signal from the frequency converter, divides the frequency of the low frequency signal, and outputs a first synchronization signal;
A first phase comparator that receives the first reference signal and the first synchronization signal and outputs a first phase comparison signal;
A first loop filter that takes the output of the first phase comparator as an input and outputs the smoothed first phase comparison signal;
An adder that receives an output signal of the first loop filter and a setting signal from the local oscillation source as an input, adds a voltage of these signals and outputs as a control signal of the first voltage-controlled oscillator;
The local oscillation source,
A second reference oscillation source for generating a second reference signal;
A second voltage controlled oscillator for generating the local oscillation signal;
A second variable frequency divider that inputs the local oscillation signal, frequency-divides the local oscillation signal, and outputs a second synchronization signal;
A second phase comparator that inputs the second reference signal and the second synchronization signal and outputs a second phase comparison signal;
The phase composed of the second phase comparison signal as an input and the smoothed second phase comparison signal output to the second voltage-controlled oscillator and output as the setting signal Synchronous loop type frequency synthesizer. A first reference oscillation source for generating a first reference signal;
A first voltage controlled oscillator for generating a high frequency signal;
A local oscillation source for generating a local oscillation signal;
The frequency converter that inputs the high-frequency signal and the local oscillation signal and outputs a low-frequency signal;
A first variable frequency divider that receives the low frequency signal from the frequency converter, divides the frequency of the low frequency signal, and outputs a first synchronization signal;
A first phase comparator that receives the first reference signal and the first synchronization signal and outputs a first phase comparison signal;
An adder that outputs an output signal of the first phase comparator and a setting signal from the local oscillation source and outputs a signal obtained by voltage-adding these signals;
A first loop filter having the output signal of the adder as an input and the smoothed output signal of the adder as a control signal of a first voltage controlled oscillator;
The local oscillation source,
A second reference oscillation source for generating a second reference signal;
A second voltage controlled oscillator for generating the local oscillation signal;
A second variable frequency divider that inputs the local oscillation signal, frequency-divides the local oscillation signal, and outputs a second synchronization signal;
A second phase comparator that inputs the second reference signal and the second synchronization signal and outputs a second phase comparison signal;
A phase constituted by a second loop filter that receives the second phase comparison signal as an input, outputs the smoothed second phase comparison signal to the second voltage controlled oscillator, and outputs it as the setting signal. Synchronous loop type frequency synthesizer. Local oscillator source
A delta-sigma modulation circuit that outputs a delta-sigma modulation signal corresponding to setting data given from the outside to the second variable frequency divider;
A second reference oscillation source for generating a second reference signal;
A second voltage controlled oscillator for generating a local oscillation signal;
A second variable frequency divider that inputs the local oscillation signal, frequency-divides the local oscillation signal according to the delta-sigma modulation signal, and outputs a second synchronization signal;
A second phase comparator that inputs the second reference signal and the second synchronization signal and outputs a second phase comparison signal;
The second phase comparison signal as an input, and the second phase comparison signal that has been smoothed is output to the second voltage controlled oscillator and is output from the second loop filter as a setting signal. 3. A phase-locked loop type frequency synthesizer according to claim 1 or 2. A voltage amplifier that inputs a setting signal output from the second loop filter and outputs a signal obtained by amplifying the setting signal with a predetermined voltage gain;
An offset voltage circuit that generates and outputs a predetermined offset voltage;
2. An adder that outputs a voltage-added signal using the output signal of the voltage amplifier and the output signal of the offset voltage circuit as input instead of a setting signal from a local oscillation source. 4. The phase-locked loop frequency synthesizer according to any one of items 3.

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