JP2003069426A - Frequency synthesizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency synthesizer with less frequency versus temperature fluctuations and excellent C/N with respect to a circuit for compensating an output signal frequency versus temperature fluctuations of the frequency synthesizer used for a wireless section of a mobile telephone or the like. SOLUTION: A simple crystal oscillator not needing temperature compensation is adopted for a reference signal of the synthesizer to enhance the C/N of the reference signal, a fraction frequency divider circuit capable of adjusting the output frequency in fine steps is adopted for a variable frequency division circuit of the synthesizer and the frequency division ratio is fine-tuned in matching with the ambient temperature change. Further, the changeover of the frequency division ratio is limited to a timing where transient fluctuations of the frequency are permitted such as channel switching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for compensating for temperature fluctuations in the output signal frequency of a frequency synthesizer used in a wireless section of a mobile phone or the like.

[0002]

2. Description of the Related Art Conventionally, in a portable telephone, a temperature-compensated crystal oscillator (hereinafter referred to as "TCXO") generates a reference frequency signal with little temperature fluctuation, and this is used as a reference signal of a synthesizer. The temperature fluctuation of the output frequency was reduced.

FIG. 3 shows the internal structure of a conventional TCXO, and FIG.
The configuration of a fractional frequency division PLL frequency synthesizer using this TCXO is shown in FIG.

In FIG. 3, 1 is a temperature detection circuit, 2 is a
A control signal generation circuit that outputs a control signal to a voltage controlled crystal oscillator (hereinafter referred to as “VCXO”) 4 by using an output signal of the temperature detection circuit 1 as an input, and 4 is a signal whose frequency changes according to the input voltage. Output to the output terminal 6
It is O. The frequency of a crystal oscillator usually has a temperature characteristic of a cubic function with a change width of several tens of ppm. Therefore, the control signal generating circuit 2 generates a cubic function having a phase opposite to that of the temperature characteristic of the VCXO4 and applies this output to the frequency control signal input terminal of the VCXO4, so that a signal with little temperature variation as a whole is generated. It is obtained at the output terminal 6.

Next, the operation of the fractional frequency division PLL frequency synthesizer will be described with reference to FIG.

First, the structure and operation of a conventional PLL synthesizer will be described.

In FIG. 4, the output signal of the TCXO 7 is input to the reference frequency dividing circuit 8 and divided by R. On the other hand, the output of the voltage controlled oscillator (hereinafter referred to as VCO) 9 is divided by P by the variable frequency dividing circuit 10. The phase comparator 11 compares the phases of the R-divided signal and the P-divided signal. The output signal of the phase comparator 11 is fed back to the VCO 9 via the low-pass filter (LPF) 12, and a signal obtained by multiplying the TCXO output signal by (P / R) is output to the frequency synthesizer output terminal 13. In this way, by reducing the temperature fluctuation of the output signal of the TCXO 7, the temperature fluctuation of the signal frequency of the frequency synthesizer output terminal 13 is reduced.

Next, the fractional frequency division P of the conventional synthesizer
The configuration and operation of the LL will be described.

Reference numeral 14 denotes an input terminal of a signal for giving an integer part N of the frequency division ratio (where N is an integer), and 15 is a fractional part F / M of the frequency division ratio (where F and M are integers). Is a signal input terminal, and 16 is an output section of the variable frequency dividing circuit. Reference numeral 17 is a delta-sigma circuit having a signal from the input terminal 15 as a data input, a signal from the output section 16 as a clock input, and having 18 as an output terminal, and 19 is a signal provided from the input terminal 14 and the output terminal 18 as an input. , An adding circuit for outputting the frequency division ratio given to the variable frequency dividing circuit 10 to the output unit 20. Assuming that the fractional part of the frequency division ratio is F / M, the signal at the output terminal 18 of the ΔΣ circuit 17 changes its value discretely at the timing when the output of the variable frequency division circuit 10 changes, and thus the temporal average value becomes It is designed to be equal to F / M and the frequency spectrum is concentrated in a high frequency band (referred to as noise shaping). As a result, the temporal average value P of the frequency division ratio of the variable frequency dividing circuit 10 is P = N + F / M because the integer part of the frequency division ratio is N. As described above, the conventional fractional frequency division PLL frequency synthesizer synthesizes a frequency that is (P / R) times the reference input frequency and has less spurious.

[0010]

However, in the above-mentioned conventional configuration, noise generated by the temperature detection circuit or the control signal generation circuit is applied to the VCXO, so that VX
The carrier noise ratio (hereinafter referred to as C / N) of the CXO output signal is deteriorated, and as a result, the C / N of the output of the frequency synthesizer is also deteriorated.

An object of the present invention is to solve the above-mentioned conventional problems, and an object thereof is to realize a synthesizer having a small frequency temperature fluctuation and a good C / N.

Further, when the frequency division ratio is continuously changed in response to a change in ambient temperature, a transient fluctuation may occur in the output frequency at the time when the frequency division ratio changes. The purpose is to prevent malfunction due to.

[0013]

In order to achieve this object, the invention according to claim 1 of the present invention is a simple crystal oscillator (hereinafter referred to as XO) which does not require temperature compensation from a synthesizer reference signal TCXO. .) Is used to improve the C / N of the reference signal. In addition, the variable frequency divider circuit of the synthesizer uses a fractional frequency divider circuit that can adjust the output frequency in fine steps, and by finely adjusting this frequency division ratio according to the ambient temperature change, the output frequency temperature fluctuation And a frequency synthesizer with a good C / N ratio.

The invention according to claim 2 of the present invention prevents malfunction due to this transient fluctuation by limiting the switching of the frequency division ratio to the timing at which transient fluctuation of the frequency is allowed such as when switching channels. is there.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a frequency synthesizer according to the first embodiment of the present invention. Figure 1
, 21 is an XO output terminal, 22 is an XO output terminal,
The signal at the terminal 22 is the phase lock circuit (PL
L) is used as a reference signal. Reference frequency dividing circuit 8, phase comparator 11, LPF 12, VCO 9, variable frequency dividing circuit 1
0, the configuration and operation of the frequency synthesizer output terminal 13 are the same as those of the conventional synthesizer shown in FIG. Regarding the configuration and operation of the fractional frequency division PLL, the input terminal 14 for the integer part of the frequency division ratio, the input terminal 15 for the fractional part, the output section 16 of the variable frequency division circuit, and ΔΣ
The circuit 17, the adder circuit 19, and the output section 20 of the adder circuit are the same as those in FIG. However, in FIG. 4, the frequency division ratio input terminal 15 in the fractional part is directly connected to the data input of the ΔΣ circuit, whereas in the present invention, the temperature detection circuit 23 is used.
Control signal generating circuit 2 with the signal from the output terminal 25 of
A signal is taken out to the output terminal 26 of No. 4 and the result of addition of this signal and the frequency division ratio input signal of the fractional part in the adder circuit 27 is output to the output terminal 28 for data input of the ΔΣ circuit.

The operation of the frequency synthesizer configured as described above will be described below.

When the ambient temperature changes, the frequency of the crystal oscillator normally exhibits a temperature characteristic of a cubic function with a change width of several tens of ppm. At this time, in the control signal generation circuit 24 which receives the signal from the output terminal 25 of the temperature detection circuit 23, a cubic function having a phase opposite to the temperature fluctuation of the crystal oscillator is generated, and this value is divided by the division ratio of the fractional part. It is used as correction data. As a result, the temperature fluctuation of the output frequency of the frequency synthesizer can be reduced.

Further, the correction data of the frequency division ratio is digital data for controlling the variable frequency division circuit 10, and is due to the noise of the analog circuit being mixed in the reference signal as in the case of FIG. 3 in the prior art. There is no deterioration of C / N,
It is possible to realize a synthesizer with a good C / N.

A second embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing the structure of a frequency synthesizer with a temperature compensation function according to a second embodiment of the present invention. 2 is the same as FIG. 1 with respect to the basic configuration and operation of the frequency synthesizer, and the configuration and operation as a fractional frequency division PLL. The difference from Fig. 1 is that
A D flip-flop (hereinafter referred to as D F / F) 3 having a terminal 30 as a clock input between the signal at the output terminal 26 of the control signal generating circuit 24 and the input terminal 29 of the adding circuit 27.
This is the point where 1 is inserted.

Next, the operation of the second embodiment will be described. The basic operation of the frequency synthesizer with a temperature compensation function is the same as that of the first embodiment. In the first embodiment, the correction data for temperature compensation is digitized to prevent the C / N from deteriorating due to the noise generated in the analog circuit. When the division ratio is changed, a transient change in the output frequency is expected at the time when the division ratio changes. This transient change in frequency may cause malfunction. Therefore, in the second embodiment, in order to prevent malfunction due to transient fluctuations in the output frequency, a D F / F 31 is inserted between the control signal generation circuit 24 and the addition circuit 27 to change the frequency division ratio in the channel. The DF / F operation is performed by a signal given to the input terminal 30 so as to respond only to the timing when the transient change of the output frequency is allowed at the time of switching.

[0023]

As described above, according to the present invention, in the frequency synthesizer using the output of the crystal oscillator without the temperature compensation function as the reference signal, the frequency division ratio of the fractional frequency division PLL is changed in accordance with the change of the ambient temperature. The present invention realizes a frequency synthesizer with little fluctuation and good C / N.

Further, according to the present invention, by limiting the change of the fractional frequency division ratio only to the timing when the transient fluctuation of the output frequency is allowed, the malfunction due to the transient fluctuation of the output frequency when the ambient temperature changes is caused. To prevent.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a frequency synthesizer with a temperature compensation function according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a frequency synthesizer with a temperature compensation function according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional temperature-compensated crystal oscillator.

FIG. 4 is a block diagram of a conventional fractional frequency division PLL frequency synthesizer.

[Explanation of symbols]

1 Temperature detection circuit 2 Control signal generation circuit 4 Voltage controlled crystal oscillator (VCXO) 6 output terminals 7 Temperature compensated crystal oscillator (TCXO) 8 Reference frequency divider 9 Voltage controlled oscillator (VCO) 10 Variable frequency divider 11 Phase comparator 12 Low-pass filter 13 Frequency synthesizer output terminal 14 input terminals 15 input terminals 16 Output section 17 ΔΣ circuit 18 output terminals 20 Output section 21 Crystal oscillator (XO) 22 output terminals 23 Temperature detection circuit 24 Control signal generation circuit 25 output terminals 26 output terminals 27 Adder circuit 28 output terminals 29 input terminals 30 D F / F clock input terminal 31 D F / F circuit

Claims (2)

[Claims] 1. A crystal oscillator output frequency is provided by comprising a fractional frequency division PLL frequency synthesizer using a crystal oscillator without temperature compensation as a reference input, and changing the frequency division ratio of the fractional frequency division PLL according to ambient temperature changes. A frequency synthesizer characterized by compensating for temperature fluctuations in the. 2. The frequency synthesizer according to claim 1, wherein the fractional frequency division PL when the ambient temperature changes.
A frequency synthesizer characterized in that the frequency division ratio of L is changed only at a timing when a transient fluctuation of the output frequency is allowed.