JP2015207805A - Phase synchronous circuit and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase signal quality while suppressing increase of a circuit scale.SOLUTION: A phase difference detector 210 detects a phase difference between an input signal at a predetermined frequency and a feedback signal. In an oscillator 240, having a plurality of delay elements connected circularly, the plurality of delay elements generate a plurality of oscillation signals, having mutually different phases from the phase difference. A delta-sigma modulator 250 quantizes a predetermined real number to an integer number corresponding to either one of the plurality of oscillation signals by delta-sigma modulation. A feedback unit 280 provides a signal, synchronized to an oscillation signal corresponding to the integer number, as a feedback signal.

Description

  The present technology relates to a phase locked loop circuit and an electronic device. Specifically, the present invention relates to a phase synchronization circuit and an electronic device that multiply the frequency.

  Conventionally, in an electronic device, a phase locked loop is used for the purpose of generating clock signals of various frequencies. This phase synchronization circuit is classified into a normal phase synchronization circuit that multiplies a frequency by an integer multiplication ratio and a fractional phase synchronization circuit that can multiply a frequency by a non-integer multiplication ratio. A fractional phase locked loop generally includes a phase difference detector, an oscillator, a frequency divider, and a delta-sigma modulator. In this general fractional phase locked loop, the phase can be adjusted only in units of the oscillation period of the oscillator. Therefore, a fractional phase synchronization circuit to which a delay synchronization circuit and a multiplexer are added has been proposed for the purpose of adjusting the phase in units smaller than the oscillation period (see, for example, Non-Patent Document 1).

  In the above-described fractional phase locked loop circuit, the feedback frequency divider divides the output clock signal from the oscillator, and the delay locked loop circuit generates a plurality of oscillation signals having different phases from the divided output clock signal. On the other hand, the delta-sigma modulator quantizes the non-integer multiplication ratio into an integer value and outputs the result to the multiplexer. The multiplexer then selects a signal corresponding to the integer value from the plurality of oscillation signals and feeds it back to the phase difference detector. With this configuration, the non-integer multiplication phase locked loop circuit can adjust the phase in units smaller than the oscillation period of the oscillator and improve the signal quality.

Kuo-Hsing, et al., A 0.77 ps RMS Jitter 6-GHz Spread-SpectrumClock Generator Using a Compensated, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011.

  However, although the signal quality is improved in the above-described prior art, there is a problem that the circuit scale is increased by adding a delay synchronization circuit and a multiplexer. In addition, power consumption increases as the circuit scale increases. For this reason, it is difficult to generate a clock signal with less noise while suppressing an increase in circuit scale.

  The present technology has been created in view of such a situation, and an object thereof is to improve signal quality while suppressing an increase in circuit scale.

  The present technology has been made to solve the above-described problems. The first aspect of the present technology includes a phase difference detector that detects a phase difference between an input signal having a predetermined input frequency and a feedback signal, and a phase difference between the input signal and the feedback signal. An oscillator in which a plurality of delay elements that generate a plurality of oscillation signals having different values from the phase difference are connected in a ring and a predetermined real number is quantized to an integer value corresponding to one of the plurality of oscillation signals by delta-sigma modulation And a feedback unit that supplies a signal synchronized with the oscillation signal corresponding to the integer value as the feedback signal. As a result, a plurality of oscillation signals having different phases are generated from the phase difference.

  The first aspect further includes a frequency divider that divides a specific signal among the plurality of oscillation signals and supplies the frequency-divided signal as a frequency-divided signal, and the feedback unit corresponds to the integer value. A selection unit that selects an oscillation signal from the plurality of oscillation signals and a feedback signal supply unit that supplies the divided signal as the feedback signal in synchronization with the selected oscillation signal may be provided. This brings about the effect that a specific signal among the plurality of oscillation signals is divided.

  In the first aspect, the delta-sigma modulator quantizes the predetermined real number into the integer value and a division ratio for dividing the specific signal by the delta-sigma modulation. May divide the specific signal according to the division ratio. As a result, the specific signal is frequency-divided according to the frequency division ratio quantized by delta-sigma modulation.

  In the first aspect, the phase difference detector is a time digital converter that generates a digital signal indicating the detected phase difference, and the oscillator converts a plurality of oscillation signals having different phases into the digital signal. It may be a digitally controlled oscillator in which a plurality of delay elements generated from a signal are connected in a ring shape. Thus, a digital signal indicating a phase difference is generated, and a plurality of oscillation signals are generated from the digital signal.

  In the first aspect, the phase difference detector generates an analog signal having a voltage corresponding to the phase difference, and the oscillator generates a plurality of oscillation signals having different phases from the analog signal. The delay element may be a voltage-controlled oscillator connected in a ring shape. As a result, an analog signal having a voltage corresponding to the phase difference is generated, and a plurality of oscillation signals are generated from the analog signal.

The second aspect of the present technology includes a phase difference detector that detects a phase difference between an input signal having a predetermined input frequency and a feedback signal, and a plurality of oscillation signals having different phases from each other. An oscillator in which delay elements are connected in a ring, a delta-sigma modulator that quantizes a predetermined real number to an integer value corresponding to one of the plurality of oscillation signals by delta-sigma modulation, and the oscillation corresponding to the integer value An electronic apparatus comprising: a feedback unit that supplies a signal synchronized with a signal as the feedback signal; and a processing circuit that executes a predetermined process in synchronization with a specific signal among the plurality of oscillation signals. As a result, a plurality of oscillation signals having different phases are generated from the phase difference.

  According to the present technology, it is possible to achieve an excellent effect that signal quality can be improved while suppressing an increase in circuit scale. Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a block diagram which shows the example of 1 structure of the electronic device in 1st Embodiment. It is a block diagram which shows the example of 1 structure of the non-integer multiplication phase-locked loop in 1st Embodiment. FIG. 3 is a block diagram illustrating a configuration example of a multiphase output voltage controlled oscillator according to the first embodiment. It is a block diagram which shows the example of 1 structure of the delta-sigma modulator in 1st Embodiment. 6 is a timing chart illustrating an example of an operation of the electronic device according to the first embodiment. It is a block diagram which shows the example of 1 structure of the non-integer multiplication phase-locked loop in the modification of 1st Embodiment. It is a block diagram which shows the example of 1 structure of the non-integer multiplication phase-locked loop in 2nd Embodiment. It is a block diagram which shows the example of 1 structure of the non-integer multiplication phase-locked loop in 3rd Embodiment.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First Embodiment (Example in which a voltage controlled oscillator for generating a plurality of oscillation signals is provided)
2. Second Embodiment (Example in which a variable frequency divider and a voltage controlled oscillator that generates a plurality of oscillation signals are provided)
3. Third embodiment (example in which a digitally controlled oscillator for generating a plurality of oscillation signals is provided)

<1. First Embodiment>
[Configuration example of electronic device]
FIG. 1 is a block diagram illustrating a configuration example of the electronic device 100 according to the first embodiment. The electronic device 100 includes a crystal resonator 110, a register 120, a processing circuit 130, and a non-integer multiplication phase synchronization circuit 200.

  The crystal unit 110 generates an input clock signal INCLK having a predetermined frequency using the piezoelectric effect of crystal. For example, a signal of 6 to 27 megahertz (MHz) is generated as the input clock signal INCLK. The crystal unit 110 supplies the generated input clock signal INCLK to the non-integer multiplication phase synchronization circuit 200 via the signal line 119.

  The register 120 stores the set value R of the multiplication ratio. As the set value R, for example, a predetermined real number is set. The non-integer multiplication phase synchronization circuit 200 multiplies the input clock signal INCLK by a real multiplication ratio (R) stored in the register 120 to generate an output clock signal OUTCLK. In this way, the non-integer multiplication phase synchronization circuit 200 that can be multiplied by a non-integer multiplication ratio in addition to an integer multiplication ratio is also called a fractional phase synchronization circuit. The non-integer multiplication phase synchronization circuit 200 supplies the generated output clock signal OUTCLK to the processing circuit 130 via the signal line 209. For example, a signal of 400 to 1500 megahertz (MHz) is generated as the input clock signal INCLK.

Here, the following relational expression is established between the frequency Fin of the input clock signal and the frequency Fout of the output clock signal OUTCLK multiplied by the set value R.
Fout = Fin × R
= Fin × (M + N) Equation 1
In the above equation, M is the integer part of the set value R, and N is the decimal part of the set value R.

  The processing circuit 130 performs predetermined processing in synchronization with the output clock signal OUTCLK. The processing circuit 130 performs, for example, transmission / reception processing and measurement processing in wireless communication. In the wireless communication transmission process, the processing circuit 130 may perform a spread spectrum process in which the frequency of the output clock signal OUTCLK is changed by updating the register 120 and the communication signal is spread and transmitted in a wider band than the original. Good.

[Configuration example of non-integer multiplication phase synchronization circuit]
FIG. 2 is a block diagram illustrating a configuration example of the non-integer multiplication phase synchronization circuit 200 according to the first embodiment. This non-integer multiplication phase synchronization circuit 200 includes a phase difference detector 210, a charge pump 220, a low-pass filter 230, a multiphase output voltage control oscillator 240, a delta-sigma modulator 250, a multiplexer 260, a fixed frequency divider 270, and a flip-flop 280. Is provided.

  The phase difference detector 210 detects the phase difference by comparing the phases of the input clock signal INCLK and the feedback clock signal FBCLK. The phase difference detector 210 supplies the charge pump 220 with a phase difference signal DIF having a voltage corresponding to the detected phase difference.

  The charge pump 220 boosts or lowers the voltage of the phase difference signal DIF. The charge pump 220 supplies the phase difference signal DIF obtained by converting the voltage to the low-pass filter 230.

  The low-pass filter 230 suppresses high frequency components higher than a predetermined cutoff frequency in the phase difference signal DIF. The low-pass filter 230 supplies a phase difference signal DIF in which high frequency components are suppressed to the multiphase output voltage controlled oscillator 240.

  The multiphase output voltage controlled oscillator 240 generates a plurality of oscillation signals having different phases based on the phase difference signal DIF. The multiphase output voltage controlled oscillator 240 supplies all of the generated oscillation signals to the multiplexer 260. The multiphase output voltage controlled oscillator 240 supplies a specific signal among the oscillation signals to the processing circuit 130 and the fixed frequency divider 270 as the output clock signal OUTCLK. The multiphase output voltage controlled oscillator 240 is an example of an oscillator and a voltage controlled oscillator described in the claims.

  The fixed frequency divider 270 divides the frequency of the output clock signal OUTCLK by a predetermined frequency division ratio Ndiv (Ndiv is an integer). The fixed frequency divider 270 supplies the divided signal to the flip-flop 280 and the delta-sigma modulator 250 as a divided clock signal DIVCLK. The fixed frequency divider 270 is an example of a frequency divider described in the claims.

  The delta sigma modulator 250 quantizes the real set value R into an integer value TAP by delta sigma modulation. This integer value TAP is a value corresponding to one of a plurality of oscillation signals from the multiphase output voltage controlled oscillator 240. The delta sigma modulator 250 supplies the integer value TAP to the multiplexer 260.

  The multiplexer 260 selects an oscillation signal corresponding to the integer value TAP from the oscillation signals generated by the multiphase output voltage controlled oscillator 240. The multiplexer 260 supplies the selected oscillation signal to the flip-flop 280 as the selected clock signal SELCLK.

  The flip-flop 280 holds the divided clock signal DIVCLK and outputs it to the phase difference detector 210 as a feedback clock signal FBCLK in synchronization with the selected clock signal SELCLK. As a result, a signal synchronized with the oscillation signal corresponding to the integer value TAP is fed back to the phase difference detector 210 as the feedback clock signal FBCLK. The circuit including the multiplexer 260 and the flip-flop 280 is an example of a feedback unit described in the claims. The multiplexer 260 is an example of a selection unit described in the claims, and the flip-flop 280 is an example of a feedback signal supply unit described in the claims.

[Configuration example of multi-phase output voltage controlled oscillator]
FIG. 3 is a block diagram showing a configuration example of the multiphase output voltage controlled oscillator 240 in the first embodiment. The multiphase output voltage controlled oscillator 240 includes P delay elements 241 connected in a ring shape.

  The delay element 241 delays the oscillation signal VCOCLK input from the preceding delay element 241 by a delay time corresponding to the phase difference indicated by the phase difference signal DIF, and supplies the delayed signal to the subsequent delay element 241. For example, an inverter is used as the delay element 241. Each of the delay elements 241 supplies the oscillation signal VCOCLK to the multiplexer 260. These oscillation signals are hereinafter referred to as oscillation signals VCOCLK_0 to VCOCLK_P-1. Among these, the oscillation signal VCOCLK_P-1 is supplied not only to the multiplexer 260 but also to the fixed frequency divider 270 and the processing circuit 130 as the output clock signal OUTCLK.

[Configuration example of delta-sigma modulator]
FIG. 4 is a block diagram illustrating a configuration example of the delta-sigma modulator 250 according to the first embodiment. The delta sigma modulator 250 includes a subtractor 251, an integrator 252, a quantizer 253, and an inverse quantizer 254.

  The subtracter 251 obtains a difference between the set value R of the multiplication ratio stored in the register 120 and the current value R ′ of the multiplication ratio obtained from the inverse quantizer 254. The subtractor 251 supplies the difference to the integrator 252.

  The integrator 252 integrates the difference in synchronization with the divided clock signal DIVCLK. The integrator 252 supplies the integrated value to the quantizer 253.

  The quantizer 253 quantizes the integrated value into an integer value TAP from 0 to P-1. For example, the quantizer 253 obtains a TAP that minimizes the error between d (Tpd × TAP) / dt and the integrated value × Fin from 0 to P−1. Here, Tpd indicates the delay time of the one-stage delay element 241. The unit of the delay time Tpd is, for example, microseconds (μs). D / dT represents time differentiation. The quantizer 253 supplies the obtained integer value TAP to the multiplexer 260 and the inverse quantizer 254.

The inverse quantizer 254 inversely quantizes the integer value TAP to the current value R ′ of the multiplication ratio. The integer value TAP is inversely quantized by the following equation, for example. The inverse quantizer 254 supplies the current value R ′ to the subtractor 251.
Fin = Fout ′ / Ndiv + d (Tpd × TAP) / dt Equation 2
R '= Fout' / Fin ... Formula 3
In the above equation, Fout ′ represents the current value of the frequency of the output clock signal OUTCLK.

  Thus, signal processing for integrating the difference (delta) between the set value and the current value and quantizing the integrated value (sigma) is called delta-sigma modulation.

[Example of operation of electronic device]
FIG. 5 is a timing chart illustrating an example of the operation of the electronic device 100 according to the first embodiment.

  In the electronic device 100, the multiphase output voltage controlled oscillator 240 generates the output clock signal OUTCLK. A fixed frequency divider 270 divides the output clock signal OUTCLK by an integer frequency division ratio Ndiv to generate a divided clock signal DIVCLK.

  The delta sigma modulator 250 quantizes the set value R into an integer value TAP by delta sigma modulation.

  The flip-flop 280 holds the divided clock signal DIVCLK and outputs it as a feedback clock signal FBCLK in synchronization with the oscillation signal VCOCLK corresponding to the integer value TAP. As a result, the feedback clock signal FBCLK divided by a non-integer division ratio is generated. Based on the phase difference between the feedback clock signal FBCLK and the input clock signal INCLK, the multi-phase output voltage controlled oscillator 240 generates the output clock signal OUTCLK. The output clock signal OUTCLK is a clock signal obtained by multiplying the input clock signal INCLK by a non-integer multiplication ratio.

  As illustrated in FIG. 5, the non-integer multiplication phase synchronization circuit 200 retimes the divided clock signal DIVCLK obtained by dividing the output clock signal OUTCLK with the oscillation signal VCOCLK having a smaller phase difference than the period of those signals. ing. For this reason, the non-integer multiplication phase synchronization circuit 200 can control the phase in units smaller than the oscillation period of the output clock signal OUTCLK. On the other hand, in a general phase synchronization circuit in which the multiplexer 260 and the flip-flop 280 are not provided, the phase can be controlled only by the unit of the cycle of the output clock signal OUTCLK. Therefore, as compared with such a general circuit, the non-integer multiplication phase synchronization circuit 200 can control the phase in smaller units. Thereby, signal quality can be improved.

  Further, in the non-integer multiplication phase synchronization circuit 200, since the multiphase output voltage control oscillator 240 generates a plurality of oscillation signals, the delay synchronization circuit generates a plurality of oscillation signals. In contrast, there is no need to provide a delay synchronization circuit. For this reason, compared with the circuit described in Non-Patent Document 1, the circuit scale and power consumption can be reduced.

  As described above, according to the first embodiment of the present technology, since the multiphase output voltage controlled oscillator 240 generates a plurality of oscillation signals, there is no need to provide a delay synchronization circuit that generates a plurality of oscillation signals. An increase in circuit scale can be suppressed.

[Modification]
In the first embodiment, the non-integer multiplication phase synchronization circuit 200 divides the output clock signal OUTCLK by the fixed divider 270, but the fixed divider 270 may not be provided.

  FIG. 6 is a block diagram illustrating a configuration example of the non-integer multiplication phase synchronization circuit 200 according to the modification of the first embodiment. The non-integer multiplication phase synchronization circuit 200 according to the modification is different from the first embodiment in that the fixed frequency divider 270 and the flip-flop 280 are not provided.

  The modified example of the delta-sigma modulator 250 performs quantization and inverse quantization with the division ratio Ndiv set to “1”.

  Further, the multiplexer 260 according to the modification supplies an oscillation signal corresponding to the integer value TAP to the phase difference detector 210 as a feedback clock signal FBCLK.

  As described above, according to the modification, the non-integer multiplication phase synchronization circuit 200 feeds back the oscillation signal as a feedback clock signal without dividing the oscillation signal, so that there is no need to provide the fixed divider 270 and the flip-flop 280. An increase in circuit scale can be suppressed.

<2. Second Embodiment>
In the first embodiment, the non-integer multiplication phase synchronization circuit 200 divides the output clock signal OUTCLK by a fixed division ratio, but dynamically changes the division ratio for the output clock signal OUTCLK. Also good. The non-integer multiplication phase synchronization circuit 200 according to the second embodiment differs from the first embodiment in that the frequency division ratio is dynamically changed.

  FIG. 7 is a block diagram illustrating a configuration example of the non-integer multiplication phase synchronization circuit 200 according to the second embodiment. The non-integer multiplication phase synchronization circuit 200 according to the second embodiment is different from the first embodiment in that a variable frequency divider 271 and a delta sigma modulator 255 are provided instead of the fixed frequency divider 270 and the delta sigma modulator 250. Different from form.

  The delta sigma modulator 255 quantizes the integrated value into n + m bits. Of the n + m bits, m bits indicate an integer value TAP, and n bits indicate a frequency division ratio Ndiv. The integer value TAP is supplied to the multiplexer 260, and the frequency division ratio Ndiv is supplied to the variable frequency divider 271.

  The variable frequency divider 271 divides the output clock signal OUTCLK by the frequency division ratio Ndiv from the delta sigma modulator 255.

  Thus, according to the second embodiment, since the frequency division ratio of the variable frequency divider 271 can be changed, the frequency of the output clock signal OUTCLK can be compared with the configuration in which the frequency division ratio is fixed. The control range can be widened.

<3. Third Embodiment>
In the first embodiment, the non-integer multiplication phase synchronization circuit 200 generates an analog phase difference signal DIF, and an oscillation signal is generated from the phase difference signal DIF by an analog circuit (such as a multiphase output voltage control oscillator 240). It was generated. However, the non-integer multiplication phase synchronization circuit 200 may generate a digital phase difference signal DIF and generate an oscillation signal by the digital circuit. The non-integer multiplication phase synchronization circuit 200 according to the third embodiment is different from the first embodiment in that an oscillation signal is generated by a digital circuit.

  FIG. 8 is a block diagram illustrating a configuration example of the non-integer multiplication phase synchronization circuit 200 according to the third embodiment. The non-integer multiplication phase synchronization circuit 200 according to the third embodiment includes a time digital converter 290, a digital filter 231, a multiphase output digital control oscillator 245, a delta sigma modulator 255, and a multiplexer 260.

  The time digital converter 290 detects the phase difference by comparing the phases of the input clock signal INCLK and the feedback clock signal FBCLK. The phase difference detector 210 supplies a digital phase difference signal DIF indicating the detected phase difference to the digital filter 231.

  The digital filter 231 suppresses high frequency components higher than a predetermined cutoff frequency in the phase difference signal DIF. As this digital filter 231, for example, an IIR (Infinite Impulse Response) filter or an FIR (Finite Impulse Response) filter is used. The digital filter 231 supplies the multi-phase output digital control oscillator 245 with the phase difference signal DIF in which the high frequency component is suppressed.

  The configuration of the delta-sigma modulator 255 of the third embodiment is the same as that of the second embodiment. However, the frequency division ratio Ndiv is supplied to the multiphase output digital control oscillator 245.

  The multiphase output digital control oscillator 245 generates an output clock signal OUTCLK based on the phase difference signal DIF. Further, the multiphase output digital control oscillator 245 divides the output clock signal OUTCLK by the frequency division ratio Ndiv, generates a plurality of oscillation signals from the divided signals, and supplies them to the multiplexer 260. As this multiphase output digitally controlled oscillator 245, for example, “Ramesh K. Pokharel, et al., Digitally Controlled Ring Oscillator Using Fraction-Based Series Optimization for Inductorless Reconfigurable All-Digital PLL, 2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems "FIG. 2 is used.

  The multiphase output digitally controlled oscillator 245 is an example of a digitally controlled oscillator described in the claims.

  The multiplexer 260 according to the third embodiment supplies the oscillation signal corresponding to the integer value TAP to the time digital converter 290 as the feedback clock signal FBCLK.

  Thus, according to the third embodiment, since the non-integer multiplication phase synchronization circuit 200 generates an oscillation signal by a digital circuit, the circuit scale is reduced as compared with the case where an oscillation signal is generated by an analog circuit. can do.

  The above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the invention-specific matters in the claims have a corresponding relationship. Similarly, the invention specific matter in the claims and the matter in the embodiment of the present technology having the same name as this have a corresponding relationship. However, the present technology is not limited to the embodiment, and can be embodied by making various modifications to the embodiment without departing from the gist thereof.

  Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

In addition, this technique can also take the following structures.
(1) a phase difference detector for detecting a phase difference between an input signal having a predetermined input frequency and a feedback signal;
An oscillator in which a plurality of delay elements that generate a plurality of oscillation signals having different phases from each other from the phase difference are connected in a ring shape;
A delta-sigma modulator that quantizes a predetermined real number into an integer value corresponding to any of the plurality of oscillation signals by delta-sigma modulation;
A phase synchronization circuit comprising: a feedback unit that supplies, as the feedback signal, a signal synchronized with the oscillation signal corresponding to the integer value.
(2) further comprising a frequency divider that divides and supplies a specific signal among the plurality of oscillation signals as a frequency-divided signal;
The feedback section is
A selection unit for selecting the oscillation signal corresponding to the integer value from the plurality of oscillation signals;
The phase synchronization circuit according to (1), further comprising a feedback signal supply unit that supplies the frequency-divided signal as the feedback signal in synchronization with the selected oscillation signal.
(3) The delta-sigma modulator quantizes the predetermined real number into the integer value and a division ratio for dividing the specific signal by the delta-sigma modulation,
The phase synchronization circuit according to (2), wherein the frequency divider divides the specific signal according to the frequency division ratio.
(4) The phase difference detector is a time digital converter that generates a digital signal indicating the detected phase difference,
The phase synchronization according to any one of (1) to (3), wherein the oscillator is a digitally controlled oscillator in which a plurality of delay elements that generate a plurality of oscillation signals having different phases from each other are annularly connected. circuit.
(5) The phase difference detector generates an analog signal having a voltage corresponding to the phase difference,
The phase synchronization according to any one of (1) to (3), wherein the oscillator is a voltage-controlled oscillator in which a plurality of delay elements that generate a plurality of oscillation signals having different phases from the analog signal are connected in a ring shape. circuit.
(6) a phase difference detector for detecting a phase difference between an input signal having a predetermined input frequency and a feedback signal;
An oscillator in which a plurality of delay elements that generate a plurality of oscillation signals having different phases from each other from the phase difference are connected in a ring shape;
A delta-sigma modulator that quantizes a predetermined real number into an integer value corresponding to any of the plurality of oscillation signals by delta-sigma modulation;
A feedback unit for supplying a signal synchronized with the oscillation signal corresponding to the integer value as the feedback signal;
An electronic apparatus comprising: a processing circuit that executes predetermined processing in synchronization with a specific signal among the plurality of oscillation signals.

DESCRIPTION OF SYMBOLS 100 Electronic device 110 Crystal oscillator 120 Register 130 Processing circuit 200 Non-integer multiplication phase synchronization circuit 210 Phase difference detector 220 Charge pump 230 Low pass filter 231 Digital filter 240 Multiphase output voltage control oscillator 241 Delay element 245 Multiphase output digital control oscillator 250, 255 Delta-sigma modulator 251 Subtractor 252 Integrator 253 Quantizer 254 Inverse quantizer 260 Multiplexer 270 Fixed divider 271 Variable divider 280 Flip-flop 290 Time digital converter

Claims (6)

A phase difference detector for detecting a phase difference between an input signal of a predetermined input frequency and a feedback signal;
An oscillator in which a plurality of delay elements that generate a plurality of oscillation signals having different phases from each other from the phase difference are connected in a ring shape;
A delta-sigma modulator that quantizes a predetermined real number into an integer value corresponding to any of the plurality of oscillation signals by delta-sigma modulation;
A phase synchronization circuit comprising: a feedback unit that supplies, as the feedback signal, a signal synchronized with the oscillation signal corresponding to the integer value. A frequency divider that divides a specific signal among the plurality of oscillation signals and supplies the divided signal as a divided signal;
The feedback section is
A selection unit for selecting the oscillation signal corresponding to the integer value from the plurality of oscillation signals;
The phase synchronization circuit according to claim 1, further comprising a feedback signal supply unit that supplies the divided signal as the feedback signal in synchronization with the selected oscillation signal. The delta-sigma modulator quantizes the predetermined real number into the integer value and a division ratio for dividing the specific signal by the delta-sigma modulation,
The phase synchronization circuit according to claim 2, wherein the frequency divider divides the specific signal according to the frequency division ratio. The phase difference detector is a time digital converter that generates a digital signal indicating the detected phase difference,
2. The phase locked loop circuit according to claim 1, wherein the oscillator is a digitally controlled oscillator in which a plurality of delay elements that generate a plurality of oscillation signals having different phases from each other are connected in a ring shape. The phase difference detector generates an analog signal having a voltage corresponding to the phase difference,
2. The phase locked loop according to claim 1, wherein the oscillator is a voltage controlled oscillator in which a plurality of delay elements that generate a plurality of oscillation signals having different phases from the analog signal are connected in a ring shape. A phase difference detector for detecting a phase difference between an input signal of a predetermined input frequency and a feedback signal;
An oscillator in which a plurality of delay elements that generate a plurality of oscillation signals having different phases from each other from the phase difference are connected in a ring shape;
A delta-sigma modulator that quantizes a predetermined real number into an integer value corresponding to any of the plurality of oscillation signals by delta-sigma modulation;
A feedback unit for supplying a signal synchronized with the oscillation signal corresponding to the integer value as the feedback signal;
An electronic apparatus comprising: a processing circuit that executes predetermined processing in synchronization with a specific signal among the plurality of oscillation signals.

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