RU66132U1 - DIGITAL FREQUENCY SYNTHESIS WITH FREQUENCY MODULATION - Google Patents

Abstract

The utility model relates to radio engineering and can be used as a transmitter exciter and a receiver local oscillator.

The technical result is a significant increase in the speed of the synthesizer when switching output frequencies.

For this, the proposed device includes: a third controlled generator and a switching unit, the output of which is the output of the synthesizer.

Description

The utility model relates to radio engineering and can be used as the exciter of a transmitter with frequency modulation and a local oscillator of the receiver.

Known dual-ring digital frequency synthesizer (DSC) with frequency modulation (FM) with the sequential inclusion of rings, built on the basis of a pulse-phase-locked loop (IFAP) with a frequency divider with a variable division ratio (DPC) in the feedback circuit of each ring (see certificate Utility Model No. 30043 of 08/26/2002).

In this DSC, the first IFAPC ring is narrow-band, operates at the same frequency as the FM output signal, which is the reference for the second ring.

The second IFAPCH ring (output) is connected in series with the first and is wide-range, high-speed (due to the use of fractional DPKD), and can operate at ultra-high frequencies. The modulating signal for the second ring is contained in its reference signal from the output of a controlled generator (UG) of the first ring.

In this DSS with FM, the functions of frequency formation and modulation are divided between the first and second IFAPH rings, which reduces the known contradictions. Two-point frequency modulation is carried out in the first ring operating at one fixed frequency, and wide-range frequency tuning and speed when switching frequencies in the second IFAPC ring.

A disadvantage of the known device is the inability at the present time to implement point-to-point modulation by introducing an FM in the UG and at the modulating input of a phase modulator connected between the divider

frequency and the input of the frequency-phase detector (ChFD), since the produced DSP chips do not have a separate accessible input to the ChFD (everything is inside the “chip” of the DSC chip). In addition, this synthesizer lacks the purity of the spectrum of the output signal.

The closest in technical essence to the proposed one is a two-ring DSC with frequency modulation (see patent for utility model No. 56747 dated 04/17/2006), which is adopted as a prototype.

The block diagram of the prototype device is shown in figure 1, where the following notation is introduced:

1 - reference generator (OG);

2, 7 and 14 - the first, second and third frequency dividers with a fixed division ratio (DPCD);

3, 8 and 15 - the first, second and third frequency-phase detectors (ChFD);

4, 9 and 16 - the first, second and third low-pass filters (low-pass filters);

5 and 11 - the first and second controlled generators (UG);

6, 12 and 19 - the first, second and third frequency dividers with a variable division ratio (DPKD);

10 - source modulating signal (IC);

13 and 21 - the first and second controlled attenuators (UA);

17, 18, 20 and 22 - the first, second, third and fourth keys (KL);

23 - microcontroller (MK).

The prototype device contains a series-connected reference generator (OG 1), the first frequency divider with a fixed division ratio (DPCD 2), the first frequency-phase detector ChFD 3, the first low-pass filter (low-pass filter 4), the first UG 5 and the first DPKD 6, the output of which is connected to the second input of the first ChFD 3, serially connected to the second DFKD 7, the second ChFD 8, the second low-pass filter 9, the first key KL 17, the second UG 11 and the second DPKD 12, the output of which is connected to the second input of the second ChFD 8; connected in series with the third DFKD 14, the third ChFD 15, the third low-pass filter 16 and the second KL 18, the output of which is connected to the output of the first key

KL 17 and with the first control input of the second UG 11, the output of which is the device’s output and simultaneously through the third DPKD 19 is connected to the second input of the third ChFD 15, the source of the modulating signal IC 10 is connected in series, the first is controlled attenuator UA 13, the third key is KL 20, the output which is connected to the modulating input of the first UG 5, serially connected to the second UA 21 and the fourth key KL 22, the output of which is connected to the modulating input of the second UG 11, as well as the microcontroller MK 23.

The output of the first UG 5 is connected to the signal inputs of the second DFKD 7 and the third DFKD 14, the input of the second UA 21 is connected to the output of the IC 10, the first output bus MK 23 is connected to the control inputs of the first DPKD 6, the second DPKD 12, the third DPKD 19, the second ChFD 8, third ChFD 15, second DFKD 7, third DFKD 14, the first UA 13 and the second UA 21, and the second output bus MK 23 is connected to the control inputs of the first KL 17, the second KL 18, the third KL 20, the fourth KL 22 and the second control input of the second UG 11.

The prototype device operates as follows.

In this FM CSC, based on two IFAPC rings in series, the first ring is narrow-band, operates at one fixed frequency and is based on the first UG 5, the output signal of which is a reference for the second ring and enters the second ring at the signal inputs of the second DFKD 7 and the third DFKD 14. The second IFAPCH ring based on the second UG 11 is two-channel - it can work either on the channel of fast frequency switching according to a given program using the second (fractional) DPKD 12, the second ChFD 8 and the second low-pass filter 9 or on the channel The normal operation of the DSC using the third (integer) DPKD 19, the third ChFD 15 and the third low-pass filter 16. The range of output frequencies and the frequency grid spacing on both channels are the same. Their difference is that the comparison frequency F _cp at the reference input of the second PSD 8 in the channel of fast switching of frequencies is formed using the second DPCD 7 from the first UG 5 and is selected

the maximum possible one - many times more than the specified frequency grid step (F _cp ≫F _w ) to obtain maximum speed (due to the use of fractional DPKD). And in the second channel, on the basis of the third (integer) DPKD 19, using the third DFKD 14, the comparison frequency F _cp is formed from the first UG 5, not exceeding the specified frequency grid spacing. In this channel, the performance is much less than in the first channel.

Frequency modulation in each channel is carried out according to a two-point scheme, when the modulating signal arrives from the IC 10 simultaneously through the first UA 13 and the third KL 20 to the modulating input of the first UG 5 and through the second UA 21 and the fourth KL 22 to the modulating input of the second UG 11.

The first or second channel is switched on using the appropriate keys: the first KL 17 or the second KL 18, which are switched by control signals received via the second control bus from MK 23.

The advantage of this method of introducing FM is the possibility of obtaining a uniform amplitude-frequency modulation characteristic (AFC) in a wide range of modulating frequencies.

A disadvantage of the known device is as follows.

When switching from one frequency to another in the second IFAPC ring, the DSC due to the inertia of the loop low-pass filter (low-pass filter 9 or low-pass filter 16) there is a transient process of establishing the control voltage V _control at the control input of UG 11 to a new frequency with a transition time t _lane (see time the diagram in figure 2 - times t _per from t ₁ to t ₂ from t ₃ to t ₄ , etc.). Each frequency of UG 11 has its own control voltage V _control at its input, which is formed after the loop low-pass filter (in Fig. 2 for frequency F ₁ - V _{control 1} , for frequency F ₂ - V _{control 2} , etc.). After the end of the transition process, a stationary synchronism mode is established at the new frequency F ₁ or F ₂ . This can be called a time t _st standing on the new frequency at which the receiving or transmitting information in a radio communication system. The standing time at one frequency is constant and the minimum possible for

such radio communication systems. Hence, the total residence time at a given frequency t _total at a certain control voltage V _control consists of two segments t _total = t _per + t _article (see timing diagrams in figure 2). For normal operation of the radio communication system (without loss of information), there should be t _st ≫t _per . In radio communication systems with fast frequency switching according to a given program, to increase noise immunity, there is a general tendency to decrease the standby time t _st at one frequency, i.e. the number of frequency switching per unit of time increases. If at the same time no measures are taken to a corresponding or even more significant reduction in the transition time t _per (i.e., to increase speed), then the proportion of t _per in the total operating time t _total at one frequency t _total = t _per + t _article becomes unacceptable large and limits the ability to work in this mode due to loss of information.

Thus, the insufficient speed of a known device often does not allow to realize a mode of operation with fast frequency switching according to a given program or a temporary duplex mode (i.e., when reception and transmission are carried out at the same frequency).

To eliminate this drawback in a digital frequency synthesizer with frequency modulation, containing a series-connected reference oscillator, a first frequency divider with a fixed division ratio, a first frequency-phase detector, a first low-pass filter, a first controlled oscillator and a first frequency divider with a variable division ratio, output which is connected to the second input of the first frequency-phase detector; a second frequency divider with a fixed division coefficient, a second frequency-phase detector and a second low-pass filter connected in series; a third frequency divider with a fixed division coefficient, a third frequency-phase detector and a third low-pass filter connected in series; a second controlled oscillator and a second frequency divider with a variable division ratio, the output of which is connected to the second

the input of the second frequency-phase detector; connected in series with the source of the modulating signal, the first controlled attenuator and the third key, the output of which is connected to the modulating input of the first controlled generator; the second controlled attenuator and the fourth switch are connected in series, the output of which is connected to the modulating input of the second controlled generator, the input of the second controlled attenuator connected to the output of the modulating signal source, and a third frequency divider with a variable division coefficient, the output of which is connected to the second input of the third frequency a phase detector, and a microcontroller, the first control bus of which is connected to the control inputs of the first, second and third frequency divider with a division coefficient, a second and third frequency-phase detector, a second and third frequency divider with a fixed division coefficient, the first and second controlled attenuator, and the second control bus of the microcontroller is connected to the control inputs of the third and fourth keys and the second control input of the second controlled generator, the output of the first controlled generator is also connected to the signal inputs of the second and third frequency divider with a fixed division coefficient, therefore, the connected third controlled generator and the switching unit, the second input of which is connected to the output of the second controlled generator, and the control input of the switching unit is connected to the second control bus of the microcontroller. In this case, the first control input of the second controlled generator is connected to the output of the second low-pass filter, the first control input of the third controlled generator is connected to the output of the third low-pass filter, the output of the third controlled generator is connected to the input of the third frequency divider with a variable division factor, the second control input of the third controlled the generator is connected to the second control bus of the microcontroller, the modulating input of the third controlled generator is connected to the output

the fourth key and with the modulating input of the second controlled generator, and the output of the switching unit is the output of the device.

A block diagram of the proposed device is shown in figure 3, where the following notation is introduced:

1 - reference generator (OG);

2, 7, 14 - the first, second and third frequency dividers with a fixed division ratio (DPCD);

3, 8, 15 - the first, second and third frequency-phase detector (ChFD);

4, 9, 16 - the first, second and third low-pass filter (low-pass filter);

5, 11, 24 - the first, second and third controlled generator (UG);

6, 12, 19 - the first, second and third frequency divider with a variable division ratio (DPKD);

10 - source modulating signal (IC);

13, 21 - the first and second controlled attenuator (UA);

20, 22 - the third and fourth keys (KL);

23 - microcontroller (MK);

25 - switching unit (BC).

The proposed device contains a series-connected reference generator OG 1, the first DPCD 2, the first ChFD 3, the first low-pass filter 4, the first UG 5 and the first DPKD 6, the output of which is connected to the second input of the first ChFD 3; connected in series to the second DPCD 7, the second ChFD 8, the second low-pass filter 9, the second UG 11, the output of which is connected to the second signal input of the BK 25 and through the second DPKD 12 is connected to the second input of the second ChFD 8; the third DPCD 14, the third ChFD 15, the third low-pass filter 16 and the third UG 24, the output of which is connected to the first signal input of the BK 25 and through the third DPKD 19 is connected to the second input of the third ChFD 15 in series; sequentially connected IC 10, the first UA 13, the third key KL 20, the output of which is connected to the modulating input of the first UG 5; serially connected to the second UA 21, the fourth key KL 22, the output of which is connected to the modulating inputs of the second UG 11 and the third UG 24,

as well as the MK 23 microcontroller and the switching unit BK 25. In this case, the input of the second UA 21 is connected to the output of the IC 10, the signal inputs of the second DFKD 7 and the third DFKD 14 are connected to the output of the first UG 5, the first control bus MK 23 is connected to the control inputs of the first DPCD 6, the second DFKD 7, the second ChFD 8, the second DPKD 12, the third DFKD 14, the third ChFD 15, the third DPKD 19, the first UA 13 and the second UA 21; the second control bus MK 23 is connected to the control inputs of the third KL 20 and the fourth KL 22, the second control inputs of the second UG 11 and the third UG 24 and the control input of the BK 25, the output of which is the output of the device.

The proposed device operates as follows.

In this CSC with FM, three IFAPCH rings function simultaneously. The first IFAPC ring is narrow-band, operates at one fixed frequency, which is a reference at the same time for the second and third rings. The second and third rings are connected in parallel, the frequency range, frequency grid pitch and speed are the same. The first ring is made on the basis of a series-connected first UG 5, the first DPKD 6, the first ChFD 3 and the first low-pass filter 4, the output of which is connected to the control input of the first UG 5. The reference input of the first ChFD 3 is supplied from OG 1 through the first DPCD 2 reference pulse signal with a sufficiently high comparison frequency, which, with a narrow passband of the ring, allows significant interference suppression in the control signal supplied to the corresponding input of UT 5 and to obtain a spectrally pure signal at its output. This signal also acts as a reference signal to the reference inputs of the second and third rings, which are respectively the signal inputs of the second DFKD 7 and the third DFKD 14. In other words, the second and third rings are connected in parallel with each other and in series with the first IFAPC ring. In the operation mode of the DSC as a transmitter exciter (PRD) in the first IFAPC ring, a single-point FM occurs at the modulating input of UG 5, i.e. in this mode, the reference signal for the second and third rings is frequency-modulated.

The second ring is made on the basis of the second UG 11, the second DPKD 12, the second ChFD 8 and the second low-pass filter 9 connected in series, the output of which is connected to the first control input of the second UG 11. The reference signal (modulated or not modulated in frequency) from the first UG 5 of the first IFAPCH ring.

The third ring is made on the basis of the third UGD 24, the third DPKD 19, the third ChFD 15 and the third low-pass filter 16, the output of which is connected to the first control input of the third UG 24 in series. The reference signal from the first UGD 14 is supplied to the reference input of the third ChFD 15 5 of the first IFAPCH ring (with FM or without frequency modulation).

Frequency dividers with a variable division coefficient (DPKD) in the second and third rings are the same: both fractional (DPKD) or integer depending on the given requirements.

In the fast frequency switching mode according to a given program, the total time spent at one of the frequencies t _{total is} added up in each ring (second and third) from two intervals t _total = t _per + t _st (see time diagrams in figa, b). The second and third rings work together constantly and switch from MK to the same frequency not simultaneously, but with a time shift equal to 0.5 t _total (see timing diagrams of operation in figa, b). After the switching unit BK 25, only the second half of the total operating time of each UG at a given frequency is passed to the DSC output cut off that section t _total where there is t _lane and part t of _Art . In other words, only the high-frequency signal (HF) from the output of UG 11 or UG 24 passes to the output of the BC 25, where the stationary synchronism mode has already been fully established. As a result, at the output of BC 25, a time interval of operation at a given frequency is set equal to the sum of two second halves t _total from each UG, i.e. there is a “stitching” of two time periods of each UG operation at 0.5 t _total , in which there are no transients (see time diagrams

works on figv). The output frequencies of the second UG 11 and the third UG 24 are coherent and therefore they do not have beats between themselves. This is facilitated by a synchronous reset and simultaneous initialization of the dividers DFKD 7 and DFKD 14 at the beginning of operation by a signal from MK 23. Thus, the operating time at a given frequency at the output of BK 25 is the same as before, t _common , but in this case the total RF signal is “cleared” of transient frequency oscillations, which are in t _per . The switching time of the outputs of the second UG 11 and the third UG 24 in the switching unit of the BC 25 is usually no more than 1 microsecond and it can be ignored, since there is practically no loss of information in the radio communication system.

Both outputs of the CSC together work continuously with a shift in t _total both in the PfP mode and in the PFM mode. For this, in the second UG 11 and in the third UG 24 there are modulating inputs, to which in the Tx mode a modulating signal is supplied from the IC 10 through the second UA 21 and the fourth KL key 22. Here, as in the prototype device, in general, a two-point FM, when frequency modulation occurs simultaneously in the first and second and third rings. In the particular case, depending on the given technical requirements, only a single-point FM can be used at the modulating input of the first UG 5 in the first IFAPC ring.

The modulating signal in the FM mode from the output of the IC 10 through the first UA 13 and the third key KL 20 is fed to the modulating input of the first UG 5, from the output of which the FM reference signal is fed to the input of the second and third rings. The control input of the first UA 13 comes from the microcontroller MK 23 via the first control bus the corresponding control signal, through which its transmission coefficient changes when the output frequency of the second ring changes. This automatically stabilizes the specified level of deviation of the frequency of the synthesizer in a wide range of switched frequencies at a certain constant level of the modulating signal from the IC 10.

The first control bus from the MK 23 is a standard three-wire interface, where three wires go to

serial binary code pulse signals: 1) clock pulses; 2) information signal; 3) a pulse of permission to record the transmitted information in one of the synthesizer blocks.

On the first control bus from MK 23, control signals in serial binary code are also fed to the first DPKD 6, the second DPKD 12, the second CFD 8, the second DPKD 7, the third DPKD 14, the third CFD 15 and the third DPKD 19 for their inclusion in the operating state on set frequency and mode. According to the control signals from MK 23, the operating mode of the second ChFD 8 and the third ChFD 15 in current changes: in the transition mode, the current from the output of the ChFD 8 and ChFD 15 is large, which means that the passband of the IFAPH rings and the speed is large, in the synchronism mode the current of these ChFD is small and the bandwidth of the rings is reduced to the value necessary to ensure the required suppression of side components in the spectrum of the output signal of the CSC.

The feasibility of the proposed device is determined by the fact that the input units are typical and can be performed on widely known microcircuits. The digital part of the synthesizers is performed on DSC chips with IFAPCH of different companies. Moreover, in one chip there can be one or two independent DSCs with integer DPKD (Integer-N) or with fractional (Fractional-N). For example, National Semiconductor's LMX2364, LMX 2470 microcircuits are a dual synthesizer with two separate control loops: one with a fractional DPKD (DDPKD), the other with a conventional one. Similarly, the ADF4252 chip from Analog Devices and others. The controlled attenuator circuit is based on a series-connected digital potentiometer on an AD8402AR10 chip and an AD822AR operational amplifier from Analog Devices. The switching unit is built on the basis of switched buffer amplifiers made according to the amplifier circuit with a common emitter on transistors such as Philips BFR93A with transistor switches in the emitter circuit. Key devices can be performed on a chip MC14053B from Motorolla.

Thus, in the proposed DSS with FM it is possible to significantly increase the speed when switching from one frequency to another when using not only fractional DPKD, but also integer ones. At the same time, you can get a uniform frequency response in a wide band of modulating frequencies with minimal distortion.

Claims (1)

A frequency-modulated digital frequency synthesizer comprising a reference oscillator connected in series, a first frequency divider with a fixed division ratio, a first frequency-phase detector, a first low-pass filter, a first controlled oscillator, a first frequency divider with a variable division ratio, the output of which is connected to the second input the first frequency-phase detector; a second frequency divider with a fixed division coefficient, a second frequency-phase detector and a second low-pass filter connected in series; a third frequency divider with a fixed division coefficient, a third frequency-phase detector and a third low-pass filter connected in series; the second controlled oscillator and the second frequency divider with a variable division coefficient, the output of which is connected to the second input of the second frequency-phase detector in series; a modulated signal source, a first controlled attenuator, and a third key connected in series with the modulating input of the first controlled generator, the output of the first controlled generator connected to the signal inputs of the second and third frequency dividers with a fixed division coefficient; a second controlled attenuator and a fourth key connected in series with the modulating input of the second controlled generator, the input of the second controlled attenuator connected to the output of the modulating signal source, and a third frequency divider with a variable division coefficient, the output of which is connected to the second input of the third frequency a phase detector, and a microcontroller, the first control bus of which is connected to the control inputs of the first, second and third frequency divider with the division coefficient of the second and third frequency-phase detectors, the second and third frequency divider with a fixed division coefficient, the first and second controlled attenuator, and the second control bus of the microcontroller is connected to the control inputs of the third and fourth keys and the second control input of the second controlled generator the fact that a third controlled generator and a switching unit are introduced in series with it, the second input of which is connected to the output of the second controlled g nerator, and the control input of the switching unit is connected to the second control bus of the microcontroller, while the first control input of the second controlled generator is connected to the output of the second low-pass filter, the first control input of the third controlled generator is connected to the output of the third low-pass filter, the output of the third controlled generator is connected to the input of the third frequency divider with a variable division ratio, the second control input of the third controlled generator is connected to the second control circuit microcontroller, the modulating input of the third controlled generator is connected to the output of the fourth key and to the modulating input of the second controlled generator, and the output of the switching unit is the output of the device.