CN204795028U - Super broadband emission of digital tunable frequency pulse radio of CMOS machine - Google Patents
Super broadband emission of digital tunable frequency pulse radio of CMOS machine Download PDFInfo
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- CN204795028U CN204795028U CN201520477574.8U CN201520477574U CN204795028U CN 204795028 U CN204795028 U CN 204795028U CN 201520477574 U CN201520477574 U CN 201520477574U CN 204795028 U CN204795028 U CN 204795028U
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Abstract
The utility model discloses a super broadband emission of digital tunable frequency pulse radio of CMOS machine comprises OOK modulated circuit, time delay network, pulse train production network and antenna, OOK modulated circuit will input data signal DATA and clock signal CLK handles, produces the data signal who satisfies the OOK modulation and require, the time delay network adopts phase inverter delayed characteristics, utilizes input and output signal's time delay interval conduct to carry on the incoming signal that pulse train produced the network, in this time delay interval time section, and the pulse unit of time width such as formation, the single pulse signal of each grade that pulse train produced the network produces the circuit and produces a single pulse signal, and all single pulse signal produce pulse signal that circuit produced and make up into a pulse train, should whole pulse train as output signal output send via the antenna. The utility model discloses a pulse frequency is adjustable and the work bandwidth satisfies the requirement of UWB agreement.
Description
Technical field
The utility model relates to impulse radio ultra-wideband technical field, is specifically related to a kind of CMOS digital frequency-adjustable impulse radio ultra-wideband transmitter.
Background technology
Since 2002 FCC (FederalCommunicationsCommission, FCC) promulgate the spectrum criterion of ultra broadband (Ultra-Wideband, UWB), and by 3.1GHz～10。6GHz frequency range as civilian ultra-wideband devices exempt from authorized since frequency range, the features such as Ultra-wideband Communication Technology is simple with its system configuration, transmission rate is high, low in energy consumption receive application study and the concern in the fields such as Wireless Personal Network, wireless sensor network, biomedicine.
Current ultra-wideband communication system can be divided three classes: direct sequence spread spectrum (DS-SS), multi-band orthogonal frequency division multiplexing (MB-OFDM), impulse radio (IR).Wherein IR-UWB technology mainly utilizes a series of ultra-narrow pulse to carry out transfer of data as the carrier of information, without the need to any carrier signal, and narrow pulse signal can directly or be gone out by antenna transmission after buffer, therefore for other two kinds of modes, its system and circuit structure are more simple, power consumption and cost lower.Current existing many documents are studied IR-UWB transmitter, these UWB mainly adopt following scheme to realize: scheme one first adopts digital delay circuit to obtain a burst pulse, burst pulse is after shaping network, frequency spectrum is shifted to required frequency range, and it is larger that this scheme needs to use a large amount of electric capacity, inductance and resistance device, therefore chip area and cost; First scheme first utilizes the delay of digital circuit to produce several burst pulses, again these burst pulses are synthesized the impulse waveform that a frequency spectrum meets the demands, this scheme is very strict to the requirement of Waveform composition part, and time of pulse combination, slightly the waveform that then obtains of deviation will distortion completely; In addition a kind of scheme is also had to be utilize the step recovery characteristics of avalanche diode to obtain required narrow pulse signal, the technique of the avalanche diode device that this scheme adopts because of it and the CMOS technology of standard incompatible, so be not suitable for very much carrying out CMOS integrated chip.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of CMOS digital frequency-adjustable impulse radio ultra-wideband transmitter, and its pulse frequency is adjustable and bandwidth of operation meets UWB protocol requirement.
For solving the problem, the utility model is achieved through the following technical solutions:
CMOS digital frequency-adjustable impulse radio ultra-wideband transmitter, by OOK modulation circuit, time delay network, pulse train produces network and antenna forms; Wherein
Supplied with digital signal DATA and clock signal clk process by OOK modulation circuit, produce the digital signal meeting OOK modulation and require;
Time delay network adopts the feature of inverter time delay, utilizes the time delay interval of constrained input signal to produce the input signal of network as follow-up pulse train, within this time delay interval time period, generates the pulse unit of equal time width;
Every one-level single pulse signal generation circuit that pulse train produces network produces a single pulse signal, and the pulse signal that all single pulse signals produce circuit generation is combined into a pulse train, and this whole pulse sequence exports as output signal and sends via antenna.
Described CMOS digital frequency-adjustable impulse radio ultra-wideband transmitter, also comprises the integer circuit be serially connected between OOK modulation circuit and time delay network further.
In such scheme, described integer circuit is in series by 2 inverter INV1 and INV2, and the input of inverter INV1 is connected with the output of OOK modulation circuit, and the output of inverter INV2 is connected with the input of time delay network.
In such scheme, OOK modulation circuit is by nmos pass transistor NM0, NM1, and a PMOS transistor PM0 and inverter INV0 circuit forms; After the drain electrode of nmos pass transistor NM0 is connected with the source electrode of PMOS transistor PM0, form the input of the digital signal CLK of OOK modulation circuit; After the grid of nmos pass transistor NM0 is connected with the input of inverter INV0, form the input of the clock signal DATA of OOK modulation circuit; The output of inverter INV0, the grid of PMOS transistor PM0 are connected with the grid of nmos pass transistor NM1; The source electrode of nmos pass transistor NM1 connects low level; The source electrode of nmos pass transistor NM0, the drain electrode of PMOS transistor PM0 are connected with the drain electrode of nmos pass transistor NM1, form the output of OOK modulation circuit.
In such scheme, described time delay network comprises at least stage of time delay unit, and every stage of time delay unit is in series by 2 adjustable negative circuits of time delay; Negative circuit that each time delay is adjustable is by nmos pass transistor NM2, NM3, NM4, NM5, NM6 and PMOS transistor PM1, PM2, PM3, PM4 composition; The grid of nmos pass transistor NM2 forms the input of the adjustable voltage Vctrl of the adjustable negative circuit of time delay; The drain electrode of the drain electrode of nmos pass transistor NM2, the grid of nmos pass transistor NM3, nmos pass transistor NM3, the drain electrode of PMOS transistor PM1, the grid of PMOS transistor PM1, the grid of PMOS transistor PM2 are connected with the grid of PMOS transistor PM3; The grid of the drain electrode of PMOS transistor PM2, the drain electrode of nmos pass transistor NM4, nmos pass transistor NM4 is connected with the grid of nmos pass transistor NM6; The source electrode of PMOS transistor PM1, the source electrode of PMOS transistor PM2 are connected high level with the source electrode of PMOS transistor PM3 simultaneously; The source electrode of the source electrode of nmos pass transistor NM2, the source electrode of nmos pass transistor NM3, nmos pass transistor NM4 is connected low level with the source electrode of nmos pass transistor N6 simultaneously; The drain electrode of PMOS transistor PM3 connects the source electrode of PMOS transistor PM4; The drain electrode of nmos pass transistor NM6 connects the source electrode of nmos pass transistor NM5; After the grid of PMOS transistor PM4 is connected with the grid of nmos pass transistor NM5, form the input of the adjustable negative circuit of time delay; After the drain electrode of PMOS transistor PM4 is connected with the drain electrode of nmos pass transistor NM5, form the output of the adjustable negative circuit of time delay.
In such scheme, regulate the anti-phase delay time of inverter by the breadth length ratio of transistor PM3, PM4, NM5, NM6 in every grade of time delay generative circuit.
In such scheme, described time delay network comprises three grades of delay units, is namely in series by 6 adjustable negative circuits of time delay.
In such scheme, described pulse train produces network and comprises at least one grade of single pulse signal generation circuit, corresponding stage of time delay unit i.e. 2 the adjustable negative circuits of time delay of every one-level pulse generative circuit; Wherein every one-level single pulse signal produces circuit by PMOS transistor PM5, PM6 and nmos pass transistor NM7, NM8 composition; The grid of PMOS transistor PM6 forms the input that single pulse signal at the corresponding levels produces the time delayed signal A of circuit, and the input of this time delayed signal A connects the input of the adjustable negative circuit INV-C1 of the first time delay of corresponding delay unit; The source electrode of PMOS transistor PM6 is connected with the grid of PMOS transistor PM5; The source electrode of PMOS transistor PM5 connects high level; After the grid of PMOS transistor PM5 is connected with the grid of nmos pass transistor NM7, form the input that single pulse signal at the corresponding levels produces the time delayed signal B of circuit, the input of this time delayed signal A connects the output of the adjustable negative circuit INV-C1 of the first time delay and the input of the adjustable negative circuit INV-C2 of the second time delay of corresponding delay unit; The source electrode of nmos pass transistor NM7 is connected with the grid of nmos pass transistor NM8; The source electrode of nmos pass transistor NM8 connects low level; The grid of nmos pass transistor NM8 forms the input that single pulse signal at the corresponding levels produces the time delayed signal C of circuit, and the input of this time delayed signal C connects the output of the adjustable negative circuit INV-C2 of the first time delay of corresponding delay unit; After the grid of PMOS transistor PM6 is connected with the grid of nmos pass transistor NM7, form the output that single pulse signal at the corresponding levels produces circuit output signal OUT; The output of three grades of single pulse signal generation circuit is connected, and the common output forming whole pulse train generation network.
In such scheme, by the amplitude regulating the breadth length ratio of transistor PM5, PM6, NM7, NM8 in every grade of pulse generative circuit to regulate formed single pulse signal.
In such scheme, described pulse train produces network and comprises three grades of single pulse signals generation circuit.
Compared with prior art, it is simple that the utility model has structure, and low in energy consumption, area is little easily integrated, and has the adjustable function of pulse frequency range, increases the utilance of the overall frequency range of UWB.
Accompanying drawing explanation
Fig. 1 is the system construction drawing of CMOS digital frequency-adjustable impulse radio ultra-wideband transmitter.
Fig. 2 is the structure chart of the adjustable rp unit INV_C of time delay of the present utility model.
Fig. 3 is the structure chart of pulse generative circuit of the present utility model.
Fig. 4 is the structure chart of inverter of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described further:
CMOS digital frequency-adjustable impulse radio ultra-wideband transmitter, as shown in Figure 1, produces network, inverter and antenna composition primarily of OOK (binary system on off keying) modulation circuit, integer circuit, time delay network, pulse train.
The major function of OOK modulation circuit is processed supplied with digital signal DATA and clock signal clk, produces the digital signal meeting OOK modulation and require.That is, when digital signal DATA is high level " 1 ", output signal Y is clock signal clk, and when digital signal DATA is low level " 0 ", output signal Y is " 0 ".
OOK modulation circuit is by nmos pass transistor NM0, NM1, and a PMOS transistor PM0 and inverter INV0 circuit forms.After the drain electrode of nmos pass transistor NM0 is connected with the source electrode of PMOS transistor PM0, form the input of the digital signal CLK of OOK modulation circuit.After the grid of nmos pass transistor NM0 is connected with the input of inverter INV0, form the input of the clock signal DATA of OOK modulation circuit.The output of inverter INV0, the grid of PMOS transistor PM0 are connected with the grid of nmos pass transistor NM1.The source electrode of nmos pass transistor NM1 connects low level.The source electrode of nmos pass transistor NM0, the drain electrode of PMOS transistor PM0 are connected with the drain electrode of nmos pass transistor NM1, form the output of OOK modulation circuit.See Fig. 1.
As shown in Figure 4, each inverter forms by PMOS transistor PM7 and nmos pass transistor NM9 the structure of inverter.After wherein the grid of PMOS transistor PM7 is connected with the grid of nmos pass transistor NM9, form the input of inverter.The source electrode of PMOS transistor PM7 connects high level, and the source electrode of nmos pass transistor NM9 connects low level.After the drain electrode of PMOS transistor PM7 is connected with the drain electrode of nmos pass transistor NM9, form the output of inverter.
The course of work of OOK modulation circuit is: when DATA is high level " 1 ", nmos pass transistor NM0 and PMOS transistor PM0 is in conducting state, and nmos pass transistor NM1 is in not on-state, so the circuit network that clock signal clk can be composed in parallel by NM0 and PM0, output signal Y equals CLK signal.When DATA is high level " 0 ", nmos pass transistor NM0 and PMOS transistor PM0 is in cut-off state, and nmos pass transistor NM1 is in conducting state, so output signal Y equals " 0 ".So when data digital signal is " 1 ", have signal to export, when data digital signal is " 0 ", no signal exports, and meets the requirement of OOK modulating mode.
The output signal Y of OOK modulation circuit is connected by two-stage inverter INV1 and INV2 after the integer circuit that forms, is re-used as the input signal of time delay network.See Fig. 1.
The major function of time delay network is the feature adopting inverter time delay, utilizes the time delay interval of constrained input signal to produce the input signal of network as follow-up pulse train, within this time delay interval time period, generates the pulse unit of equal time width.
Above-mentioned time delay network comprises three grades of delay units, and every stage of time delay unit is in series by 2 adjustable negative circuits of time delay.Negative circuit that each time delay is adjustable is by nmos pass transistor NM2, NM3, NM4, NM5, NM6 and PMOS transistor PM1, PM2, PM3, PM4 composition.The grid of nmos pass transistor NM2 forms the input of the adjustable voltage Vctrl of the adjustable negative circuit of time delay.The drain electrode of the drain electrode of nmos pass transistor NM2, the grid of nmos pass transistor NM3, nmos pass transistor NM3, the drain electrode of PMOS transistor PM1, the grid of PMOS transistor PM1, the grid of PMOS transistor PM2 are connected with the grid of PMOS transistor PM3.The grid of the drain electrode of PMOS transistor PM2, the drain electrode of nmos pass transistor NM4, nmos pass transistor NM4 is connected with the grid of nmos pass transistor NM6.The source electrode of PMOS transistor PM1, the source electrode of PMOS transistor PM2 are connected high level with the source electrode of PMOS transistor PM3 simultaneously.The source electrode of the source electrode of nmos pass transistor NM2, the source electrode of nmos pass transistor NM3, nmos pass transistor NM4 is connected low level with the source electrode of nmos pass transistor N6 simultaneously.The drain electrode of PMOS transistor PM3 connects the source electrode of PMOS transistor PM4.The drain electrode of nmos pass transistor NM6 connects the source electrode of nmos pass transistor NM5.After the grid of PMOS transistor PM4 is connected with the grid of nmos pass transistor NM5, form the input of the adjustable negative circuit of time delay.After the drain electrode of PMOS transistor PM4 is connected with the drain electrode of nmos pass transistor NM5, form the output of the adjustable negative circuit of time delay.See Fig. 2.
The course of work of negative circuit that time delay is adjustable is: when regulating adjustable voltage Vctrl, the electric current flowing through PMOS transistor PM1 can be changed, and because the effect of current mirror, also the electric current flowed through in PMOS transistor PM3 and nmos pass transistor NM6 is changed accordingly, thus change the drain-source current of the inverter be made up of PMOS transistor PM4 and nmos pass transistor NM5, change the delay time of inverter.The main feature of this structure with the addition of nmos pass transistor NM3, nmos pass transistor NM3 can be equivalent to the resistance being connected in parallel on nmos pass transistor NM2 two ends.By changing breadth length ratio, nmos pass transistor NM3 is made to be equivalent to a very large resistance, thus linearity when reducing the change of nmos pass transistor NM2 grid voltage and cause electric current to change, make the linearity smoothly, make voltage tuning scope broaden simultaneously.In the utility model, regulate the anti-phase delay time of inverter by the breadth length ratio of transistor PM3, PM4, NM5, NM6 in every grade of time delay generative circuit.
Pulse train produces network and comprises three grades of single pulse signals generation circuit, and every one-level single pulse signal produces circuit and produces a single pulse signal, and tertiary vein rushes signal combination and becomes a pulse train as output signal.Regulated the amplitude of formed single pulse signal by the breadth length ratio regulating every grade of single pulse signal to produce transistor in circuit, three grades of single pulse signals are combined into one and have the pseudo-Gaussian pulse signal of good spectral characteristic.Corresponding stage of time delay unit i.e. 2 the adjustable negative circuits of time delay of every one-level pulse generative circuit.
Every one-level single pulse signal produces circuit by PMOS transistor PM5, PM6 and nmos pass transistor NM7, NM8 composition.The grid of PMOS transistor PM6 forms the input that single pulse signal at the corresponding levels produces the time delayed signal A of circuit, and the input of this time delayed signal A connects the input of the adjustable negative circuit INV-C1 of the first time delay of corresponding delay unit.The source electrode of PMOS transistor PM6 is connected with the grid of PMOS transistor PM5.The source electrode of PMOS transistor PM5 connects high level.After the grid of PMOS transistor PM5 is connected with the grid of nmos pass transistor NM7, form the input that single pulse signal at the corresponding levels produces the time delayed signal B of circuit, the input of this time delayed signal A connects the output of the adjustable negative circuit INV-C1 of the first time delay and the input of the adjustable negative circuit INV-C2 of the second time delay of corresponding delay unit.The source electrode of nmos pass transistor NM7 is connected with the grid of nmos pass transistor NM8.The source electrode of nmos pass transistor NM8 connects low level.The grid of nmos pass transistor NM8 forms the input that single pulse signal at the corresponding levels produces the time delayed signal C of circuit, and the input of this time delayed signal C connects the output of the adjustable negative circuit INV-C2 of the first time delay of corresponding delay unit.After the grid of PMOS transistor PM6 is connected with the grid of nmos pass transistor NM7, form the output that single pulse signal at the corresponding levels produces circuit output signal OUT.The output of three grades of single pulse signal generation circuit is connected, and the common output forming whole pulse train generation network.See Fig. 3.
The course of work that pulse train produces network is: in pulse generative circuit, initial condition is A=" 1 ", B=" 0 ", C=" 1 ".Nmos pass transistor NM8 and PMOS transistor PM5 conducting, nmos pass transistor NM7 and PMOS transistor PM6 cut-off, output signal OUT is constant voltage values.When A point signal becomes low level " 0 " from high level " 1 ", and because the reason of anti-phase time delay, now B point signal is still low level " 0 ", when A=B=" 0 ", PMOS transistor PM5 and PM6 all conductings, and nmos pass transistor NM7 is still in cut-off state, so output signal OUT is communicated to high-level DC voltage signal, magnitude of voltage is driven high.After time of delay, B point signal becomes " 1 " from " 0 ", and PMOS transistor PM5 ends, and output signal voltage stops being driven high.When B point signal becomes high level " 1 ", because inverter time delay reason, C point voltage still time high level " 1 ", so nmos pass transistor NM7, NM8 all conductings.Output signal OUT is communicated to signal ground (low level " 0 "), and magnitude of voltage is dragged down.After the inverter delay time terminates, C point signal becomes low level " 0 ".Nmos pass transistor NM8 ends, and output signal voltage stops being dragged down.In the change of this one-period, output signal defines a little single pulse signal.
In the process that output signal OUT magnitude of voltage is dragged down or draws high, the amplitude of change in voltage determines by the performance of transistor.When changing the breadth length ratio of transistor, the amplitude of the pulse that can regulation output signal be formed.This pulse generate network forms circuit by three pulses, and continues all in time, and three pulses are combined to form a complete pulse train, the similar high-order Gaussian pulse of whole pulse train.This high-order Gaussian pulse has good spectral characteristic on frequency spectrum, is conducive to the transmission of signal of communication.In the utility model, by the amplitude regulating the breadth length ratio of transistor PM5, PM6, NM7, NM8 in every grade of pulse generative circuit to regulate formed single pulse signal.
The course of work of output pulse signal frequency-adjustable is: the operating center frequency f of the pulse train that system produces
c=1/t
c, wherein t
cfor the delay time that time delay adjustable network produces, i.e. the pulse duration of single pulse signal.The signal frequency range B=1/t of pulse train
b, wherein t
bfor the time domain width of pulse train.So by regulating time delay adjustable network delay time t
csize regulate the operating center frequency of transmitter output pulse signal.The pulse signal that transmitter is launched can select best working frequency range in 3-10GHz frequency range.Be conducive to effective utilization of 3-10GHz frequency range in UWB agreement.
In addition, between pulse train generation network and antenna, a buffer circuit is serially connected with.
Claims (10)
1.CMOS digital frequency-adjustable impulse radio ultra-wideband transmitter, is characterized in that: by OOK modulation circuit, time delay network, pulse train produces network and antenna forms; Wherein
Supplied with digital signal DATA and clock signal clk process by OOK modulation circuit, produce the digital signal meeting OOK modulation and require;
Time delay network adopts the feature of inverter time delay, utilizes the time delay interval of constrained input signal to produce the input signal of network as follow-up pulse train, within this time delay interval time period, generates the pulse unit of equal time width;
Every one-level single pulse signal generation circuit that pulse train produces network produces a single pulse signal, and the pulse signal that all single pulse signals produce circuit generation is combined into a pulse train, and this pulse train exports as output signal and sends via antenna.
2. CMOS according to claim 1 digital frequency-adjustable impulse radio ultra-wideband transmitter, is characterized in that: also comprise the integer circuit be serially connected between OOK modulation circuit and time delay network further.
3. CMOS according to claim 2 digital frequency-adjustable impulse radio ultra-wideband transmitter, it is characterized in that: described integer circuit is in series by 2 inverter INV1 and INV2, the input of inverter INV1 is connected with the output of OOK modulation circuit, and the output of inverter INV2 is connected with the input of time delay network.
4., according to the digital frequency-adjustable impulse radio ultra-wideband of the CMOS in claims 1 to 3 described in any one transmitter, it is characterized in that:
OOK modulation circuit is by nmos pass transistor NM0, NM1, and a PMOS transistor PM0 and inverter INV0 circuit forms; After the drain electrode of nmos pass transistor NM0 is connected with the source electrode of PMOS transistor PM0, form the input of the digital signal CLK of OOK modulation circuit; After the grid of nmos pass transistor NM0 is connected with the input of inverter INV0, form the input of the clock signal DATA of OOK modulation circuit; The output of inverter INV0, the grid of PMOS transistor PM0 are connected with the grid of nmos pass transistor NM1; The source electrode of nmos pass transistor NM1 connects low level; The source electrode of nmos pass transistor NM0, the drain electrode of PMOS transistor PM0 are connected with the drain electrode of nmos pass transistor NM1, form the output of OOK modulation circuit.
5. CMOS according to claim 4 digital frequency-adjustable impulse radio ultra-wideband transmitter, is characterized in that: described time delay network comprises at least stage of time delay unit, and every stage of time delay unit is in series by 2 adjustable negative circuits of time delay; Negative circuit that each time delay is adjustable is by nmos pass transistor NM2, NM3, NM4, NM5, NM6 and PMOS transistor PM1, PM2, PM3, PM4 composition; The grid of nmos pass transistor NM2 forms the input of the adjustable voltage Vctrl of the adjustable negative circuit of time delay; The drain electrode of the drain electrode of nmos pass transistor NM2, the grid of nmos pass transistor NM3, nmos pass transistor NM3, the drain electrode of PMOS transistor PM1, the grid of PMOS transistor PM1, the grid of PMOS transistor PM2 are connected with the grid of PMOS transistor PM3; The grid of the drain electrode of PMOS transistor PM2, the drain electrode of nmos pass transistor NM4, nmos pass transistor NM4 is connected with the grid of nmos pass transistor NM6; The source electrode of PMOS transistor PM1, the source electrode of PMOS transistor PM2 are connected high level with the source electrode of PMOS transistor PM3 simultaneously; The source electrode of the source electrode of nmos pass transistor NM2, the source electrode of nmos pass transistor NM3, nmos pass transistor NM4 is connected low level with the source electrode of nmos pass transistor N6 simultaneously; The drain electrode of PMOS transistor PM3 connects the source electrode of PMOS transistor PM4; The drain electrode of nmos pass transistor NM6 connects the source electrode of nmos pass transistor NM5; After the grid of PMOS transistor PM4 is connected with the grid of nmos pass transistor NM5, form the input of the adjustable negative circuit of time delay; After the drain electrode of PMOS transistor PM4 is connected with the drain electrode of nmos pass transistor NM5, form the output of the adjustable negative circuit of time delay.
6. CMOS according to claim 5 digital frequency-adjustable impulse radio ultra-wideband transmitter, is characterized in that: regulate the anti-phase delay time of inverter by the breadth length ratio of transistor PM3, PM4, NM5, NM6 in every grade of time delay generative circuit.
7. CMOS according to claim 5 digital frequency-adjustable impulse radio ultra-wideband transmitter, is characterized in that: described time delay network comprises three grades of delay units, is namely in series by 6 adjustable negative circuits of time delay.
8. CMOS according to claim 5 digital frequency-adjustable impulse radio ultra-wideband transmitter, it is characterized in that: described pulse train produces network and comprises at least one grade of single pulse signal generation circuit, corresponding stage of time delay unit i.e. 2 the adjustable negative circuits of time delay of every one-level pulse generative circuit; Wherein every one-level single pulse signal produces circuit by PMOS transistor PM5, PM6 and nmos pass transistor NM7, NM8 composition; The grid of PMOS transistor PM6 forms the input that single pulse signal at the corresponding levels produces the time delayed signal A of circuit, and the input of this time delayed signal A connects the input of the adjustable negative circuit INV-C1 of the first time delay of corresponding delay unit; The source electrode of PMOS transistor PM6 is connected with the grid of PMOS transistor PM5; The source electrode of PMOS transistor PM5 connects high level; After the grid of PMOS transistor PM5 is connected with the grid of nmos pass transistor NM7, form the input that single pulse signal at the corresponding levels produces the time delayed signal B of circuit, the input of this time delayed signal A connects the output of the adjustable negative circuit INV-C1 of the first time delay and the input of the adjustable negative circuit INV-C2 of the second time delay of corresponding delay unit; The source electrode of nmos pass transistor NM7 is connected with the grid of nmos pass transistor NM8; The source electrode of nmos pass transistor NM8 connects low level; The grid of nmos pass transistor NM8 forms the input that single pulse signal at the corresponding levels produces the time delayed signal C of circuit, and the input of this time delayed signal C connects the output of the adjustable negative circuit INV-C2 of the first time delay of corresponding delay unit; After the grid of PMOS transistor PM6 is connected with the grid of nmos pass transistor NM7, form the output that single pulse signal at the corresponding levels produces circuit output signal OUT; The output of three grades of single pulse signal generation circuit is connected, and the common output forming whole pulse train generation network.
9. CMOS according to claim 8 digital frequency-adjustable impulse radio ultra-wideband transmitter, is characterized in that: by the amplitude regulating the breadth length ratio of transistor PM5, PM6, NM7, NM8 in every grade of pulse generative circuit to regulate formed single pulse signal.
10. CMOS according to claim 8 digital frequency-adjustable impulse radio ultra-wideband transmitter, is characterized in that: described pulse train produces network and comprises three grades of single pulse signals generation circuit.
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