CN202167988U - Charge pump circuit for phase-locked loop - Google Patents

Charge pump circuit for phase-locked loop Download PDF

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Publication number
CN202167988U
CN202167988U CN 201120194658 CN201120194658U CN202167988U CN 202167988 U CN202167988 U CN 202167988U CN 201120194658 CN201120194658 CN 201120194658 CN 201120194658 U CN201120194658 U CN 201120194658U CN 202167988 U CN202167988 U CN 202167988U
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China
Prior art keywords
pipe
nmos pipe
grid
phase
pmos
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Chinese (zh)
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梁仁光
胡胜发
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Anyka Guangzhou Microelectronics Technology Co Ltd
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Anyka Guangzhou Microelectronics Technology Co Ltd
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Abstract

The utility model discloses a charge pump circuit for a phase-locked loop, which comprises a group of complementary switching circuits, a pull-up constant-current source and a pull-down constant-current source, wherein, the complementary switching circuits are connected to a pull-up signal output port and a pull-down signal output port of a phase-locked loop PFD (Phase-Frequency Detector); and the pull-up constant-current source is connected with the first node of the complementary switching circuits, and the pull-down constant-current source is connected to the third node of the complementary switching circuits so as to provide mirror image charge-discharge current for the phase loop filter of the phase-locked loop The charge pump circuit reduces the non-ideal factors of the charge pump and the burrs of the phase-locked loop so as to greatly improve the performance of the phase-locked loop.

Description

A kind of charge pump circuit that is used for phase-locked loop
Technical field
The utility model relates to phase-locked loop circuit, relates in particular to a kind of charge pump circuit that is used for phase-locked loop.
Background technology
Phase-locked loop (PLL) is an important module in simulation and the Digital Analog Hybrid Circuits, mainly is made up of parts such as phase frequency detector (PFD), loop filter (LPF) and voltage controlled oscillators (VCO).When being in the lock state; Has only a fixing stable state phase difference between the input signal of VCO output signal and loop filter; And do not have frequency difference to exist, and in the pull-in range scope, change or during phase change, VCO exports the frequency and the phase place of signal trace input signal when frequency input signal.In various phase-locked loop structures; Charge pump phase lock loop (CPPLL) has that stability is high, catching range big, phase frequency detector (PFD) adopts digital circuit and is convenient to integrated characteristics, is widely used among radio communication, frequency synthesizer and the clock restore circuit.Charge pump (charge pump; CP) be a very important modular circuit in the phase-locked loop; Performance decisive role to whole phase-locked loop; But the conventional charge pump exists current source mismatch, electric charge imperfect problem such as to share inevitably, and this can be directly transferred on the control voltage of voltage-controlled oscillator, therefore can produce extremely important influence to the burr of phase-locked loop, the main performance index such as shake of output clock.
Shown in Fig. 1 frame of broken lines is got up; Charge pump in the phase-locked loop is made up of two constant-current sources that discharge and recharge; It is through phase frequency detector (PFD; Input signal is Fref, Ffb) two output signals UP and DN control constant-current source loop filter (LPF) discharged and recharged, thereby realize the purpose of this control voltage to the voltage controlled oscillator regulating frequency.In the side circuit design, charge pump exists some nonideal factors: owing to the low output impedance of Effect of Short-channel MOSFET, the charging or discharging current mismatch can change with output voltage (1); (2) the clock feedthrough mismatch of switch and electric charge inject mismatch has increased the ripple of phase error with control voltage; (3) the shared effect of electric charge has further caused the ripple voltage on the loop filter capacitance, thereby causes burr; (4) in addition, also has the leakage of electric current.Therefore, when the design charge pump, need find feasible way to come to improve these non-ideal factors as far as possible.
Fig. 2 is that a kind of common charge pump is realized circuit; Wherein Mp1, Mp2, Mp3 represent the PMOS pipe, and Mn1, Mn2, Mn3 represent the NMOS pipe, and UP, DN represent the output signal from phase frequency detector; Ich, Idisch represent to discharge and recharge constant-current source, and UP and DN represent PDF output signal.When UP is 0, DN is 0 o'clock, and image current is through the electric capacity charging of Mp3 to LPF; When UP is 1, DN is 1 o'clock, and electric capacity is through the Mn3 discharge; When UP is 1, DN is 0 o'clock, and the voltage on the electric capacity remains unchanged.This charge pump circuit is simple; Be convenient to realize; But some shortcomings are arranged: at first be to guarantee that charging current and discharging current can equate by clock when output voltage changes, will make control voltage of voltage-controlled oscillator produce ripple like this, cause the generation of output frequency burr.In addition, the switch that UP and DN controlled is respectively PMOS and NMOS, their conducting and different by speed, and they conducting and by the time electric charge that brings share and all can cause burr.
Non-ideal factors such as charging or discharging current does not match because existing charge pump circuit exists, not the matching of switching sequence, electric charge is shared bring very big burr to phase-locked loop, so that have greatly influenced the performance of phase-locked loop systems.Thereby, be necessary to design a high performance charge pump circuit, to reach the requirement of phase-locked loop systems high performance index.
The utility model content
Be directed to this, the utility model purpose is to propose a kind of charge pump circuit that is used for phase-locked loop that improves performance and realizes circuit, but the minimizing non-ideal factor of maximum possible, the burr of reduction phase-locked loop.
For solving above technical problem, the technical scheme that the utility model provides is: a kind of charge pump circuit that is used for phase-locked loop comprises and draws a constant-current source and a drop-down constant-current source on one group of complementary switch circuit; Said complementary switch circuit be connected to the phase-locked loop phase frequency detector on draw signal output port and pulldown signal output port; Draw constant-current source to be connected to the first node of complementary switch circuit on said, said drop-down constant-current source is connected to the 3rd node of said complementary switch circuit, so that the mirror image charging and discharging currents of phase-locked loop mirror loop filter to be provided.
More excellent ground comprises a unit gain amplifying circuit, and the input of said unit gain amplifying circuit connects the Section Point of said complementary switch circuit, and the output of said unit gain amplifying circuit connects the 4th node of said complementary switch circuit.
More excellent ground, it is a complementary MOS switching circuit that said complementary switch closes circuit.
More excellent ground; Said complementary MOS switching circuit comprises PMOS pipe, NMOS pipe; The 2nd PMOS pipe, the 2nd NMOS pipe, the 3rd PMOS pipe, the 3rd NMOS pipe, the 4th PMOS pipe, the 4th NMOS pipe; Wherein: the drain electrode of the drain electrode of the source electrode of said PMOS pipe, NMOS pipe, the source electrode of the 2nd PMOS pipe and the 2nd NMOS pipe connects jointly, forms the first node of said complementary MOS switching circuit; The drain electrode of the source electrode of the source electrode of the drain electrode of said PMOS pipe, NMOS pipe, the 3rd PMOS pipe, the 3rd NMOS pipe connects jointly, forms the Section Point of said complementary MOS switching circuit; The source electrode of the drain electrode of the source electrode of the drain electrode of said the 3rd PMOS pipe, the 3rd NMOS pipe, the 4th PMOS pipe, the 4th NMOS pipe connects jointly, forms the 3rd node of said complementary MOS switching circuit; The source electrode of the drain electrode of the drain electrode of the source electrode of said the 4th PMOS pipe, the 4th NMOS pipe, the 2nd PMOS pipe, the 2nd NMOS pipe connects jointly, forms the 4th node of said complementary MOS switching circuit; The grid of the grid of the grid of the grid of said PMOS pipe, NMOS pipe, the 2nd PMOS pipe and the 2nd NMOS pipe be connected to the phase-locked loop phase frequency detector on draw signal positive output end mouth; The grid of the grid of the grid of the grid of said the 3rd PMOS pipe, the 3rd NMOS pipe, the 4th PMOS pipe and the 4th NMOS pipe is connected to the pulldown signal output port of phase-locked loop phase frequency detector.
More excellent ground, the grid of the grid of said PMOS pipe and said the 2nd NMOS pipe be connected to the phase-locked loop phase frequency detector on draw signal negative output port; The grid of the grid of said the 2nd PMOS pipe and said NMOS pipe be connected to the phase-locked loop phase frequency detector on draw signal positive output end mouth; The grid of the grid of said the 3rd PMOS pipe and said the 4th NMOS pipe is connected to the pulldown signal negative output port of phase-locked loop phase frequency detector; The grid of the grid of said the 4th PMOS pipe and said the 3rd NMOS pipe is connected to the pulldown signal positive output end mouth of phase-locked loop phase frequency detector.
More excellent ground, drawing constant-current source on said is the wide amplitude of oscillation, cascade utmost point PMOS constant-current source.
More excellent ground; The said wide amplitude of oscillation, cascade utmost point PMOS constant-current source comprise: the 11 PMOS pipe, the 12 PMOS pipe, the 13 PMOS pipe, the 14 PMOS pipe and the 15 PMOS pipe, and wherein: the source electrode of the source electrode of said the 11 PMOS pipe, the 12 PMOS pipe and the source electrode of the 13 PMOS pipe are connected to power supply; The source electrode of said the 14 PMOS pipe is connected to the drain electrode of said the 11 PMOS pipe; The source electrode of said the 15 PMOS pipe is connected to the drain electrode of said the 12 PMOS pipe; The drain electrode of the grid of the grid of said the 11 PMOS pipe and said the 12 PMOS pipe and said the 14 PMOS pipe is connected to said drop-down constant-current source; The drain electrode of the grid of the grid of the grid of said the 13 PMOS pipe, the 14 PMOS pipe and the 15 PMOS pipe and said the 13 PMOS pipe is connected to ground; The drain electrode of said the 15 PMOS pipe is connected to the first node of said complementary switch circuit.
More excellent ground, said drop-down constant-current source is the wide amplitude of oscillation, cascade utmost point NMOS constant-current source.
More excellent ground; The said wide amplitude of oscillation, cascade utmost point NMOS constant-current source comprise: the 11 NMOS pipe, the 12 NMOS pipe, the 13 NMOS pipe, the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe and the 17 NMOS pipe, and wherein: the source electrode of the source electrode of the source electrode of said the 11 NMOS pipe, the 12 NMOS pipe, the source electrode of the 13 NMOS pipe and the 14 NMOS pipe is connected to ground; The source electrode of said the 15 NMOS pipe is connected to the drain electrode of said the 11 NMOS pipe; The source electrode of said the 16 NMOS pipe is connected to the drain electrode of said the 12 NMOS pipe; The source electrode of said the 17 NMOS pipe is connected to the drain electrode of said the 13 NMOS pipe; The drain electrode of the grid of the grid of the grid of said the 11 NMOS pipe, the 12 NMOS pipe and the 13 NMOS pipe and said the 15 NMOS pipe is connected to power supply; The grid of the grid of the grid of the grid of said the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe and the 17 NMOS pipe connects; The drain electrode of said the 14 NMOS pipe is connected to power supply; The drain electrode of said the 16 NMOS pipe is connected to draws constant-current source on said; The drain electrode of said the 17 NMOS pipe is connected to the 3rd node of said complementary switch circuit.
More excellent ground draws constant-current source to be connected to ground through a constant current source on said.
Compared with prior art; The charge pump circuit that the utility model is used for phase-locked loop can obviously improve phase-locked loop ground performance; It includes but are not limited to following advantage: the wide amplitude of oscillation, cascode current source structure can improve output impedance; Improve the performance of constant-current source, thereby reduce the charging or discharging current mismatch preferably; Adopt switch and a unity gain amplifier of four complementations can eliminate shared effect of electric charge and other non-ideal characteristic preferably, reduce phase error greatly.
Description of drawings
Fig. 1 is the schematic diagram of charge pump circuit;
Fig. 2 is common charge pump circuit structure;
Fig. 3 is the charge pump circuit structure that the utility model is used for phase-locked loop.
Embodiment
In order to make those skilled in the art understand the technical scheme of the utility model better, the utility model is done further to specify below in conjunction with accompanying drawing and specific embodiment.
For simplicity, following Reference numeral is all with the letter representation component type, which element of numeral.Represent PMOS pipe like Mp1, Mn4 representes the 4th NMOS pipe, and SW11 representes first switch etc., so analogizes.The following specifically describes the circuit structure and the operation principle of this circuit.
Referring to Fig. 3; Expression the utility model is used for charge pump circuit one preferred embodiment of phase-locked loop systems; Its circuit structure mainly is made up of three parts: draw constant-current source Ib1 and drop-down constant-current source Ib2 on (1) wide amplitude of oscillation, the cascade, so that the mirror image charging and discharging currents of phase-locked loop mirror loop filter LPF to be provided; The switch of (2) 4 pairs of complementations forms complementary complementary MOS switching circuit, draws constant-current source Ib1 in its first node 1 connection, and the 3rd node 3 connects drop-down constant-current source Ib2, is used for controlling the capacitor charge and discharge to loop filter LPF; The operational amplifier UGB of (3) unit gains; Its input connects the Section Point 2 of complementary switch circuit; Output connects the 4th node 4 of complementary switch circuit, help to reduce greatly node VOUT and on draw the electric charge between the output node SN of output node SP and drop-down constant-current source Ib2 of constant-current source Ib1 to share.
In the present embodiment; In order to adapt to the wide-voltage range of output voltage VO UT; And let the output signals UP of phase-locked loop phase frequency detector and the consistency of DN institute control switch; Adopt the switch SW 11~SW14 of four complementations, can reduce the effect that clock feedthrough and electric charge inject preferably, specifically adopted structure shown in Figure 3.
As shown in Figure 3, the complementary MOS switching circuit comprises the SW14 of SW13, Mp4 and Mn4 formation that SW12, Mp3 and the Mn3 of SW11, Mp2 and pipe Mn2 formation that the MOS switch of 4 pairs of complementations: Mp1 and Mn1 constitute constitute.Concrete annexation is: the source electrode of the source electrode of Mp1, the drain electrode of Mn1, Mp2 and the drain electrode of Mn2 connect jointly, form the first node 1 of complementary MOS switching circuit; The source electrode of the drain electrode of Mp1, the source electrode of Mn1, Mp3, the drain electrode of Mn3 connect jointly, form the Section Point 2 of complementary MOS switching circuit; The drain electrode of the drain electrode of Mp3, the source electrode of Mn3, Mp4, the source electrode of Mn4 connect jointly, form the 3rd node 3 of complementary MOS switching circuit; The drain electrode of the source electrode of Mp4, the drain electrode of Mn4, Mp2, the source electrode of Mn2 connect jointly, form the 4th node 4 of complementary MOS switching circuit; The grid of Mp1, Mn1, Mp2 and Mn2 be connected to phase-locked loop phase frequency detector LPF on draw signal output port; The grid of Mp3, Mn3, Mp4 and Mn4 is connected to the pulldown signal output port of phase-locked loop phase frequency detector.
Optimal way is, the output signal of phase-locked loop phase frequency detector is exported with difference form, draws signal to be divided into UP, the output of UP_b two-way on promptly, and pulldown signal is DN, the output of DN_b two-way.At this moment, the grid of Mp1 and Mn2 be connected to the phase-locked loop phase frequency detector on draw signal negative output port UP_b; The grid of Mp2 and Mn1 be connected to the phase-locked loop phase frequency detector on draw signal positive output end mouth UP; The grid of Mp3 and Mn4 is connected to the pulldown signal negative output port DN_b of phase-locked loop phase frequency detector; The grid of Mp4 and Mn4 is connected to the pulldown signal positive output end mouth DN of phase-locked loop phase frequency detector.
In order to eliminate the effect that electric charge is shared; The utility model has adopted a unit gain operational amplifier UGB; Make output voltage VO UT equal the voltage VSP of SP node and the voltage VSN of SN node, the electric charge that will greatly reduce like this between node VOUT and node SP and the SN is shared.Certainly, under practical situations, can some specific requirements be arranged to unit gain operational amplifier UGB.In order to make phase-locked loop output reference clock frequency big as much as possible; To satisfy different practical applications; The control voltage of voltage-controlled oscillator amplitude of oscillation also must be big as much as possible, so the input voltage amplitude of oscillation of the operational amplifier of unit gain and output voltage swing are that requirement is bigger; Simultaneously, its loop bandwidth also will be done bigger, meets requirement of actual application.
Drawing constant-current source in the present embodiment is the wide amplitude of oscillation, cascade utmost point PMOS constant-current source, and drop-down constant-current source is the wide amplitude of oscillation, cascade utmost point NMOS constant-current source.The cascode current source structure can improve output impedance, improves the performance of constant-current source, can reduce the non-ideal characteristic of charging or discharging current mismatch preferably; The bias structure of the wide amplitude of oscillation then can make its output voltage VO UT in the scope than broad, and it is relatively good that the matching properties of charging or discharging current still keeps, and therefore, the reference frequency output of voltage controlled oscillator can be greatly improved.The constant-current source circuit structure of the wide amplitude of oscillation, the cascade utmost point specifically describes as follows.
As shown in Figure 3, the wide amplitude of oscillation, cascade utmost point PMOS constant-current source Ib1 comprise 5 PMOS pipes such as Mp11, Mp12, Mp13, Mp14 and Mp15, and wherein: the source electrode of Mp11, Mp12 and Mp13 is connected to power vd D; The source electrode of Mp14 is connected to the drain electrode of Mp11; The source electrode of Mp15 is connected to the drain electrode of Mp12; The grid of Mp11 and Mp12 and the drain electrode of Mp14 are connected to drop-down constant-current source; The grid of Mp13, Mp14 and Mp15 and the drain electrode of Mp13 are connected to ground through a constant current source Icp; The drain electrode of Mp15 is connected to the first node 1 of complementary switch circuit.
The wide amplitude of oscillation, cascade utmost point NMOS constant-current source Ib2 comprise 7 NMOS pipes such as Mn11, Mn12, Mn13, Mn14, Mn15, Mn16 and Mn17, and wherein: the source electrode of Mn11, Mn12, Mn13 and Mn14 is connected to ground; The source electrode of Mn15 is connected to the drain electrode of Mn11; The source electrode of Mn16 is connected to the drain electrode of Mn12; The source electrode of Mn17 is connected to the drain electrode of Mn13; The grid of Mn11 and Mn12 and Mn13 and the drain electrode of Mn15 are connected to power vd D; The grid of Mn14, Mn15, Mn16 and Mn17 connects; The drain electrode of Mn14 is connected to power vd D; The drain electrode of Mn16 is connected to draws constant-current source, specifically is the drain electrode that is connected to Mp14; The drain electrode of Mn17 is connected to the 3rd node 3 of complementary switch circuit.
Above embodiment is a kind of high performance charge pump solution that has; The implementation of its physical circuit has following characteristics: the wide amplitude of oscillation; The cascode current source structure can improve output impedance, improves the performance of constant-current source, can reduce the non-ideal characteristic of charging or discharging current mismatch preferably; Adopt switch and a unity gain amplifier of four complementations can eliminate the shared effect of electric charge preferably, reduced phase error.The charge pump circuit of the utility model in the phase-locked loop circuit of low jitter, can obviously improve the performance of phase-locked loop adaptable across the low-power consumption of high-performance digital systems.
Only be the preferred implementation of the utility model below, should be pointed out that above-mentioned preferred implementation should not be regarded as the restriction to the utility model, the protection range of the utility model should be as the criterion with claim institute restricted portion.For those skilled in the art, in spirit that does not break away from the utility model and scope, can also make some improvement and retouching, these improvement and retouching also should be regarded as the protection range of the utility model.

Claims (10)

1. a charge pump circuit that is used for phase-locked loop is characterized in that, comprises drawing a constant-current source and a drop-down constant-current source on one group of complementary switch circuit; Said complementary switch circuit be connected to the phase-locked loop phase frequency detector on draw signal output port and pulldown signal output port; Draw constant-current source to be connected to the first node of complementary switch circuit on said, said drop-down constant-current source is connected to the 3rd node of said complementary switch circuit, so that the mirror image charging and discharging currents of phase-locked loop mirror loop filter to be provided.
2. the charge pump circuit that is used for phase-locked loop as claimed in claim 1; It is characterized in that; Comprise a unit gain amplifying circuit; The input of said unit gain amplifying circuit connects the Section Point of said complementary switch circuit, and the output of said unit gain amplifying circuit connects the 4th node of said complementary switch circuit.
3. the charge pump circuit that is used for phase-locked loop as claimed in claim 1 is characterized in that, it is a complementary MOS switching circuit that said complementary switch closes circuit.
4. the charge pump circuit that is used for phase-locked loop as claimed in claim 3; It is characterized in that said complementary MOS switching circuit comprises PMOS pipe, NMOS pipe, the 2nd PMOS pipe, the 2nd NMOS pipe; The 3rd PMOS pipe, the 3rd NMOS pipe; The 4th PMOS pipe, the 4th NMOS pipe, wherein: the drain electrode of the drain electrode of the source electrode of said PMOS pipe, NMOS pipe, the source electrode of the 2nd PMOS pipe and the 2nd NMOS pipe connects jointly, forms the first node of said complementary MOS switching circuit; The drain electrode of the source electrode of the source electrode of the drain electrode of said PMOS pipe, NMOS pipe, the 3rd PMOS pipe, the 3rd NMOS pipe connects jointly, forms the Section Point of said complementary MOS switching circuit; The source electrode of the drain electrode of the source electrode of the drain electrode of said the 3rd PMOS pipe, the 3rd NMOS pipe, the 4th PMOS pipe, the 4th NMOS pipe connects jointly, forms the 3rd node of said complementary MOS switching circuit; The source electrode of the drain electrode of the drain electrode of the source electrode of said the 4th PMOS pipe, the 4th NMOS pipe, the 2nd PMOS pipe, the 2nd NMOS pipe connects jointly, forms the 4th node of said complementary MOS switching circuit; The grid of the grid of the grid of the grid of said PMOS pipe, NMOS pipe, the 2nd PMOS pipe and the 2nd NMOS pipe be connected to the phase-locked loop phase frequency detector on draw signal output port; The grid of the grid of the grid of the grid of said the 3rd PMOS pipe, the 3rd NMOS pipe, the 4th PMOS pipe and the 4th NMOS pipe is connected to the pulldown signal output port of phase-locked loop phase frequency detector.
5. the charge pump circuit that is used for phase-locked loop as claimed in claim 4 is characterized in that, the grid of the grid of said PMOS pipe and said the 2nd NMOS pipe be connected to the phase-locked loop phase frequency detector on draw signal negative output port; The grid of the grid of said the 2nd PMOS pipe and said NMOS pipe be connected to the phase-locked loop phase frequency detector on draw signal positive output end mouth; The grid of the grid of said the 3rd PMOS pipe and said the 4th NMOS pipe is connected to the pulldown signal negative output port of phase-locked loop phase frequency detector; The grid of the grid of said the 4th PMOS pipe and said the 3rd NMOS pipe is connected to the pulldown signal positive output end mouth of phase-locked loop phase frequency detector.
6. the charge pump circuit that is used for phase-locked loop as claimed in claim 1 is characterized in that, drawing constant-current source on said is the wide amplitude of oscillation, cascade utmost point PMOS constant-current source.
7. the charge pump circuit that is used for phase-locked loop as claimed in claim 6; It is characterized in that; The said wide amplitude of oscillation, cascade utmost point PMOS constant-current source comprise: the 11 PMOS pipe, the 12 PMOS pipe, the 13 PMOS pipe, the 14 PMOS pipe and the 15 PMOS pipe, and wherein: the source electrode of the source electrode of said the 11 PMOS pipe, the 12 PMOS pipe and the source electrode of the 13 PMOS pipe are connected to power supply; The source electrode of said the 14 PMOS pipe is connected to the drain electrode of said the 11 PMOS pipe; The source electrode of said the 15 PMOS pipe is connected to the drain electrode of said the 12 PMOS pipe; The drain electrode of the grid of the grid of said the 11 PMOS pipe and said the 12 PMOS pipe and said the 14 PMOS pipe is connected to said drop-down constant-current source; The drain electrode of the grid of the grid of the grid of said the 13 PMOS pipe, the 14 PMOS pipe and the 15 PMOS pipe and said the 13 PMOS pipe is connected to ground; The drain electrode of said the 15 PMOS pipe is connected to the first node of said complementary switch circuit.
8. the charge pump circuit that is used for phase-locked loop as claimed in claim 1 is characterized in that, said drop-down constant-current source is the wide amplitude of oscillation, cascade utmost point NMOS constant-current source.
9. the charge pump circuit that is used for phase-locked loop as claimed in claim 8; It is characterized in that; The said wide amplitude of oscillation, cascade utmost point NMOS constant-current source comprise: the 11 NMOS pipe, the 12 NMOS pipe, the 13 NMOS pipe, the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe and the 17 NMOS pipe, and wherein: the source electrode of the source electrode of the source electrode of said the 11 NMOS pipe, the 12 NMOS pipe, the source electrode of the 13 NMOS pipe and the 14 NMOS pipe is connected to ground; The source electrode of said the 15 NMOS pipe is connected to the drain electrode of said the 11 NMOS pipe; The source electrode of said the 16 NMOS pipe is connected to the drain electrode of said the 12 NMOS pipe; The source electrode of said the 17 NMOS pipe is connected to the drain electrode of said the 13 NMOS pipe; The drain electrode of the grid of the grid of the grid of said the 11 NMOS pipe, the 12 NMOS pipe and the 13 NMOS pipe and said the 15 NMOS pipe is connected to power supply; The grid of the grid of the grid of the grid of said the 14 NMOS pipe, the 15 NMOS pipe, the 16 NMOS pipe and the 17 NMOS pipe connects; The drain electrode of said the 14 NMOS pipe is connected to power supply; The drain electrode of said the 16 NMOS pipe is connected to draws constant-current source on said; The drain electrode of said the 17 NMOS pipe is connected to the 3rd node of said complementary switch circuit.
10. like each described charge pump circuit that is used for phase-locked loop of claim 1~9, it is characterized in that, draw constant-current source to be connected to ground on said through a constant current source.
CN 201120194658 2011-06-10 2011-06-10 Charge pump circuit for phase-locked loop Expired - Lifetime CN202167988U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887966A (en) * 2014-03-24 2014-06-25 华为技术有限公司 Charge pump implementation circuit
CN103904870A (en) * 2012-12-28 2014-07-02 北京兆易创新科技股份有限公司 Charge pump circuit system
CN103973100A (en) * 2013-01-25 2014-08-06 北京兆易创新科技股份有限公司 Positive and negative voltage generation device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103904870A (en) * 2012-12-28 2014-07-02 北京兆易创新科技股份有限公司 Charge pump circuit system
CN103904870B (en) * 2012-12-28 2016-12-28 北京兆易创新科技股份有限公司 A kind of charge pump circuit system
CN103973100A (en) * 2013-01-25 2014-08-06 北京兆易创新科技股份有限公司 Positive and negative voltage generation device
CN103973100B (en) * 2013-01-25 2017-02-08 北京兆易创新科技股份有限公司 Positive and negative voltage generation device
CN103887966A (en) * 2014-03-24 2014-06-25 华为技术有限公司 Charge pump implementation circuit
CN103887966B (en) * 2014-03-24 2017-06-20 华为技术有限公司 Charge pump realizes circuit

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