CN109936361A - A kind of fractional frequency division frequency synthesizer containing PFD/DAC quantizing noise technology for eliminating - Google Patents
A kind of fractional frequency division frequency synthesizer containing PFD/DAC quantizing noise technology for eliminating Download PDFInfo
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Abstract
The invention discloses a kind of fractional frequency division frequency synthesizers containing PFD/DAC quantizing noise technology for eliminating, fractional frequency division ratio is inputted to sigma-delta modulator, sigma-delta modulator controls real-time integer frequency ratio and is given to frequency divider, concussion is in a frequency near target frequency when VCO is initial, output frequency division clock is given to PFD after frequency divider divides, PFD carries out frequency to REF clock and frequency-dividing clock and phase identifies, output charge and discharge control pulse is given to DAC, DAC exports charge or discharge electric current according to control pulse, electric current changes the control voltage of VCO after loop filter, to change the frequency and phase of output clock, wherein PFD/DAC module can compensate charging or discharging current according to the modulator residual error received, it is missed with offsetting the extra phase introduced due to modulation Difference, VCO can export the clock for being exactly equal to target frequency after final loop stability.
Description
Technical field
The invention belongs to fractional frequency division frequency synthesizer fields, and in particular to kind eliminates skill containing PFD/DAC quantizing noise
The fractional frequency division frequency synthesizer of art.
Background technique
Fractional frequency division frequency synthesizer can generate high-resolution high-frequency clock, have important valence to many communication systems
Value.Traditional fractional frequency division frequency synthesizer include PFD (phase frequency detector), CP (charge pump), modulator, loop filter and
Frequency divider.Since frequency divider only realizes integral frequency divisioil, need by the instantaneous frequency dividing ratio of modulator control to realize dynamic decimal
Frequency dividing (such as 6 frequency-dividing clocks are exported after one 5 frequency-dividing clock of output, the average divide ratio of such 2 frequency dividings is
5.5), however, the Dynamic dithering of modulator can be phase locked ring loop response, the quantizing noise with very high clutter components is generated,
Deteriorate synthesizer phase noise performance.
Quantizing noise is broken up and is shaped at higher frequency, then led to by the order of increase sigma-delta modulator by initial people
Loop filter is crossed to inhibit influence of the quantizing noise to output performance, but under this method, when loop bandwidth is larger, still
There can be more serious deterioration to the phase noise of high frequency treatment.
Summary of the invention
The present invention will be used to provide a kind of fractional frequency division frequency synthesizer containing PFD/DAC quantizing noise technology for eliminating,
By DAC compensation quantizing noise in the way of, quantization error is offset within each phase demodulation period, be effectively reduced be embodied in it is defeated
The quantizing noise of outlet.
In order to solve the above technical problems, the present invention adopts the following technical scheme that:
A kind of fractional frequency division frequency synthesizer containing PFD/DAC quantizing noise technology for eliminating, including phase frequency detector/number
Mode converter PFD/DAC, loop filter, voltage controlled oscillator VCO, dual-mode frequency divider, accumulator and sigma-delta modulator, REF are
The reference frequency clock of input, VCO clock are that phaselocked loop exports clock, and frequency divider is the integer frequency divider of variable dividing radio, defeated
Enter fractional frequency division ratio to sigma-delta modulator, sigma-delta modulator controls real-time integer frequency ratio and is given to frequency divider, shakes when VCO is initial
It swings in a frequency near target frequency, output frequency division clock is given to PFD after frequency divider divides, and PFD is to REF clock
Frequency is carried out with frequency-dividing clock and phase identifies, and output charge and discharge control pulse is given to DAC, and DAC is filled according to control pulse output
Electricity or discharge current, electric current change the control voltage of VCO after loop filter, to change the frequency and phase of output clock
Position, wherein PFD/DAC module can compensate charging or discharging current according to the modulator residual error received, to offset since modulation is drawn
The extra phase error entered, VCO can export the clock for being exactly equal to target frequency after final loop stability.
Preferably, the sigma-delta modulator is single order Mash sigma-delta modulator.
Preferably, when the input of modulator decimal is 0.3, by cumulative, the integer in continuous 10 frequency-dividing clock periods is defeated
It is respectively as follows: 0-0-0-1-0-0-1-0-0-1 with residual error out；0.3-0.6-0.9-0.2-0.5-0.8-0.1-0.4-0.7-0, integer
Frequency divider carries out 8 frequency dividings when being 0,9 frequency dividing of frequency divider progress when integer is 1, and average frequency dividing ratio is 8.3 in time domain, each week
The phase error that phase phase discriminator is identified are as follows: Φerror=residual error/2 π needs to subtract Φ when DAC is respondederrorIt is corresponding
Part increases by one when PFD phase demodulation and fixed is greater than a TvcoThe phase error in period, so that frequency divider output phase is advanced
In one VCO of reference clock more than the period, then electric discharge when, by the current value in a VCO periodic width according to residual error into
Row compensation, compensates size of current are as follows: IIt mends=(1- residual error) Icp, the corresponding charge accumulation amount of compensation electric current is QIt mends=IIt mends=Tvco
=(1- residual error) Icp·Tvco, the corresponding charge accumulation amount of phase error caused by residual error is Qerr=residual error Tvco·Icp,
The net charge cumulant for then compensating electric current and phase error is 1, eliminates quantization error, and phaselocked loop precise operation is joined at 8.3 times
It examines at frequency.
Preferably, the DAC uses two current steer type DAC, one of them is by current source IP1 and by UP1/UP2/
The switch composition of UPN1/UPN2 control, another sinks IP2 by electric current and forms with the switch controlled by DN1/DN2/DNN1/DNN2,
Respective switching signal is passed through by phi1, phi2, dac_data, dac_datan, UP and vdd, vss to be generated with door, wherein phi1
It is the discharge switch pulse of phase discriminator output with phi2, wherein the rising edge of phi2 lags behind mono- VCO period of phi1, and DAC exists
Discharging compensation electric current is exported in this VCO period, UP is the charge switch pulse by the PFD fixed width generated, is greater than one
A VCO period, IdownAnd IupRespectively electric discharge, charging current waveform.
Using the present invention with following the utility model has the advantages that can be by DSM modulator using this structure fractional frequency-division phase-locked loop
The phase noise of introducing is reduced to 1/2n, 1/64), the property of fractional frequency-division phase-locked loop is greatly improved in the embodiment of the present invention
Can, and work is made it possible under bigger loop bandwidth.
Detailed description of the invention
Fig. 1 is the fractional frequency division frequency synthesizer containing PFD/DAC quantizing noise technology for eliminating of the embodiment of the present invention
Structure principle chart；
Fig. 2 is the fractional frequency division frequency synthesizer containing PFD/DAC quantizing noise technology for eliminating of the embodiment of the present invention
Response wave shape figure；
Fig. 3 is in the fractional frequency division frequency synthesizer containing PFD/DAC quantizing noise technology for eliminating of the embodiment of the present invention
The schematic diagram of DAC；
Fig. 4 is in the fractional frequency division frequency synthesizer containing PFD/DAC quantizing noise technology for eliminating of the embodiment of the present invention
The structural schematic diagram of every potential difference parallel circuit of DAC.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
Referring to Fig.1, it show a kind of fractional frequency division containing PFD/DAC quantizing noise technology for eliminating of the embodiment of the present invention
The structure principle chart of frequency synthesizer, including phase frequency detector/digital analog converter (PFD/DAC), loop filter, voltage controlled oscillation
Device VCO, dual-mode frequency divider, accumulator and sigma-delta modulator, REF are the reference frequency clock of input, and VCO clock is phaselocked loop
Clock is exported, frequency divider is the integer frequency divider of variable dividing radio, input fractional frequency division ratio to sigma-delta modulator, ∑-Δ modulation
Device controls real-time integer frequency ratio and is given to frequency divider, and concussion is in a frequency near target frequency when VCO is initial, through excessive
Output frequency division clock is given to PFD after frequency device frequency dividing, and PFD carries out frequency to REF clock and frequency-dividing clock and phase identifies, and output is filled
Control of discharge pulse is given to DAC, and DAC exports charge or discharge electric current according to control pulse, and electric current changes after loop filter
Become the control voltage of VCO, to change the frequency and phase of output clock, wherein PFD/DAC module can be according to the tune received
Device residual error processed compensates charging or discharging current, to offset the extra phase error introduced due to modulation, VCO after final loop stability
The clock for being exactly equal to target frequency can be exported.
The working principle of PLL under this structure (phaselocked loop, Phase Locked Loop) is illustrated by taking 8.3 frequency dividings as an example
As follows, modulator selects single order Mash sigma-delta modulator (being in the nature an accumulator), and decimal input at this time is 0.3, by tired
Add, the integer output and residual error in continuous 10 frequency-dividing clock periods are as shown in the table:
| Integer | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| Residual error | 0.3 | 0.6 | 0.9 | 0.2 | 0.5 | 0.8 | 0.1 | 0.4 | 0.7 | 0 |
Corresponding, frequency divider carries out 8 frequency dividings when integer is 0, and frequency divider carries out 9 frequency dividings when integer is 1, so in the time domain
Average frequency dividing ratio is 9.3, the phase error that each period phase discriminator is identified are as follows: Φerror=residual error/2 π, and this part by
Phase error caused by residual error be actually not intended to by loop response (if this fractional phase error of loop response, VCO output
Frequency can also change according to the change of real-time frequency dividing ratio, can introduction volume although frequency dividing ratio average in this way remains as 8.3
Change noise, and if be not responding to this phase error, final VCO output can stablize not to change in 8.3 times of reference frequencies), institute
To need to subtract Φ when DAC is respondederrorCorresponding part increases by one fixed big when implementation is PFD phase demodulation
In a TvcoThe phase error in period, so that it is more than the period to be ahead of one VCO of reference clock for frequency divider output phase, then
In electric discharge, the current value in a VCO periodic width is compensated according to residual error, compensates size of current are as follows: IIt mends=(1- is residual
Difference) Icp, the corresponding charge accumulation amount of compensation electric current is QIt mends=IIt mends·Tvco=(1- residual error) Icp·Tvco, caused by residual error
The corresponding charge accumulation amount of phase error is Qerr=residual error Tvco·Icp, then the net charge accumulation of electric current and phase error is compensated
Amount is Tvco·Icp, eliminate quantization error, in the ideal case phaselocked loop will precise operation at 8.3 times of reference frequencies.
Waveform response is as shown in Fig. 2, REF is reference clock, and VCO is that phaselocked loop exports clock, and frequency is 8.3 times of REF,
DIV is frequency divider frequency dividing output, and the frequency dividing ratio in continuous 10 periods is 8,8,8,9,8,8,9,8,8,9；Phi1 and phi2
For the discharge switch pulse of phase discriminator output, wherein the rising edge of phi2 lags behind mono- VCO period of phi1, and DAC is at this
Discharging compensation electric current is exported in the VCO period, UP is (to be greater than one VCO weeks by the charge switch pulse of the PFD fixed width generated
Phase), IdownAnd IupRespectively electric discharge, charging current waveform, ∫ Idown+IupFor charging and discharging currents integration amount, corresponding DAC output point
Charge accumulated amount.
The above-mentioned function compensated to the electric current determined in the moment may be implemented in the DAC structure that the embodiment of the present invention proposes
Energy.As shown in figure 3, Dac_data<63:0>is the input after residual error decoding, decoding relationship is one of feasible structure
1 number=residual error is rounded multiplied by after 64 in Dac_data<63:0>: P and N respectively indicate difference channel positive negative part (for
Single-end circuit takes the corresponding circuit of P), respectively using 64 (in fact 2nPosition) identical electric current position parallel output, often
One structure is as shown in Figure 4.
Wherein the control code word that Dac_data/Dac_datan is received by every, OutP/OutN are output point, and Dmy is
It being not required to receive the node of current steer electric current when output electric current, this structure is applied to fully differential structure, if being applied to single-ended structure,
Part in " N " dotted line frame is left out.
According to required function, the structure of proposition is based primarily upon 2 current steer type DAC, one of them is by current source IP1
(IN1) it is formed with the switch controlled by UP1/UP2/UPN1/UPN2, another is sunk IP2 (IN2) by electric current and by DN1/DN2/
DNN1/DNN2 control switch composition, respective switching signal by phi1, phi2, dac_data, dac_datan, UP and vdd,
Vss (low and high level) by being generated with door in figure, it will be appreciated by those skilled in the art that thing, as long as meeting logic needed for function
Relationship, it is possible to use other logic gates are realized.
For the structure in P frame, it is all receive data be 0 electric current position DN1 is connected between phi1 high period, receive
Only DN2 is connected in phi2 high period part in the electric current position that data is 1, and UP1 is connected between UP high period；Conversely, in N frame
Structure, it is all receive data be 0 electric current position UP1 is connected between phi1 high level, receive data be 1 electric current position only exist
UP2 is connected during phi2, DN1 is connected between UP high period.From the point of view of the electric current of output point, exactly exported after phi1 arrival
Discharging compensation electric current, phi2 export maximum discharge current when opening, UP exports charging current when opening.Meet with required function.
1/ is reduced to using the phase noise that this structure fractional frequency-division phase-locked loop can theoretically introduce DSM modulator
2n(being 1/64 in the example of patent), greatly improves the performance of fractional frequency-division phase-locked loop, and make it possible to work more
Under big loop bandwidth.
It should be appreciated that exemplary embodiment as described herein is illustrative and be not restrictive.Although being retouched in conjunction with attached drawing
One or more embodiments of the invention is stated, it should be understood by one skilled in the art that not departing from through appended right
In the case where the spirit and scope of the present invention defined by it is required that, the change of various forms and details can be made.
Claims (4)
1. a kind of fractional frequency division frequency synthesizer containing PFD/DAC quantizing noise technology for eliminating, which is characterized in that including frequency discrimination
Phase discriminator/digital analog converter PFD/DAC, loop filter, voltage controlled oscillator VCO, dual-mode frequency divider, accumulator and ∑-Δ tune
Device processed, REF are the reference frequency clock of input, and VCO clock is that phaselocked loop exports clock, and frequency divider is the integer of variable dividing radio
Frequency divider, input fractional frequency division ratio to sigma-delta modulator, sigma-delta modulator control real-time integer frequency ratio and are given to frequency divider,
Concussion is in a frequency near target frequency when VCO is initial, and output frequency division clock is given to PFD after frequency divider divides,
PFD carries out frequency to REF clock and frequency-dividing clock and phase identifies, and output charge and discharge control pulse is given to DAC, and DAC is according to control
Pulse processed exports charge or discharge electric current, and electric current changes the control voltage of VCO after loop filter, thus when changing output
The frequency and phase of clock, wherein PFD/DAC module can compensate charging or discharging current according to the modulator residual error received, to support
Disappear the extra phase error introduced due to modulation, after final loop stability VCO can export be exactly equal to target frequency when
Clock.
2. the fractional frequency division frequency synthesizer as described in claim 1 containing PFD/DAC quantizing noise technology for eliminating, feature
It is, the sigma-delta modulator is single order Mash sigma-delta modulator.
3. the fractional frequency division frequency synthesizer as claimed in claim 2 containing PFD/DAC quantizing noise technology for eliminating, feature
It is, the integer output and residual error point when the input of modulator decimal is 0.3, by cumulative, in continuous 10 frequency-dividing clock periods
Not are as follows: 0-0-0-1-0-0-1-0-0-1；0.3-0.6-0.9-0.2-0.5-0.8-0.1-0.4-0.7-0, integer divide when being 0
Device carries out 8 frequency dividings, and frequency divider carries out 9 frequency dividings when integer is 1, and average frequency dividing ratio is 8.3 in the time domain, each period phase discriminator
The phase error identified are as follows: Φerror=residual error/2 π subtracts Φ when DAC is respondederrorCorresponding part, when PFD phase demodulation, increase
One is added fixed to be greater than a TvcoThe phase error in period, so that frequency divider output phase is ahead of one VCO of reference clock
More than the period, then in electric discharge, the current value in a VCO periodic width is compensated according to residual error, compensation electric current is big
It is small are as follows: IIt mends=(1- residual error) Icp, the corresponding charge accumulation amount of compensation electric current is QIt mends=IIt mends·Tvco=(1- residual error) Icp·
Tvco, the corresponding charge accumulation amount of phase error caused by residual error is Qerr=residual error Tvco·Icp, then compensate electric current and phase missed
The net charge cumulant of difference is 1, eliminates quantization error, phaselocked loop precise operation is at 8.3 times of reference frequencies.
4. the fractional frequency division frequency synthesizer as claimed in claim 3 containing PFD/DAC quantizing noise technology for eliminating, feature
It is, the DAC uses two current steer type DAC, one of them is controlled by current source IP1 with by UP1/UP2/UPN1/UPN2
Switch composition, another sinks IP2 by electric current and forms with the switch controlled by DN1/DN2/DNN1/DNN2, and respective switch is believed
Number by phi1, phi2, dac_data, dac_datan, UP and vdd, vSS pass through with door generate, wherein phi1 and phi2 be phase demodulation
The discharge switch pulse of device output, wherein the rising edge of phi2 lags behind mono- VCO period of phi1, and DAC is in this VCO period
Interior output discharging compensation electric current, UP are the charge switch pulse by the PFD fixed width generated, are greater than a VCO period, Idown
And IupRespectively electric discharge, charging current waveform.
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Cited By (4)
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| CN112636748A (en) * | 2020-11-30 | 2021-04-09 | 深圳市国微电子有限公司 | Spread spectrum clock circuit and communication chip |
| CN112953531A (en) * | 2021-02-18 | 2021-06-11 | 华南理工大学 | Phase-locked loop fractional frequency division method based on novel delta-sigma modulator |
| CN112953516A (en) * | 2021-01-27 | 2021-06-11 | 浙江大学 | Low-power-consumption decimal frequency division phase-locked loop circuit |
| CN114189249A (en) * | 2022-02-14 | 2022-03-15 | 微龛(广州)半导体有限公司 | Open loop fractional divider and clock system |
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