JPS63196112A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To reduce the phase jitter without losing high speed response characteristic by varying a delay supplied to an overflow signal in response to a frequency setting value and a remaining data when a phase accumulator (PACC) generates the overflow signal. CONSTITUTION:A reference frequency fr is supplied to the PACC 2 and a clock input of a pulse synchronizer circuit 7 and the overflow signal A of the PACC 2 is fed to the circuit 7 and the write pulse input of a remaining data memory 8. A frequency setting circuit 1A supplies a frequency setting value Fi to a summing input of the PACC 2 and a multiplication coefficient Fid inversely proportional to the Fi is fed to a multiplier 10. The multiplier 10 supplies the result of multiplication Drm between the coefficient and the output Dr of the memory 8 to a D/A converter 4. The circuit 7 uses a reference signal to synchronize the inputted signal A to absorb the fluctuation caused in the process of accumulation of the PACC 2 and supplies an output signal f0to a voltage controlled phase shifter 9. A delay quantity fed to the signal f0 is large when the output voltage of the converter 4 is high and less when the output voltage is low to output a signal of a frequency fd.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital direct synthesis frequency synthesizer that can switch frequencies faster than a phase-locked loop frequency synthesizer.

(Prior art and its problems) A conventional device of this kind was constructed as in the first embodiment shown in FIG. In FIG. 6, 1 is a frequency setting circuit, 2 is a phase accumulator (hereinafter abbreviated as PACC), and 3 is a sine waveform ROM.

4t is a kD/A converter, 5 is a low-pass filter, and 6 is a reference oscillator. Here, as shown in FIG. 8, the PACC2 is composed of full adders 21, 22.23 and D-type flip-flops 24, 25, 26, and uses the frequency setting value Fi given by the frequency setting circuit l to the reference oscillator 6. It has the function of a digital integrator that performs cumulative addition every oscillation period 1/fr.

FIG. 7(A) is a graphical representation of the operation of PACC2, where the horizontal axis shows time and the vertical axis shows the accumulated value of PACC2. FIG. 7(A) shows that the cumulative value increases with the passage of time. The output of the PACC2 is connected to the address input of the sine waveform ROM3, and triangular waveform changes in the input data are converted into sinusoidal waveform changes and output. This situation is expressed as shown in FIG. 7(a).

Next, the digital value outputted from the sine waveform ROM 3 is converted into an analog value by the D/A converter 4, thereby obtaining the waveform shown in FIG. Therefore, by applying the output of the D/A converter 4 to the low-pass filter 5, it is possible to obtain a sinusoidal output signal with the harmonic components attenuated, as shown in FIG. 1(1). When the cumulative value of PACC2 reaches the total capacitance value, an overflow signal is generated and the cumulative addition operation is repeated again, so that a continuous sine wave output can be obtained from the low-pass filter 5.

For applications that do not necessarily require a sine wave as the output of a frequency synthesizer, as in the second conventional embodiment shown in FIG. It is also possible to use the overflow signal in its pulse waveform. In this case as well, it is possible to generate a frequency proportional to the frequency setting value (digital information) set by the frequency setting circuit 1, as in the first conventional embodiment. Now, in FIG. 9(T), if the frequency setting value of the frequency setting circuit l is Fi, the total capacitance value of PACC2 is Nt, and the reference frequency of the reference oscillator 6 is fr, then the output frequency fo is fo=
frX f i/Nt.

For example, f r= l MHz, Fi= l, Nt=
10, the output frequency fo is fo=FiX fr/
Nt=Pix1/ 1G [MHz] = Q,■',
1 iHz]. Now, as mentioned above, by changing the set value fi, it is possible to generate an output frequency fo proportional to Fi, but the ratio of the reference frequency fr to the output frequency fo, in other words, the total When the ratio Nt/Pi between the capacitance value Nt and the frequency setting value Fi is an integer, the output signal does not include phase jitter in principle. FIG. 9(A) shows an example of operation when Nt/Pi-5, where the horizontal axis shows time and the vertical axis shows the accumulated value of PACC2. The figure shows a state in which the cumulative value increases every reference period 1/fr, and an overflow signal (indicated by Δ in the figure) is generated regularly every 5/fr (=l/fo) periods. This is what is shown. However, if Nt/Pi is not an integer, the output signal will include phase jitter.

Figure 9 (a) is an example of operation when Nt/Fi = 10/3, but the cycle of generating the overflow signal is 4/3.
There are cases of fr and cases of 3/fr, and the periods are not equally spaced. The figure shows once every 4/fr period, 3/fr
This shows that overflow signals are generated twice in a period of . Therefore, the frequency spectrum of the output signal is no longer a line spectrum, but becomes a frequency spectrum including unnecessary band noise. Various conventional measures have been taken to reduce phase jitter and improve the purity of the output signal.

(a) In FIG. 6, a method for reducing phase jitter by switching the blocking layer wave number of the low-pass filter 5 according to the output frequency, (b) a region where the output frequency fo is sufficiently small compared to the reference frequency fr, in other words, Nt/ (c) A method in which the output signal is used after dividing the frequency to reduce the phase jitter; (d) A method in which the output signal is used after dividing the frequency to reduce the phase jitter. Attempts have been made to provide a reference signal as an input to a phase-locked loop frequency synthesizer and to reduce phase jitter using a low-pass filter within the phase-locked loop.

However, the conventional methods described above have the following problems: (a) The effect of reducing phase jitter is not sufficient; (b)
There were problems such as (c) the output frequency would be reduced, and (d) the high-speed response characteristic that is a characteristic of direct synthesis frequency synthesizers would be lost.

(Means for Solving the Problems) In order to solve these problems, the present invention provides PACC2
Means for changing the amount of delay given to the overflow signal according to the residual data and the frequency setting value when the overflow signal is generated is provided to cancel phase jitter, and will be explained in detail below with reference to the drawings.

(Embodiment) FIG. 1 shows an embodiment of the present invention, and the same parts as in FIG. 6 are designated by the same numbers. In the same figure, 6 is the reference oscillator, 2 is P
ACC, 8 is a residual data memory, 1A is a frequency setting circuit, IO is a multiplier, 4 is a D/A converter, 7 is a pulse synchronizer, and 9 is a voltage controlled phase shifter. In the figure, first, the output of the reference oscillator 6 that outputs the reference frequency fr is added to the clock input of PACC2 and the pulse synchronizer 7, and the overflow signal of PACC2 having a total capacitance value Nt is added to the signal input of the pulse synchronizer 7. The data output is added to the write pulse input of the residual data memory 8 as an input. Then, the frequency setting circuit IA sets the frequency setting value Fi to the PACC2 for setting the output frequency of the frequency synthesizer to a desired value.
A multiplication coefficient Fid, which is inversely proportional to Fi, is added to one input of the multiplier 10. Multiplier IO
The other input is the output take D of the residual data memory 8.
r is input, and the multiplication result Drm is given to the input of the D/A converter 4. In addition, the output signal fo of the pulse synchronizer 7
With the output of the D/A converter 4 as the limiting input, the voltage-controlled phase shifter 9 outputs a signal having a frequency fd. In the above circuit connection, to further explain each function, the reference oscillator 6 uses, for example, a temperature compensated crystal oscillator (TcXO) depending on the required stability, and outputs a logic level such as TTL/CMO8. do. P.A.
CC2 is basically a full adder and a D type flip-flop connected in cascade as described above using FIG. 8, but when the number of addition bits exceeds 8 bits,
Although it is preferable to use a high-speed adder based on the carry-lookahead method, for convenience of explanation, it is assumed that the configuration is equivalent to that shown in FIG.

The residual data memory 8 is a memory that stores residual data when PACC2 overflows. Specifically, the required number of D type flip-flops are prepared, and the PA is connected to the D input.
This is achieved by applying the output of CC2 and applying the overflow signal as a write pulse to the clock input terminal. Further, the frequency setting circuit IA specifically uses a microcomputer or the like to apply a frequency setting value Fi and a multiplication coefficient Fid inversely proportional to Fi to the inputs of the PACC2 and the multiplier IO, respectively. Here, the maximum value of Fl is F i
max, then F id= F imax/ F i
When Pi is given from the relational expression, the microcomputer (or divider) calculates Fid and outputs the result as a multiplication coefficient. The multiplier IO is connected to the residual data memory 8.
Output data Dr and frequency setting circuit! - Multiply the multiplication coefficient Fid output from A digitally to obtain the multiplication result D
rm, and the D/A converter 4 converts the digital information into an analog voltage.

Furthermore, in the process of cumulative addition by the PACC2, the overflow signal includes fluctuations due to fluctuations in operating time during internal carry. Therefore, the pulse synchronizer 7 absorbs the fluctuation by synchronizing the input overflow signal with a reference signal.

In addition, the pulse synchronizer 7 has a function of converting the waveform of the output signal into a waveform suitable for input to the voltage-controlled phase shifter 9 at the next stage and outputting the converted waveform. This voltage controlled phase shifter 9 includes an electronic switch 91 as shown in FIG.
．． It is composed of a constant current source 92, an integrating capacitor 93, and an ultra-high-speed precision comparator 94. Now, if the output of the pulse synchronizer 7 is a signal with the waveform shown in FIG.
1 is turned on to rapidly discharge the integrating capacitor 93, and the electronic switch 91 is turned off at a low level.

Therefore, if the capacitance of the integrating capacitor 93 is 01, the charging current is 11, and the elapsed time is t, then when the electronic switch 91 is turned off, the potential of the integrating capacitor 93 increases linearly as a linear function of (i/c)t. .

Then, when the potential exceeds the output voltage of the D/A converter 4 (indicated by the broken line in FIG. 5(a)), the output of the ultra-high-speed precision comparator 94 becomes as shown in FIG. If the output potential of is assumed to be low level, it will be switched to high level. In the next cycle, when the output voltage of the D/A converter 4 decreases as shown by the broken line in FIG. The delay time td2 until the potential is switched is smaller than the previous delay time tdl. In other words, when the output voltage of the D/A converter 4 as a control input is high, the amount of delay given to the output signal of the pulse synchronizer 7, which is given as an input signal, is large, and when the control input voltage is low, the amount of delay is small. It is assumed that the voltage-controlled phase shifter 9 in this embodiment operates.

Now, in the embodiment of the present invention consisting of the circuit configuration, connections, and functions as described above, the output frequency fr of the reference oscillator 6 is, for example, 10 MHz, the total capacitance value Nt of the P AC C2 is 107, the frequency setting value Fi is 200, 010, the output frequency fd=fr-Fi/NL, that is, fd=Fi=200
．． A specific example of obtaining 0IO [Hz] will be explained below.

Note that for convenience of explanation, the multiplication coefficient Fid is assumed to be an integer 1.

First, PACC2 changes from the initial state zero to the reference period 1/
Repeat the cumulative addition every f r, and when an overflow signal occurs, extract the residual data of PACC2 and store it in the residual data memory 8. As shown in Figure 3 (A), the data is plotted with time on the horizontal axis. If taken, it will change into a sawtooth shape over time. In this case, the maximum value of the residual data is Pi-1
, that is, 200°009. In this example, the ratio Nt/Fi is not an integer but 49.9975, and it is sufficient that overflow signals are generated at equal intervals as shown in Figure 2 (A) every 49.9975 times the reference period 1/fr. However, since PACC2 actually performs digital calculations, an overflow signal is generated every 50 times the reference period.
As shown in b), when <to is the standard, when 11, △t1t,
When 2Δ1,1. In the case of 3Δt, the phase of the overflow signal lags behind the desired phase in FIG. By the way, this phase delay △t is l/f rX5
0-1/f rXNt/Pi=0.2SX10-”(
seconds). This phase delay is accumulated and the reference period 1/
When f r = 100X 10-" (seconds) is reached, overflow signals that previously occurred every 50 times the reference period will now occur at 49 times the reference period. Then, overflow signals will again occur every 50 times the reference period. A signal is generated and the above operation is repeated.In the end, every 50 times the reference period l/fr, 39
An overflow signal is generated 9 times, and 4 of the reference period 1/fr
Since an overflow signal occurs once every 9 times the period, the apparent average is 49.9975 times the reference period (= (5
This means that an overflow signal is generated every 0x399+49x1)/400 times). The average output frequency at this time is 200,010 [Hz]. Now, since the magnitude of the residual data when PACC2 generates an overflow signal is proportional to the magnitude of the phase shift, as mentioned above, the data is applied to the multiplier! 0 and multiplied by the multiplication coefficient Fid, the multiplication result Drs (=DrXFid) is D
As shown in FIG. 3(a), the output voltage of the D/A converter 4 is increased when the residual data is small, and is decreased when the residual data is large.
A control voltage for the voltage-controlled phase shifter 9 is generated. Then,
As mentioned above, the amount of delay that the voltage controlled phase shifter 9 gives to its input pulse is proportional to the control voltage, so it has the characteristics as shown in FIG.

In other words, the delay amount is maximum when the residual data is zero, and the delay amount decreases as the residual data gradually increases.

Here, in FIG. 2, if the residual data is zero at the reference time to and the delay amount is tdo, then the residual data when PACC2 overflows is 500 in a specific example.
(=200,0IOX 5G-10'), and the output phase of the overflow signal is delayed by Δt with respect to the original output phase ti. The remaining data when the next overflow occurs is 1000 (= 200.010x
50-10'+500), and the phase delay of the overflow signal is 2Δt. Similarly, the next residual data is 1500 and the phase delay is 3Δt. Therefore, the relationship between the phase shift amount and the control voltage of the voltage-controlled phase shifter 9, that is, the m control sensitivity K P [Second/V ol
Adjust t and get tdl = tdo - △t (td snow = td
o-2Δt, td3=tdo-3Δt), the phase jitter included in the overflow signal of PACC2 can be canceled. More specifically, the conversion gain of the D/A converter 4 is expressed as K d [V o
lt/bit], Fi・Fid−Kd−
Kd or Kp so that the equation Kp=1/fr holds true.
By setting , the purpose of canceling phase jitter can be achieved.

In Fig. 2, the overflow signal causes a phase shift as shown in Fig. 2 (B) with respect to the originally desired output phase (A), but the output signal finally extracted is as shown in (A). Since only a constant delay tdo is always added to the output phase of (a) and the phase delay Δt is not accumulated as in (a), no phase jitter occurs.

(Effects of the Invention) As explained above, according to the present invention, in order to cancel the phase jitter included in the PACC overflow signal,
Since the circuit operates to change the amount of delay given to the overflow signal according to the residual data of the PACC when an overflow occurs and the frequency setting value, there are various advantages described below.

(a) The effect of reducing phase jitter is significant.

(b) Since the Nt/Fi ratio is not necessarily limited to a large range, the output frequency can be used over a wide range.

(c) Since it is not necessary to divide the output signal before use, the output frequency does not decrease.

(d) The low-pass filter 5 shown in FIG. 6 is an essential component for removing the reference frequency component and reducing phase jitter, and the response speed during frequency switching mainly depends on the characteristics of the low-pass filter. However, since the present invention does not require a corresponding low-pass filter, it is possible to fully utilize the high-speed response characteristics that are the original characteristics of a direct synthesis frequency synthesizer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIGS. 2 to 5 are explanatory diagrams of the operation of FIG. 1E, FIG. 6 is a block diagram of a conventional direct synthesis frequency synthesizer, and FIG. FIG. 6 shows an operating waveform diagram, FIG. 8 shows a specific example of a phase accumulator, and FIG. 9 shows a second example of a conventional direct synthesis frequency synthesizer. IA...Frequency setting circuit, 2...Phase accumulator, 4...D/A converter, 6...Reference oscillator,
7... Pulse synchronizer, 8... Residual data memory, 9... Voltage controlled phase shifter, lO... Multiplier. Patent applicant: Japan Radio Co., Ltd. Tsuta 4, 5, 8

Claims (2)

[Claims] (1) A reference oscillator, a phase accumulator that accumulates phase information for each cycle of the oscillation output, a residual data memory that extracts and stores residual data when the phase accumulator overflows, and a desired output frequency. a frequency setting circuit that provides a frequency setting value to be set to a value to the phase accumulator and outputs a multiplication coefficient calculated from the frequency setting value; a multiplier that receives a coefficient as a second input; a D/A converter that receives the multiplier output and converts it into a voltage; and a D/A converter that synchronizes the overflow signal with the output of the reference oscillator to generate a signal with a constant pulse width. It consists of a pulse synchronizer that outputs, and a voltage controlled phase shifter that takes the output as an input and the output of the D/A converter as a control input, and applies it to the overflow signal of the phase accumulator according to the residual data and frequency setting value. A frequency synthesizer characterized by varying the amount of delay. (2) The frequency setting value is Fi [bit], the multiplication coefficient given to the second input of the multiplier is Fid, the conversion gain of the D/A converter is Kd [Volt/bit], and the voltage controlled phase shifter is The control sensitivity of Kp[Second/vo
lt], and when the output frequency of the reference oscillator is fr [Hz], substantially Fi・Fid・Kd・Kp=1/fr
2. The frequency synthesizer according to claim 1, wherein the frequency synthesizer is configured such that the following equation holds true.