GB2150775A - Frequency synthesiser - Google Patents

Abstract

A frequency synthesiser of the phase-locked loop, fractional-n type, with means 8,9 for modifying the division ratio 'n' of variable divider 7 to a non-integer average value, includes a phase modulator 10 via which either the reference signal f@ or the feedback signal Q@ is fed to the phase detector 4, and a wave-form generator 11 responsive to the division ratio modifying means for producing a modulation signal which is received by the modulator, to modulate the signal applied thereform to the phase detector, thereby substantially to cancel phase jitter. Converter 11 generates a staircase wave-form. The modulator 10 is in the form of a D-type flip-flop set by f@ and reset when a ramp reaches equality with the staircase waveform, so that the output pulses have trailing edges which are jittered in accordance with the staircase waveform. <IMAGE>

Description

SPECIFICATION Synthesiser This invention relates to digital frequency synthesisers.

A basic digital frequency synthesiser comprises a variable frequency oscillator (VFO), which provides an output signal the frequency of which is set by a control signal produced by a phase detector in dependence upon the phase relationship between a reference signal and a feedback signal derived from the output signal via a variable divider, whereby the frequency of the output signal is determined by a division ration 'n' to which the variable divider is set.

The basic digital frequency synthesiser provides an output signal the frequency of which is variable in frequency steps the size of which cannot be smaller than the reference frequency. Also the settling time of the synthesiser is dependent upon its reference frequency and bandwidth and is thus constrained for a given frequency step size.

If a fast settling speed is required, together with frequency steps which are smaller than the reference frequency a reference frequency and bandwidth which is chosen affords the settling speed desired. The basic frequency synthesiser is then modified by the use of a fractional-n technique so as to provide frequency steps smaller than the reference frequency. The fractional-n technique involves varying the ratio 'n' to which the variable divider is set, whereby a non-integer mean division ratio is achieved which will afford the frequency step required.

Fractional-n techniques however, have the disadvantage that they introduce a new problem, namely the generation of spurious frequencies resulting from jitter which is produced as the division ratio is varied. This results in unwanted sidebands on the output signal. It is known to provide jitter cancellation circuits but hitherto such circuits have been less than ideal with the result that spurious signals at an undesirably high level may be present in the output signal.

It is an object of the present invention to provide a digital frequency synthesiser of the fractional-n type including means for effecting efficient jitter cancellation.

According to the present invention a digital frequency synthesiser of the fractional-n type comprises a VFO which provides an output signal the frequency of which is set by a control signal produced by a phase detector in dependence upon the phase relationship between a reference signal and a feedback signal derived from the output signal via a variable divider. The frequency of the output signal is determined by a division ratio 'n' to which the variable divider is set. Also included are division ratio modifying means which modify the division ratio 'n' to a non-integer value, whereby frequency steps are produced which are smaller than the reference signal frequency and whereby unwanted jitter is accordingly produced. The synthesiser includes a modulator via which either the reference signal or the feedback signal is fed to the phase detector.A wave-form generator responsive to the division ratio modifying means produces a modulation signal which is received by the modulator. This modulates the signal applied to the phase detector, thereby cancelling the unwanted jitter.

The modulator consists of a flip-flop triggered by the reference signal or the feedback signal, as the case may be, to produce a trigger signal which is used to operate a switch and a current source. Also a capacitor which is charged from the current source consequent upon operation of the switch, a comparator responsive to the relative amplitudes of the charge on the capacitor and the modulation signal, which is used to reset the flip-flop whereby the flip-flop is constrained to provide an input signal for the phase detector, which is phase modulated so as to effect jitter cancellation.

The modulator may comprise differential amplifier means for controlling the current source in dependence upon a combination of the reference signal or the feedback signal as the case may be, and the output from the flip-flop, whereby operation of the modulator is stabilised.

One embodiment of the invention will now be described solely by way of example with reference to the accompanying drawings in which: Figure lisa generally schematic block diagram of a frequency synthesiser; Figure 2 is a somewhat schematic block circuit diagram of a modulator for use with the synthesiser shown in Figure 1; Figure 3 is a wave-form diagram appertaining to operation of the modulator shown in Figure 2; and, Figure 4 is a somewhat schematic block diagram of a modulator which is similar to the modulator shown in Figure 2 but which includes a stabilisation circuit.

Referring now to Figure 1, a synthesiser comprises a VFO 1 which provides an output frequency signal on a line 2 and which is controlled by means of a control signal fed on a line 3 from a phase detector 4 via a filter 5. The phase detector 4 is fed with a reference frequency from a reference frequency source 6 and with a feedback signal derived from the VFO 1 via a variable divider 7.

In order to achieve fast frequency setting a relatively high reference frequency fr, is used and accordingly to achieve frequency switching in steps which are smaller than the reference frequency fr a fractional-n technique is applied to modify the division ratio of the variable divider 7 so that the average effective division ratio is a non-integer value. The division ratio of the variable divider 7 is modified by means of an adder 8 which is effective to add pulses internally to the divider 7 whereby its division ratio is modified as required. The adder 8 is operated under the control of an arithmetic computer unit 9 which determines the least significant digits of the output frequency and an integral control 8a which determines the more significant digits.Operation of the variable divider 7, to achieve non-integer division ratios, as required by the fractional-n technique is well known and since the technique is not central to the present invention no further explanation of its operation is believed to be necessary.

Because the division ratio afforded by the variable divider 7 is varied, pulses fed from the variable divider 7 to the phase detector 4 tend to arrive irregularly. This irregularity or jitter gives rise to unwanted sidebands in the output signal on the line 2 and accordingly a modulator 10 is provided which operates as will in hereinafter be described for jitter cancellation purposes. In the present example, the modulator 10 is used to modulate the reference frequency fr fed to the phase detector 4 from the reference frequency generator 6 with a signal derived from 22, so as to cancel the jitter fed from the divider 7 to the phase detector 4. In an alternative embodiment the modulator 10 may be connected between the variable divider 7 and the phase detector 4. The modulator 10 is fed with a modulation signal from the arithmetic unit 9 via a digital to analogue converter 11.This modulating signal comprises a staircase wave-form the amplitude changes in which correspond to the phase changes which constitute the jitter. The staircase wave-form is fed from the digital to analogue converter 11 to the modulator 10 and the amplitude changes in the staircase wave-form are converted back to corresponding phase changes in the modulator 10 which are therefore effective to cancel the jitter in the phase detector 4.

The modulator 10 comprises a D-type flip-flop 12 to which the reference frequency is applied on an input line 13. The Q output of the D-type flip-flop 12 is fed via a resistor 14 to a transistor switch 15. The transistor switch 15 is shunted by a capacitor 16 which is charged under control of the switch 15 from a current source comprising a transistor 17 and a resistor 18. The D-type flip-flop 12 is reset by a signal on a line 19 from a comparator 20 which is responsive to the charge on the capacitor 16 which is present on a line 21 coupled to the capacitor 16, and to the staircase wave-form fed thereto on a line 22 from the digital to analogue converter 11.The staircase wave-form on the line 22 is used to phase modulate the reference frequency applied on the line 13 and a modulated output signal is produced on a line 23 from the Terminal of the D-type flipflop 12.

In operation of the modulator 10, assuming that the Q output is initially '0', that the transistor 15 is initiaily 'ON', and that the signal level on the line 21 is '0'; when the reference frequency on the input line 13 goes from '0' to '1' the Q output will rise from '0' to '1' and be applied via the resistor 14to switch the transistor 15 'OFF'. The capacitor 16 will then start to charge from the current source comprising the transistor 17 and when the voltage on the line 21 corresponds to the voltage of the staircase wave form on the line 22, the comparator 20 will produce a '1' output on the line 19 which will reset the D-type flip-flop 12.

As can be seen from Figure 3, with a reference frequency inputwave4orm 'A' on the line 13, a corresponding output signal 'B' will be produced on the Qterminal of the D-type flip-flop 12. The wave form B operates the transistor switch 15 so as to allow across the capacitor 12 a ramp wave-form C.

The ramp wave-form C is reset each time the charge voltage on the line 21 corresponds to the voltage of the staircase wave-form on the line 22. The reset voltage is shown in wave-form D and the staircase wave-form on the line 22 is shown in a wave-form E.

Thus since the control voltage amplitude rises in steps, the instant at which the trailing edges of the pulses comprising the wave-form B occur, varies correspondingly. Thus the trailing edge of the pulses on the wave-form 'B' is jittered in accordance with the staircase wave-form applied to the comparator 20 via the line 22. The output signal on an output line 23 is taken from the Q output terminal of the D-type flip-flop 12 and applied to the phase detector 4.

It will be appreciated that any variation with temperature of the capacitance of the capacitor 16 or Vbe of the transistor 17 will significantly affect efficient operation of the circuit. Feedback is therefore provided in order to temperature stabilise operation of the modulator and a stabilising feedback circuit will now be described with reference to Figure 3, wherein parts corresponding to Figure 2 bear the same numerical designations.

The circuit comprises a resistive potentiometer means comprising resistors 24 and 25 connected between the input line 13 and the output line 23. If the supply voltage on the line 26 isV5, it can be seen that pulses on the input line 13 and the output line 23 both go from 0 to V5. The junction 33 is coupled to a differential amplifier 27 which is fed also with a reference voltage equivalent to Us/2. The differential amplifier 27 is shunted by a capacitor 28 and arranged to feed the transistor 17 of the current source via a resistor 29. The bias voltage of the transistor 17 is set by means of resistors 30 and 31.

The circuit operates in effect to make constant the mean period of the pulses in the wave-form B.

Conveniently the input signal from the reference frequency source 6, has a 1:1 mark/space ratio and input and output signals go from 0 to V5 as hereinbefore mentioned. If the resistors 24 and 25 are made equal then the mean value of the voltage at the junction 26 should be V5/2 which corresponds to the value V5/2 on the line 32 which feeds the differential amplifier 27. Thus it will be appreciated that the system is stable when the mean mark space ratio of the output is 1:1. If the '1' period of the output tends to increase, the output from the differential amplifier 27 tends to fall thereby decreasing the charging current for the capacitor 16 and lengthening the time needed for the capacitor 16to ramp down towards the collectorvoltage of the transistor 17. Thus the Q output of the D-type flip-flop 12 spends less time at '1' and the output on the line 23 spends less time at '1'. The capacitor 28 is chosen so that no significant feedback occurs at the lowest rate at which delay changes must occur. This is usually the smallest step size of the synthesiser. If the current fed from the transistor 17 to the transistor C1 were to fall so low that the output period exceeded the input period, then the feedback would cease to work correctly. Thus the biasing resistors 29, 30 and 31 are included to define a minimum charging current.

Various modifications may be made to the arrangement just before described without departing from the scope of the invention and for example a forward biased diode may be included in series with the resistor 31 to counteract the temperature dependence of the Vbe of the transistor 17 which would otherwise complicate the tolerancing of the circuit which ensures a minimum charging current.

Claims (5)

1. A digital frequency synthesiser of the fractionaln type comprising a VFO which provides an output signal the frequency of which is set by a control signal produced by a phase detector in dependence upon the phase relationship between a reference signal and a feedback signal derived from the output signal via a variable divider, whereby the frequency of the output signal is determined by a division ratio 'n' to which the variable divider is set and including division ratio modifying means effective for modifying the division ratio 'n' to a non-integer value, whereby frequency steps are producable which are smaller than the reference signal frequency and whereby unwanted jitter tends accordingly to be produced, characterised in that the synthesiser includes a modulator via which either the reference signal or the feedback signal is fed to the phase detector, and a wave-form generator responsive to the division ratio modifying means for producing a modulation signal which is received by the modulator, to modulate the signal applied therefrom to the phase detector, thereby substantially to cancel the jitter.

2. A digital frequency synthesiser as claimed in claim 1 wherein the modulator comprises a flip-flop triggered by the reference signal or the feedback signal as the case may be to produce a trigger signal which is used to operate a switch, a current source, capacitor means which is charged from the current source consequent upon operation of the switch, a comparator responsive to the relative amplitudes of the charge on the capacitor means and the modulation signal for producing an output signal which is used to reset the flip-flop whereby the flipflop is constrained to provide an input signal for the phase detector, which is phase modulated so as to effect jitter cancellation.

3. A digital frequency synthesiser as claimed in claim 1 wherein the modulator comprises a differential amplifier means for controlling the current source in dependence upon a combination of the reference signal or the feedback signal as the case may be, and the output from the flip-flop, whereby operation of the modulator is stabilised.

4. A digital frequency synthesiser as claimed in claim 3 wherein the combination of the reference signal or the feedback signal as the case may be and the output from the flip-flop is produced in a potentiometer which provides one of two input signals for the differential amplifier means, the other of the two input signals comprising a reference voltage.

5. A digital frequency synthesiser substantially as herein before described with reference to the accompanying drawings.