JP3417734B2 - Frequency synthesizer and frequency synthesizer method - Google Patents

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial applications Conventional technology (Fig. 6) Problems to be Solved by the Invention (FIG. 7) Means for solving the problem (FIG. 2) Action (Fig. 2) Example (FIGS. 1 to 5) The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer and a frequency synthesizing method, and can be applied to those which generate a high frequency signal whose frequency is stabilized by a PLL (phase locked loop) circuit.

[0003]

2. Description of the Related Art Conventionally, there is a frequency synthesizer of this type that outputs at a frequency that is an integral multiple of the frequency output by a reference oscillator or a frequency with a narrow interval other than the integral multiple. As shown in FIG. 6, the fractional-N synthesizer 1 has a reference frequency signal S output from a reference oscillator 2.
1 is supplied to the phase comparator 3. The phase comparator 3 detects the phase difference between the frequency-divided signal S2 output by the frequency divider 4 having the logic circuit configuration and the reference frequency signal S1, and gives the error signal S3 based on the detected phase difference to the adder 5. .

The adder 5 adds the interpolation signal S4 output from the automatic phase interpolation circuit 6 to the error signal S3, and gives the added error signal S5 to the low-pass filter 7. Low-pass filter 7
Of the error signal S5 blocks the harmonic component of the error signal S5 and supplies the low-frequency component signal S6 to the sample hold circuit 8. The sample-and-hold circuit 8 samples the low-frequency component signal S6 and supplies the voltage-controlled oscillator 9 with a DC signal S7 whose waveform fluctuation is suppressed.
The voltage-controlled oscillator 9 gives an oscillation signal S8 to an output terminal (not shown) and also gives it to the frequency divider 4 and the frequency division control circuit 10 having a logic circuit configuration.

The frequency divider 4 is controlled by the control signal S9 of the frequency division control circuit 10 so that the two frequency division ratios at the time of dividing the oscillation signal S8 of the voltage controlled oscillator 9 alternate in a predetermined cycle. The frequency-divided signal S2 that is switched according to each frequency-division ratio
Is output. These two frequency division ratios are 1 / where N is an integer.
N and 1 / (N + 1). By periodically switching these two frequency division ratios, it is possible to perform frequency division by a so-called decimal point frequency division method in which the frequency division is apparently performed by a frequency division ratio having a rational number obtained by adding a decimal point to an integer as a denominator. The frequency division control circuit 10
The control signal S10 is given to the automatic phase interpolation circuit 5 at every predetermined cycle to output the interpolation signal S4.

As a result, the fractional-N type synthesizer 1 corrects the phase error detected by the phase comparator 3 with the interpolation signal S4 so as to oscillate at a frequency of, for example, (N + 0.5) times the reference frequency. The signal S8 can be output.

[0007]

In the fractional-N synthesizer 1, the interpolation signal S4 generated by the automatic phase interpolation circuit 6 is generated by the oscillation signal S of the voltage controlled oscillator 8.
It is generated based on only 8. Therefore, the oscillation signal S
A sample and hold circuit 8 is connected after the low-pass filter 7 so that the frequency of 8 is not directly influenced by the fluctuation of the interpolation signal S4 and an unnecessary wave, so-called spurious is not generated.

However, the above-mentioned configuration has a drawback in that the actual configuration is complicated, such as the sample-hold circuit 8 being composed of high-precision parts and the connection of the perfect integrating circuit. Moreover, there is a drawback that the timing control of the sample hold is difficult. Furthermore, the above-mentioned fractional N
In the system synthesizer 1, the automatic phase interpolation circuit 6 is configured as a digital analog converter that converts the control signal S10 into an analog level. Therefore, there is a problem that the configuration of the automatic phase interpolation circuit 6 becomes complicated.

Here, consider a case where the sample and hold circuit 8 is not used and the high frequency signals of a plurality of channels are switched at high speed from the fractional-N synthesizer and taken out. In this case, it is generally necessary to increase the cutoff frequency of the low-pass filter to increase the speed in order to lock the high-frequency signal with the PLL at high speed. In this case, the reference frequency signal may escape to the voltage controlled oscillator and the oscillation signal of the voltage controlled oscillator may be modulated at the reference frequency. Therefore, there is a problem in that it is difficult to switch high frequency signals of a plurality of channels at high speed and to extract them.

On the other hand, instead of canceling the phase error in an analog manner, it is possible to cancel it in a digital manner. For example, as shown in FIG. 7, the first and second selection circuits 12 and 13 that provide the output of the phase comparator control the error signal charge pump 14 to cause a phase error period (hereinafter referred to as an error period). Only, a phase error input / output current of a constant magnitude is generated. The automatic phase interpolation circuit 15 has a third
Also, the correction charge pumps 18 and 19 of the two systems are controlled via the fourth selection circuits 16 and 17 to generate the correction input / output currents in the opposite phase to the error signal charge pump 14.

Here, the correction period by the correction input / output current is set to be larger than the error period so as to always include the error period. Therefore, the respective currents flowing through the input current source and the output current source of the correction charge pumps 18 and 19 are very small values (for example, 2.06 [μA] compared with the phase error input / output current (for example, 1.45 [mA]). ]) Is set.
The input / output current for phase error and the input / output current for correction are wired-added and given to the low-pass filter 7. By doing so, the values integrated by the low-pass filter 7 within the correction period become equal, and the error signal S3 that causes phase fluctuation is generated.
Are offset.

Incidentally, the error period and the order of magnitude of the error period change according to the decimal point frequency division value. For this reason, the correction charge pumps 18 and 19 are arbitrarily combined when generating the required correction input / output current.
An input current source or an output current source is selected for the error signal charge pump 14 and the correction charge pumps 18 and 19 depending on whether the low-pass filter 7 is a passive type or an active type.

However, with the above-mentioned configuration, it is difficult to generate an accurate and minute correction signal of high frequency at high speed. Therefore, there is a problem that the phase error cannot be corrected at high speed.

The present invention has been made in consideration of the above points, and when the oscillation outputs of a plurality of frequencies are switched and output at high speed, generation of unnecessary waves is suppressed with a simple structure, and each frequency is increased. The present invention is intended to propose a frequency synthesizer and a frequency synthesizer method capable of PLL locking.

[0015]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a voltage control oscillator and a voltage control by a frequency division ratio 1 / N or 1 / (N + 1) where N is an arbitrary integer. Frequency dividing means for dividing the oscillation output of the oscillator, reference signal generating means for generating a reference frequency signal, phase difference detecting means for detecting a phase difference between the frequency signal and the divided output of the frequency dividing means, A correction output generation unit that generates a correction output that corrects the detection output in a phase opposite to the detection output of the phase difference detection unit and the frequency division ratio of the frequency division unit are cyclically 1 / N or 1 / (N +
In the frequency synthesizer, the first control means for controlling 1), the addition means for adding the detection output and the correction output, and the filter means for converting the addition output of the addition means into a DC voltage and providing the voltage control oscillator with the correction output are generated. Means to the first
A first current source for flowing a current and a second current source connected in series with the first current source for flowing a second current, and the correction output of the first current and the second current is provided. Generate from the difference.

Further, according to the present invention, the frequency division ratios 1 / N and 1 / (N + 1), where N is an arbitrary integer, are periodically controlled to divide the oscillation output of the voltage controlled oscillator. ,
A phase difference detection process that detects the phase difference between the reference frequency signal and the frequency division output obtained by the frequency division process, and a correction output that corrects the detection output with the opposite phase to the detection output obtained by the phase difference detection process. In accordance with the correction output generation process for generation, the addition process for adding the detection output and the correction output, and the addition output obtained by the addition process,
In a frequency synthesis method for generating an oscillation output by a DC conversion process for generating a DC component that controls the frequency of the oscillation output of the voltage controlled oscillator,
The second current source connected in series with the first current source, and the correction output from the difference between the first current and the second current. To generate.

[0017]

A dark current sufficiently larger than the correction output is simultaneously passed through the first current source and the second current source connected in series to the dark current, and the current of the first current source and the second current source are simultaneously supplied. By generating the correction output at a high speed from the difference between the current and the current, the output of oscillating outputs of a plurality of frequencies can be switched at a high speed, and the unnecessary wave can be suppressed with a simple configuration and each frequency can be locked at a high speed. Can be made.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1 in which parts corresponding to those in FIG. 6 are designated by the same reference numerals, numeral 21 indicates a fractional-N type synthesizer for generating a plurality of high-frequency signals which are used as the carrier frequency of the communication device as a whole. Fractional
When generating a high-frequency signal of a plurality of channels, the N-system synthesizer 21 has a frequency signal output from a reference signal generation means, for example, a reference oscillator 2, for example, an integral multiple frequency of the reference frequency signal S1 or a frequency with a narrow interval other than the integral multiple. , And each frequency is locked by the PLL.

Fractional N-type synthesizer 21
The sample hold circuit 8 is omitted from the configuration of the conventional fractional-N synthesizer 1. Further, the fractional-N system synthesizer 21 is provided with a correction output generation means, for example, an automatic phase interpolation circuit 22 and a second control means, for example, a pulse width control circuit 23, instead of the conventional automatic phase interpolation circuit 6. ing.

The reference oscillator 2 is a TCXO (Temperature
Compensated Crystal Oscillator, temperature-compensated crystal oscillator) and other high-precision oscillators are used. The reference oscillator 2 divides the output of the TCXO to generate a reference frequency signal S1 having an accurate period, and supplies this reference frequency signal S1 to a phase difference detecting means, for example, a phase comparator 3. The phase comparator 3 uses the reference frequency signal S of the reference oscillator 2.
1 and the frequency division means, for example, the frequency division output of the frequency divider 4, for example, the phase of the frequency division signal S2 is compared to detect the phase difference, and the detection output is a rectangular wave whose period is different according to the detected phase difference. , For example, the error signal S3 is given to the adding means, for example, the adder 5.

On the other hand, the reference oscillator 2 supplies the pulse width control circuit 23 with the reference frequency signal S11 generated by dividing the output of the TCXO. The pulse width control circuit 23 has a logic circuit configuration, generates a pulse width control signal S12 having an accurate width (that is, a period) and timing according to the reference frequency signal S11, and supplies it to the automatic phase interpolation circuit 22. In the automatic phase interpolation circuit 22, the size is set by the control signal S10, and the correction period is the pulse width control signal S12.
The correction output of a rectangular wave set accurately according to, for example, a correction signal S13 is generated, and this correction signal S13 is added to the adder 5
Give to.

The adder 5 receives the error signal S3 from the phase comparator 3.
And the interpolation signal S13 of the automatic phase interpolation circuit 22 are added, and the addition output, for example, the error signal S14 is added to the filter means,
For example, it is given to the low-pass filter 7. The low-pass filter 7 removes the harmonic component of the error signal S14 of the adder 5 and supplies the low-frequency component signal S6 to the voltage controlled oscillator 9. This low pass filter 7 determines the response of the PLL.

The first control means, for example, the frequency division control circuit 10, to which the oscillation output of the voltage controlled oscillator 9, for example, the oscillation signal S8 is provided, is composed of an adder and a latch. The frequency division control circuit 10 gives the control signal S10 to the automatic phase interpolation circuit 22 so as to eliminate the fluctuation of the phase of the oscillation signal S8 by the decimal point frequency division method. As a result, in the fractional-N synthesizer 21, the PLL repeatedly corrects the phase shift for a short period of time to synchronize the phase of the oscillation signal S8 at high speed.

Here, for example, as shown in FIG. 2, the reference oscillator 2 oscillates at 19.2 [MHz] and divides this by 1.2.
[MHz] reference frequency signal S1 and reference frequency signal S1
1 is generated respectively. The pulse width control circuit 23 gives an output obtained by dividing the reference frequency signal S11 by the counter 25 to the AND circuit 26, and 1 / (1.2 [MHz]) at a period of 1 / (1.2 [MHz]).
Pulse width control signal S12 having a period of (9.6 [MHz])
To generate. The phase comparator 3 is composed of a NAND gate. The output of the NAND gate is given to the first selection circuit 12 and the second selection circuit 13, and the selection circuit 12
And 13 control the error signal charge pump 14.

The error signal charge pump 14 includes a series circuit including a first current source, for example, a charge pump current source and an input switch, which is interposed between a first power source and an output end, an output end and a second end. A second current source, for example, a current source for a charge pump and a series circuit including an output switch. The error signal charge pump 14 selects the input switch or the output switch for a period corresponding to the output of the phase comparator 3 to select the circuit 12 or 13.
To open and close to generate a rectangular wave current, and the rectangular wave current is output to the output terminal as an error signal S3.

The frequency division control circuit 10 generates a control signal S10 with the latch 27, the adder 28 and the latch 29, and supplies the control signal S10 to the automatic phase interpolation circuit 22. The automatic phase interpolation circuit 22 generates a correction current having a magnitude corresponding to the control signal S10 and outputs the correction current to the adder 5 as a correction signal S13 to generate an error signal S3 that causes a phase fluctuation.
To offset. The automatic phase interpolation circuit 22 determines the magnitude of this correction current from the correction charge pumps 31 to 31 of the first to fourth systems.
34.

Correction charge pumps 3 for the first to fourth systems
Reference numerals 1 to 34 denote series circuits of a charge pump current source and an input switch, which are inserted between the first power source and the output terminal, and a charge pump, which is inserted between the output terminal and the second power source. It is composed of a current source and a series circuit including an output switch. Correction charge pumps 31-34
Causes a dark current to flow through the respective current sources, resulting in an error signal S3
When canceling, the input switch and the output switch are turned on at the same time. As a result, a difference current between the current of the charge pump current source on the first power supply side and the current of the charge pump current source on the second power supply side is generated as an input current or an output current.

That is, in the correction charge pumps 31 and 33 of the first and third systems, the current source for the charge pump on the second power source side supplies a smaller current than the current source for the charge pump on the first power source side. Generate the input current. The correction charge pumps 32 and 34 of the second and fourth systems are the second
The current source for the charge pump on the power source side supplies a larger current than the current source for the charge pump on the first power source side to generate the output current. Further, the correction charge pumps 33 and 34 of the third and fourth systems generate twice as much input current or output current as compared with the correction charge pumps 31 and 32 of the first and second systems.

The automatic phase interpolation circuit 22 includes the first and third correction charge pumps 31 and 33, or the second and fourth correction charge pumps 31 and 33.
The charge pumps 32 and 34 are selectively combined in a predetermined cycle. Accordingly, the correction signal S13 including the input current or the output current having the correction current and the correction period according to the presence or absence and the magnitude of the phase difference is generated.

Each of the correction charge pumps 31 to 34 is constructed as shown in FIG. That is, the diode-connected NPN-type transistor Q1 is configured as NPN-type transistors Q2 to Q4 and a current mirror constant current source, for example, 20 [μA], 20 [μA], and 20 [μA], respectively.
Flow 80 [μA] and 40 [μA].

The transistor Q2 is connected to the power supply voltage V _CC via a diode-connected PNP transistor Q5 and a resistor R9. PNP transistor Q6
Is composed of a transistor Q5 and a current mirror constant current source, and supplies a constant current of 40 μA to the PNP type transistors Q7 and Q8 of the differential pair. The collectors of the transistors Q7 and Q8 are diode-connected NPN.
Are connected to the ground line via transistors Q9 and Q10, and the transistors Q9 and Q are connected to the bases via input terminals INP and INM.
Turn 10 on and off.

The transistor Q9 is formed of NPN type transistors Q11 and Q12 and a current mirror constant current source. The transistors Q3 and Q11 are respectively supplied with a constant current of 80 [μA] by a current mirror constant current source composed of PNP transistors Q13 and Q14. The transistors Q4 and Q12 are respectively supplied with a constant current of 40 [μA] by a current mirror constant current source composed of PNP type transistors Q15 and Q16.

The constant current of the transistor Q14 flows to the transistor Q11 when the transistor Q11 is on, and the NPN transistor Q when the transistor Q11 is off.
17 and the diode-connected NPN transistor Q18. In this way, the current values of the transistors Q17 and Q18 are
With the constant current of 14 as the reference, the transistor Q11 turns on,
Turned off.

The constant current of the transistor Q16 flows to the transistor Q12 when the transistor Q12 is on, and the NPN transistor Q when the transistor Q12 is off.
19 and a diode-connected NPN transistor Q20. Thus, the current values of the transistors Q19 and Q20 are
With the constant current of 16 as the reference, the transistor Q12 turns on,
Turned off.

When the reference value of the input / output current of the error signal charge pump 14 is set to, for example, 1.45 [mA], the charge pumps 31 to 34 are connected to the transistors Q19 and Q20.
The total value of the emitter current due to is set to 80 [μA]. In the charge pumps 31 to 34, the collector current of the transistor Q17 is (80-2.06) [μA],
(80 + 2.06) [μA], (80-4.13) [μA] and (80
+4.13) [μA]. This allows
The charge pumps 31 to 34 have an input current of 2.06 [μA],
An output current of −2.06 [μA], an input current of 4.13 [μA], and an output current of −4.13 [μA] are generated and output at the midpoint of connection between the common emitter of the transistors Q19 and Q20 and the transistor Q17, respectively.

The adder 5 is the error signal charge pump 1
4 and the currents output from the correction charge pumps 31 to 34 are wired-added and given to the low-pass filter 7.
For the low-pass filter 7, a passive circuit or an active circuit is arbitrarily selected. The voltage controlled oscillator 9 is controlled so as to oscillate in the 1.6 [GHz] band. The automatic phase interpolation circuit 22 resets each circuit by the reset circuit 37.

Incidentally, the input switch and the output switch of the error signal charge pump 14 are controlled by the first and second selection circuits 12 and 13 in accordance with a passive circuit or an active circuit arbitrarily selected by the low-pass filter 7. , One switch is used. Similarly, the input switches and the output switches of the correction charge pumps 31 to 34 of the first to fourth systems are controlled by AND circuits 39 and 40, respectively.
And by the fourth selection circuits 16 and 17, depending on the passive circuit or active circuit arbitrarily selected by the low-pass filter 7,
One switch is used.

In the above configuration, the frequency divider 4 is set to 1376 as the integer N of the frequency division count value, and the oscillation signal S8 is divided into N + (1/4) and N + (1/2), respectively. , N
+ (3/4) frequency division and N + (0/4) frequency division, voltage controlled oscillator 9
It is assumed that the oscillation frequency of is locked by the PLL according to each frequency division ratio and is stable. Further, among the correction charge pumps 31 to 34, the correction charge pumps 32 and 3 are used.
4 is selected and combined.

First, when dividing by N + (1/4), FIG.
As shown in, at time t ₀ , the reference frequency signal S1
When the phase of the divided signal S2 and the phase of the divided signal S2 match, the error signal S3 of the phase comparator 3 becomes zero. Further, as shown in FIG. 4B, in the automatic phase interpolation circuit 22, the correction charge pumps 32 and 34 are opened to set the correction signal S13 to 0. Further, as shown in FIG. 4C, at this time t ₀ , the frequency division count value is switched from N + 1 to N.

Then, from time t ₀ , the period 1 / (1.2 [MHz
]) At the time t ₁ that has elapsed only, the desired N + (1 /
4) Since the frequency divider 4 finishes counting 1/4 frequency earlier than the frequency division, a phase shift of 1/4 frequency occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a rectangular wave error signal S3 corresponding to the shift of 1/4 frequency division. As shown in FIG. 4 (A), the error signal S3 at this time is displayed as a rectangle having an area A ₁ in which the magnitude and duration of the current correspond to the height and width on the paper surface, respectively.

On the other hand, shortly before time t ₁ , the automatic phase interpolation circuit 22 outputs a rectangular wave correction signal S13 whose magnitude is determined only by the correction charge pump 32. The correction period by the correction signal S13 is, for example, 1 / (9.6 [MHz]) centering on the time t ₁ . As shown in FIG. 4 (B),
The correction signal S13 at this time is displayed as a rectangle having an area A ₁ in which the magnitude of the current and the duration 1 / (9.6 [MHz]) correspond to the height and width on the paper.

When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz])
Becomes 0, and PL is divided by N + (1/4).
It means that you have locked L. Incidentally, S shown in the figure
Is a portion of the charge pump current that is canceled as a dark current.

Then, from time t ₁ , the period 1 / (1.2 [MHz
]) At time t ₂ has elapsed only by 1/2-divided partial fast divider 4 has finished counting, 1/2 frequency division of the phase shift occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a square wave error signal S3 corresponding to the shift of 1/2 frequency division. As shown in FIG.
The error signal S3 at this time is displayed as a rectangle having an area of 2A ₁ .

On the other hand, just before time t ₂ , the automatic phase interpolation circuit 22 outputs a rectangular wave correction signal S13 whose magnitude is determined only by the correction charge pump 34. The correction period by the correction signal S13 is 1 / centered around the time t _2.
(9.6 [MHz]). As shown in FIG. 4B, the correction signal S13 at this time is displayed as a rectangle having an area of 2A ₁ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz]) becomes
It becomes substantially zero.

Subsequently, from time t ₂ , the period 1 / (1.2 [MHz
]) At time t ₃ when has elapsed, 3/4 min rotations of fast frequency divider 4 by finishes counting, 3/4 frequency division of the phase shift occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a rectangular wave error signal S3 corresponding to the shift of 3/4 frequency division. As shown in FIG.
The error signal S3 at this time is displayed as a rectangle having an area of 3A ₁ . Further, as shown in FIG. 4C, this time t ₃
In, the frequency division count value is switched from N to N + 1.

On the other hand, shortly before time t ₃ , the automatic phase interpolation circuit 22 has the size of the correction charge pumps 32 and 3 for correction.
The correction signal S13 having a rectangular wave determined by 4 is output. The correction period by the correction signal S13 is about the time t ₃
It becomes 1 / (9.6 [MHz]). As shown in FIG. 4B, the correction signal S13 at this time is displayed as a rectangle having an area of 3A ₁ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz])
Is substantially 0.

Then, from time t ₃ , the period 1 / (1.2 [MHz
]) At time t ₄ , the phases of the reference frequency signal S1 and the frequency-divided signal S2 match, the error signal S3 of the phase comparator 3 becomes 0, and the error signal S14 becomes equal to that at time t _0. It becomes 0. Thus the period 1 / (1.2
[MHz]) 4 times the period, that is, period 1 / (300 [KHz])
The above operation is repeated with 1 cycle as the cycle, and the voltage controlled oscillator 9 can output the oscillation signal S8 which is PLL locked to a frequency higher by 300 [KHZ] than the center frequency. Further, the waveform areas of the error signal S3 and the correction signal S13 are set to be the same and cancel each other, and the timings of canceling each other are substantially the same, so that generation of an unnecessary wave applied to the voltage controlled oscillator 9 can be further reduced.

Next, when dividing by N + (1/2),
As shown in (D), when the phases of the reference frequency signal S1 and the divided signal S2 match at time t ₀ , the phase comparator 3
The error signal S3 of is 0. Further, as shown in FIG. 4 (E), the automatic phase interpolation circuit 22 includes a correction charge pump 3
2 and 34 are opened, and the correction signal S13 is set to 0.
Further, as shown in FIG. 4 (F), at this time t ₀ , the frequency division count value is switched from N + 1 to N.

Subsequently, at time t ₁ , desired N +
(1/2) When the frequency divider 4 finishes counting by 1/2 the division earlier than the division, a phase shift of 1/2 division occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a square wave error signal S3 corresponding to the shift of 1/2 frequency division. As shown in FIG. 4D, the error signal S3 at this time is displayed as a rectangle having an area of 2A ₂ . Further, as shown in FIG. 4 (F), at this time t ₁ , the frequency division count value is switched from N to N + 1.

On the other hand, just before time t ₁ , the automatic phase interpolation circuit 22 outputs a rectangular wave correction signal S13 whose magnitude is determined only by the correction charge pump 34. The correction period by the correction signal S13 is 1 / centered around the time t _1.
(9.6 [MHz]). As shown in FIG. 4 (E), the correction signal S13 at this time is displayed as a rectangle having an area of 2A ₂ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz]) becomes
It is substantially 0, which means that the PLL is locked in a state of being divided by N + (1/2).

Then, at time t ₂ , the phases of the reference frequency signal S1 and the frequency-divided signal S2 match, and the phase comparator 3
The error signal S3 of is 0. As a result, the PLL is locked in the state of being divided by N + (1/2). Further, as shown in FIG. 4 (F), at this time t ₂ , the frequency division count value is switched from N + 1 to N.

Subsequently, the operation at time t ₃ is the same as at time t ₁ described above. Subsequently, the operation at time t ₄ is the same as at time t ₀ described above. As a result, the PLL is locked in the state of being divided by N + (1/2). Thus the period 1 / (1.2
[MHz]) twice the period, that is, period 1 / (600 [KHz])
The above operation is repeated with 1 cycle as the cycle, and the voltage controlled oscillator 9 can output the oscillation signal S8 that is PLL locked to a frequency higher by 600 [KHZ] than the center frequency.

Next, when dividing by N + (3/4),
As shown in (A), when the phases of the reference frequency signal S1 and the divided signal S2 match at time t ₀ , the phase comparator 3
The error signal S3 of is 0. Further, as shown in FIG. 5 (B), the automatic phase interpolation circuit 22 includes a correction charge pump 3
2 and 34 are opened, and the correction signal S13 is set to 0.
Further, as shown in FIG. 5C, at this time t ₀ , the frequency division count value is switched from N + 1 to N.

Subsequently, at time t ₁ , desired N +
(3/4) When the frequency divider 4 finishes counting 3/4 earlier than the frequency division, a phase shift of 3/4 frequency division occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a rectangular wave error signal S3 corresponding to the shift of 3/4 frequency division. As shown in FIG. 5A, the error signal S3 at this time is displayed as a rectangle having an area of 3A ₃ . Further, as shown in FIG. 5C, at this time t ₁ , the frequency division count value is switched from N to N + 1.

On the other hand, just before the time t ₁ , the automatic phase interpolation circuit 22 has the size of the correction charge pumps 32 and 3 for correction.
The correction signal S13 having a rectangular wave determined by 4 is output. The correction period based on the correction signal S13 is centered on the time t _1.
It becomes 1 / (9.6 [MHz]). As shown in FIG. 5B, the correction signal S13 at this time is displayed as a rectangle having an area of 3A ₃ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz])
Becomes 0, and PL is divided by N + (3/4).
It means that you have locked L.

Subsequently, at time t ₂ , the frequency divider 4 finishes counting earlier by 1/2 frequency division, resulting in a phase shift of 1/2 frequency division. Therefore, the phase comparator 3 detects this phase shift and outputs a square wave error signal S3 corresponding to the shift of 1/2 frequency division. As shown in FIG. 5A, the error signal S3 at this time is displayed as a rectangle with an area of 2A ₃ .

On the other hand, just before time t ₂ , the automatic phase interpolation circuit 22 outputs a rectangular wave correction signal S13 whose magnitude is determined only by the correction charge pump 34. The correction period by the correction signal S13 is 1 / centered around the time t _2.
(9.6 [MHz]). As shown in FIG. 5B, the correction signal S13 at this time is displayed as a rectangle with an area of 2A ₃ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz]) becomes
It becomes substantially zero.

Then, at time t ₃ , the frequency divider 4 finishes counting 1/4 frequency earlier, and a phase shift of 1/4 frequency occurs. Therefore, the phase comparator 3 detects this phase shift and outputs a rectangular wave error signal S3 corresponding to the shift of 1/4 frequency division. As shown in FIG. 5A, the error signal S3 at this time is displayed as a rectangle having an area A ₃ .

On the other hand, just before time t ₃ , the automatic phase interpolation circuit 22 outputs a rectangular wave correction signal S13 whose magnitude is determined only by the correction charge pump 32. The correction period by the correction signal S13 is 1 about the time t ₃ /
(9.6 [MHz]). As shown in FIG. 5B, the correction signal S13 at this time is displayed as a rectangle having an area A ₁ . When the error signal S3 and the correction signal S13 are added, the error signal S14 in the period of 1 / (9.6 [MHz]) becomes substantially zero.

Subsequently, from time t ₃ , the period 1 / (1.2 [MHz
]) At time t ₄ , the phases of the reference frequency signal S1 and the frequency-divided signal S2 match, the error signal S3 of the phase comparator 3 becomes 0, and the error signal S14 becomes equal to that at time t _0. It becomes 0. Thus the period 1 / (1.2
The above operation is repeated with a period of four times [MHz]) as one cycle, and the voltage controlled oscillator 9 generates the oscillation signal S8 which is PLL locked to a frequency higher by 900 [KHZ] than the center frequency. Can be output.

Next, when dividing by N + (0/4),
As shown in (D) to (F), by dividing by the integer N, the error signal S3 of the phase comparator 3 becomes zero. As a result, the voltage-controlled oscillator 9 has a frequency P that is a multiple of the integer N.
It is possible to output the LL-locked oscillation signal S8.

In this way, when generating the correction current as the correction signal S13, a dark current of, for example, 10 times or more compared with the correction current is supplied to the charge pumps of the first and second power sources of the charge pumps 31 to 34. The correction signal S13 is generated at a high speed every period 1 / (1.2 [MHz]) by simultaneously flowing to the current source, and the error signal S3 can be corrected more accurately. As a result, the generation of unnecessary waves can be effectively reduced, and the error signal S3 can be corrected more accurately.

N + (1/4) division, N + (1/2) division, N
Phase error is detected and corrected in 1 / (300 [KHz]), which is one period common to + (3/4) frequency division and N + (0/4) frequency division, and P
In addition to LL locking, a period of 1/4 period 1 /
It is possible to detect and correct the phase error by adjusting the correction timing every (1.2 [MHz]) and to lock the PLL. This allows
When switching the oscillation signals S8 of multiple channels at high speed, the frequency of each channel can be increased more quickly.
It will be possible to output after L lock.

According to the above configuration, a dark current sufficiently larger than the correction current is supplied to the charge pump current source on the first power source side of the charge pumps 31 to 34 and the second power source side connected in series thereto. A plurality of correction signals S13 are simultaneously supplied to the charge pump current source and the correction signal S13 is generated at high speed from the difference between the current of the charge pump current source on the first power supply side and the current of the charge pump current source on the second power supply side. When switching and outputting the high frequency signal of the channel at high speed,
Generation of unnecessary waves can be suppressed with a simple configuration, and each frequency can be PLL locked at high speed.

Further, the automatic phase interpolation circuit 22 can be simply constructed. Further, the sample and hold circuit 8 is not necessary, and the whole structure can be simplified.

In the above-described embodiment, the case where a high frequency signal for a carrier frequency of a communication device is generated for a plurality of channels has been described, but the present invention is not limited to this, and a signal for an arbitrary frequency is generated for a plurality of channels. It can be widely applied when Also in this case, the same effect as described above can be obtained.

In the above-described embodiment, the case where the frequency between multiples of N is divided into four has been described, but the present invention is not limited to this, and the frequency between multiples of N is divided into three. It can also be applied to the case where the frequency is divided into five or less or five or more.

Further, in the above-mentioned embodiment, when setting the magnitude of the correction signal according to the error signal generated by the error signal charge pump 14, the case where four systems of correction charge pumps 31 to 34 are combined has been described. ,
The present invention is not limited to this, and can also be applied to the case where correction is performed by combining five or more correction charge pumps.

Further, in the above-described embodiment, the case where the timing when the error signal S3 rises and the center of the period of the correction signal S13 coincide with each other regardless of the period of the error signal S3 has been described, but the present invention is not limited to this. Without the error signal S
The center of the period of the correction signal S13 may be adjusted according to the period of 3.

[0071]

As described above, according to the present invention, a dark current sufficiently larger than the correction output is simultaneously supplied to the first current source and the second current source connected in series, and By generating the correction output at a high speed from the difference between the current of the first current source and the current of the second current source, when the oscillation outputs of a plurality of frequencies are switched and output at high speed, the unnecessary wave is generated by the simple configuration. It is possible to realize a frequency synthesizer and a frequency synthesizer method capable of suppressing the frequency and locking each frequency at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a fractional-N synthesizer according to one embodiment of a frequency synthesizer and a frequency synthesizer method according to the present invention.

FIG. 2 is a connection diagram showing a detailed configuration of a fractional-N type synthesizer.

FIG. 3 is a connection diagram for explaining a charge pump.

FIG. 4 shows the error signal of the phase comparator, the correction signal of the automatic phase interpolation circuit, and the count value switching of the frequency divider for N + (1/4) frequency division and N + (1/2) frequency division respectively. It is a timing diagram which shows a timing.

FIG. 5 shows the error signal of the phase comparator, the correction signal of the automatic phase interpolation circuit, and the switching of the count value of the frequency divider for N + (1/4) frequency division and N + (1/2) frequency division. It is a timing diagram which shows a timing.

FIG. 6 is a block diagram showing a conventional N-type synthesizer.

FIG. 7 is a connection diagram for explaining a conventional charge pump.

[Explanation of symbols]

1, 21 ... Fractional N-type synthesizer, 2
...... Reference oscillator, 3 ... Phase comparator, 4 ... Frequency divider,
5, 28 ... Adder, 6, 22 ... Automatic phase interpolation circuit,
7 ... Low-pass filter, 8 ... Sample-hold circuit, 9
...... Voltage control oscillator, 10 ...... Division control circuit, 12, 1
3, 16, 17 ... Selection circuit, 14 ... Error signal charge pump, 15 ... Automatic phase interpolation circuit, 18, 19,
31-34 ... Correction charge pump, 23 ... Pulse width control circuit, 24, 25 ... Counter, 26, 39, 4
0 ... AND circuit ... 27, 29 ... Latch, 37 ...
Reset circuit.

Claims (6)

(57) [Claims] 1. A voltage-controlled oscillator, frequency-dividing means for dividing the oscillation output of the voltage-controlled oscillator by a frequency division ratio 1 / N or 1 / (N + 1) where N is an arbitrary integer, and a reference. A reference signal generating means for generating a frequency signal, a phase difference detecting means for detecting a phase difference between the frequency signal and the frequency-divided output of the frequency dividing means, and a phase opposite to the detection output of the phase-difference detecting means. , A correction output generation means for generating a correction output for correcting the detection output, and a frequency division ratio of the frequency division means are periodically set to 1
/ N or 1 / (N + 1) control means, an addition means for adding the detection output and the correction output, and a filter for converting the addition output of the addition means to a DC voltage and giving it to the voltage controlled oscillator. A frequency synthesizer having a means, a first current source for supplying a first current to the correction output generating means, and a second current for connecting a second current connected in series with the first current source. A frequency synthesizer, the correction output being generated from the difference between the first current and the second current. 2. The frequency synthesizer according to claim 1, wherein each of the first current source and the second current source is composed of a plurality of current sources. 3.The first current source and the second current source
Is The current values are different from each other, The correction output is selected according to the control of the division ratio.
The frequency synthesizer according to claim 1, which is generated.
Cesizer. 4. A frequency division ratio 1 / N and 1 where N is an arbitrary integer.
/ (N + 1) is cyclically controlled to detect the frequency division processing for dividing the oscillation output of the voltage controlled oscillator and the phase difference between the reference frequency signal and the frequency division output obtained by the frequency division processing. Phase difference detection processing, correction output generation processing that generates a correction output that corrects the detection output in the opposite phase to the detection output obtained by the phase difference detection processing, and addition processing that adds the detection output and the correction output When, in accordance with the added output obtained in the addition process, the frequency synthesizer method in generating the I connexion the oscillation output to a DC process of generating a DC component to control the frequency of the oscillation output of the voltage controlled oscillator in, the flow of the first current from a first current source, flows <br/> a second current to a second current source connected to the first current source in series, the said corrected output It is generated from the difference between the first current and the second current. Frequency synthesizer wherein the. 5. The frequency synthesis method according to claim 4, wherein each of the first current source and the second current source is composed of a plurality of current sources. 6.The first current source and the second current source
Is The current values are different from each other, The correction output is selected according to the control of the division ratio.
The frequency synthesizer according to claim 4, wherein the frequency synthesizer is generated.
Cease method.