GB2288931A - Frequency synthesizer employing frequency-dividing ratios of 1/N and 1/(N+1) - Google Patents
Frequency synthesizer employing frequency-dividing ratios of 1/N and 1/(N+1) Download PDFInfo
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- GB2288931A GB2288931A GB9508511A GB9508511A GB2288931A GB 2288931 A GB2288931 A GB 2288931A GB 9508511 A GB9508511 A GB 9508511A GB 9508511 A GB9508511 A GB 9508511A GB 2288931 A GB2288931 A GB 2288931A
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- frequency
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- output
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
- H03J7/18—Automatic scanning over a band of frequencies
- H03J7/20—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element
- H03J7/28—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element using counters or frequency dividers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
Abstract
A frequency synthesizer includes a voltage-controlled oscillator 5, frequency dividing circuits 14, 15, a signal source 1, phase comparing circuits 11, 12, an adding circuit 13, a converting circuit 4 and a control circuit 16. The frequency dividing circuits divide an output supplied thereto from the voltage-controlled oscillator by with frequency-dividing ratios of 1/N and 1/(N+1) where N is an arbitrary integer. The signal source outputs a reference frequency signal. The phase comparing circuits phase-compare a signal divided by the N supplied thereto from the frequency dividing circuit and a signal divided by the (N+1) supplied thereto from the frequency dividing circuit and the reference frequency signal from the signal source. The adding circuit adds a signal which results from phase-comparing the reference frequency signal output from the phase comparing circuit and the signal divided by N and a signal which results from phase-comparing the reference frequency signal output from the phase comparing circuit and the signal divided by (N+1). The converting circuit converts an output from the adding circuit to a DC signal and supplies the same to the voltage-controlled oscillator. The control circuit controls frequency-dividing ratios of the frequency dividing circuits. The control circuit cyclically changes the frequency-dividing ratios of the frequency dividing circuits to 1/N or 1/(N+1). <IMAGE>
Description
FREQUENCY SYNTHESIZER
The present invention relates to a frequency synthesizer and, particularly to a frequency synthesizer formed of a phase locked loop (PLL) circuit.
Frequency synthesizers formed of a PLL circuit generate and output a frequency signal having a frequency of an integral multiple of that of a reference frequency signal output from a reference oscillator. There have hitherto been developed frequency synthesizers that can change a frequency at an interval smaller than an integral multiple.
FIGURE 1 of the accompanying drawings shows an example of such frequency synthesizer. This frequency synthesizer is of a fractional-N system and supplies a reference frequency signal output from a reference oscillator 1 to a phase comparator 2.
The phase comparator 2 detects a phase difference between a frequency-divided signal output from a frequency divider 7, which will be described later on, and the reference frequency signal. The phase comparator 2 supplies an error signal based on the detected phase difference to an adder 3. The adder 3 adds an interpolation signal output from an automatic phase interpolating circuit 9, which will be described later on, to the error signal supplied thereto from the phase comparator 2. The adder 3 supplies a resulting added error signal to a low-pass filter (LPF) 4.
The LPF 4 converts the error signal to a DC error signal.
The LPF 4 supplies a resulting DC error signal to a voltagecontrolled oscillator (VCO) 5 as a control signal. The VCO 5 supplies an oscillation signal to a frequency signal output terminal 6, the frequency divider 7 and a control unit 8.
The frequency divider 7 divides the oscillation output from the VCO 5. The frequency divider 7 alternately switches a frequency-dividing ratio to a predetermined value 1/N (N is an integer) or 1/(N+1) under the control of the control unit 8. The frequency divider 7 supplies a frequency-divided signal to the phase comparator 2. The control unit 8 controls the automatic phase interpolating circuit 9 such that the automatic phase interpolating circuit 9 outputs an interpolation signal at every predetermined period.
Operation of the frequency synthesizer will be described with reference to timing charts of FIGURES 2A to 2C. Assuming that the reference oscillator 1 outputs a reference frequency signal of a period shown in FIGURE 2A, then the frequency divider 7 has a frequency-dividing ratio of 1/N at a certain timing ta of the reference frequency signal as shown in FIGURE 2B. The frequency divider 7 changes the frequency-dividing ratio of 1/N to 1/(N+1) when the reference frequency signal is advanced from the timing ta to a timing tb. Further, the frequency divider 7 resets the frequency-dividing ratio of 1/(N+1) to 1/N when the reference frequency signal is advanced from the timing tb to a timing tc Therefore, the frequency divider 7 repeats the switching of the frequency-dividing ratios of 1(N+1) and 1/N at every period.
When the frequency-dividing ratios are set as described above, the phase comparator 2 detects a predetermined phase error 1 at a timing point where the frequency-dividing ratio is switched from 1/N to 1/(N+1) at every two periods of the reference frequency signal as shown in FIGURE 2C. As a consequence, the oscillation frequency of the VCO 5 is disturbed.
In the frequency synthesizer shown in FIGURE 1, the automatic phase interpolating circuit 9 outputs an interpolation signal for interpolating the phase error 01 at every two periods of the reference frequency signal. Then, the adder 3 adds the interpolation signal to the phase error signal to cancel the phase error 1 out so that the VCO 5 outputs a stable oscillation output.
Therefore, the VCO 5 can output a frequency signal having a frequency (N+0.5) times the frequency of the reference frequency signal. Thus, the frequency synthesizer can change the frequency at an interval smaller than the integral multiple.
In the case of the frequency synthesizer shown in
FIGURE 1, however, the automatic phase interpolating circuit 9 and peripheral circuits become complicated in arrangement.
Specifically, the automatic phase interpolating circuit 9 is formed as a digital-to-analog (DiA) converter for converting digital control data to data of analog level. Thus, the arrangement of the automatic phase interpolating circuit 9 is complicated. Therefore, if the frequency synthesizer includes the automatic phase interpolating circuit, then the
PLL circuit becomes complex in arrangement.
It is therefore an object of the present invention to provide a frequency synthesizer in which the aforesaid problems can be reduced or eliminated.
According to the present invention, there is provided a frequency synthesizer comprising:
voltage-controlled oscillating means;
frequency-dividing means for dividing an output from said voltage-controlled oscillating means with a frequency-dividing ratio of 1/N and 1/(N+1) where N is an arbitrary integer);
a signal source for outputting a reference frequency signal; phase comparing means for phase-comparing signals divided by said frequency-dividing ratios of 1/N and 1/(N+1) by said frequency-dividing means and said reference frequency signal supplied thereto from said signal source;
adding means for adding a signal which results from phase-comparing said reference frequency signal and said signal frequency-divided by said frequency-dividing ratio of 1/N by said phase comparing means and a signal which results from phase-comparing said reference frequency signal and said signal frequency-divided by said frequencydividing ratio of 1/(N+1) by said phase comparing means;
converting means for converting an output from said adding means and supplying a DC output to said voltagecontrolled oscillating means; and
control means for controlling said frequencydividing ratios of said frequency-dividing means, wherein said control means changes said frequency-dividing ratio of said frequency-dividing means to 1/N or 1/(N+1) cyclically.
According to the present invention, since the frequency-dividing ratios of the frequency dividing circuits are changed cyclically at different timings, phase differences between the frequency-divided signals and the reference frequency signal are changed cyclically. Average phase errors can be made equal by adding the results obtained when the frequency-divided signals are phasecompared with the reference signal. As a consequence, the voltage-controlled oscillator can be controlled in the stable state and the oscillation output of the voltagecontrolled oscillator can be controlled by combined frequency-dividing ratios of 1/N and 1/(N+1) of the frequency dividing circuits.
The invention will be further described by way of non-limitative example with reference to the accompanying drawings, in which:
FIGURE 1 is a block diagram showing an example of an arrangement of a frequency synthesizer;
FIGURES 2A to 2C are timing charts used to explain an operation of the frequency synthesizer shown in FIGURE 1;
FIGURE 3 is a block diagram showing a frequency synthesizer according to a first embodiment of the present invention;
FIGURES 4A to 4C are timing charts used to explain an operation of the frequency synthesizer shown in FIGURE 3;
FIGURE 5 is a block diagram showing a frequency synthesizer according to a second embodiment of the present invention; and
FIGURES 6A to 6E are timing charts used to explain an operation of the frequency synthesizer according to the second embodiment of the present invention.
A frequency synthesizer according to the present invention will be described in detail with reference to the drawings.
Initially, a frequency synthesizer according to a first embodiment of the present invention will be described below with reference to FIGURE 3 and FIGURES 4A through 4C.
In FIGURE 3 and FIGURES 4A through 4C, elements and parts identical to those of FIGURE 1 are marked with the same references and therefore need not be described in detail.
FIGURE 3 is a block diagram showing an arrangement of a frequency synthesizer according to a first embodiment of the present invention.
As shown in FIGURE 3, the reference oscillator 1 outputs and supplies a reference frequency signal f, r to first and second phase comparators 11, 12. The reference frequency signal fr has a frequency of 600 kHz. The first comparator 11 detects a phase error signal between a frequency-divided signal of a first frequency divider 14, which will be described later on, and the reference frequency signal. The second phase comparator 12 detects a phase error between a frequency-divided signal of a second frequency divider 15, which will be described later on, and the reference frequency signal.
An adder 13 adds the phase error signals output from the two phase comparators 11, 12. The adder 13 supplies a resulting added phase error signal through the
LPF 4 to the VCO 5 as a control signal. The VCO 5 supplies an oscillation output fc to the frequency signal output terminal 6 and the first and second frequency dividers 14, 15.
The first and second frequency dividers 14, 15 switch a frequency-dividing ratio between 1/N and 1/(N+1) (i.e., 1/2744 and 1/2745) at every predetermined period.
The first and second frequency dividers 14, 15 switch the frequency-dividing ratios under the control of a control unit 16.
The first frequency divider 14 supplies a frequency-divided output to the first phase comparator 14 and the control unit 16. The second frequency divider 15 supplies a frequency-divided output to the second phase comparator 12. The control unit 16 switches the frequencydividing ratios of the first and second frequency dividers 14, 15 in response to every period of the frequency-divided output of the first frequency divider 14. In this case, when the frequency-dividing ratio of the first frequency divider 14 is set to 1/2744, the frequency-dividing ratio of the second frequency divider 15 is set to 1/2745 and vice versa.
An operation of the frequency synthesizer according to the first embodiment of the present invention will be described with reference to FIGURES 4A to 4C.
Assuming that the reference oscillator 1 outputs the reference frequency signal with frequency of 600 kHz at a timing shown in FIGURE 4A, then the frequency-dividing ratio of the first frequency divider 14 is set to 1/2744 at a certain timing t1 of the reference frequency signal as shown in FIGURE 4B and the frequency-dividing ratio of the second frequency divider 15 is set to 1/2745 at a certain timing t1 of the reference frequency signal as shown in
FIGURE 4C. The VCO 5 outputs an oscillation frequency of 1.6 GHz.
When the first and second frequency dividers 14, 15 are energized under this condition, the first frequency divider 14 outputs a frequency-divided output pulse at a timing a little before a timing t2 advanced from the timing t1 of the reference frequency signal by one period as shown in FIGURE 4B, i.e., at a timing earlier than the timing t2 by 0.3 nanosecond. A duration of 0.3 nanosecond corresponds to a half period of 1.6 GHz. The second frequency divider 15 outputs a frequency-divided output pulse a little after the timing t2 advanced from the timing t1 of the reference frequency signal as shown in FIGURE 4C, i.e., later than the timing t2 by 0.3 nanosecond. That is, the second frequency divider 15 outputs the frequency-divided output pulse during a period of time corresponding to a half period of 1.6 GHz.
The first phase comparator 11 detects a phase difference signal between the frequency-divided output pulse of the first frequency divider 14 and the reference frequency signal. The second phase comparator 12 detects a phase difference signal between the frequency-divided output pulse of the second frequency divider 15 and the reference frequency signal. The first and second phase comparators 11 and 12 detect corresponding phase difference signals (i.e., phase difference signals equivalent to difference of duration of 0.3 nanosecond), respectively. The phase difference signals are the phase difference signal advanced from the reference frequency signal by 0.3 nanosecond and the phase difference signal delayed from the reference frequency signal by 0.3 nanosecond.Therefore, the adder 13 adds the above two phase error signals to output a phase error signal whose phase difference is cancelled out.
Accordingly, the adder 13 supplies a phase error signal with phase difference cancelled out through the LPF 4 to the VCO 5. Then, the VCO 5 can continuously output a stable oscillation output.
When the first frequency divider 14 outputs a frequency-divided output pulse, then the first frequency divider 14 switches the frequency-dividing ratio to 1/2745 under the control of the control unit 16 as shown in FIGURE 4B. The second frequency divider 15 also switches the frequency-dividing ratio to 1/2744 under the control of the control unit 16 as shown in FIGURE 4B. As a result, at a timing t3 delayed from the timing t2 of the reference frequency signal by one period, the first comparator 11 detects no phase difference between the frequency-divided output pulse of the first frequency divider 14 and the reference frequency signal. Also, the second phase comparator 12 detects no phase difference between the frequency-divided output pulse of the second frequency divider 15 and the reference frequency signal.Specifically, a time period required till the timing t3 after the first frequency divider 14 had output the frequency-divided output pulse at a timing a little before the timing t2 is longer than one period of the reference frequency signal by 0.3 nanosecond. This time period is equivalent to one period required when the first frequency divider 14 divides the oscillation frequency of 1.6 GHz with the frequency-dividing ratio of 1/2745. A time period required till the timing t3 after the second frequency divider 15 had output the frequency-divided output pulse at a timing delayed a little from the timing t2 is shorter than one period of the reference frequency signal by 0.3 nanosecond. This time period is equivalent to one period required when the second frequency divider 15 divides the oscillation frequency of 1.6 GHz with the frequency-dividing ratio of 1/2744.
Accordingly, the phase differences detected by the first and second phase comparators 11, 12 at the timing t3 are zero. Therefore, when the adder 13 adds the two phase error signals, the adder 13 outputs the phase error signal with a phase difference cancelled. Thus, the phase error signal of phase difference zero is supplied to the VCO 5. A processing from timing t1 to timing t3 will be repeated hereinafter.
Consequently, the VCO 5 outputs the same signal as the oscillation output obtained when the frequency-dividing ratio is 1/2744.5. Then, a frequency signal (about 1.6 GHz) obtained when the frequency-dividing ratio is 1/2744.5 is output from the output terminal 6. Under the condition that the loop of this circuit is stabilized, to be precisely. the oscillation frequency of the VCO 5 becomes 1646.7 MHz.
The frequency synthesizer thus arranged can output a frequency signal having a frequency (integer + 0.5) times the frequency of the reference frequency signal. A circuit arrangement of the inventive frequency synthesizer can be simplified because the phase error signal need not be interpolated unlike the frequency synthesizer shown in
FIGURE 1. Further, in the frequency synthesizer shown in
FIGURE 3, under the condition that the loop circuit is stabilized, the phase error signal supplied to the VCO 5 has a phase difference zero constantly. Thus, the loop circuit can oscillate stably.
Since the inventive frequency synthesizer can output the frequency signal having the frequency (integer + 0.5) times the frequency of the reference frequency signal, the frequency of the reference oscillation signal can be raised high enough to obtain a signal of a desired frequency. Moreover, it is possible to reduce a time required until the loop circuit becomes stabilized.
Further, since the frequency of the reference oscillation signal can be increased, a spurious signal caused by the reference oscillation signal can be attenuated with ease by the LPF 4. Therefore, it is possible to eliminate a bad influence exerted by the spurious signal.
A frequency synthesizer according to a second embodiment of the present invention will be described below with reference to FIGURE 5 and FIGURES 6A through 6E. In
FIGURE 5, like parts corresponding to those of FIGURE 1 are marked with the same references and therefore need not be described in detail. According to the second embodiment of the present invention, the frequency synthesizer can output a frequency signal having a frequency (integer + 0.25) times the frequency of the reference frequency signal.
As shown in FIGURE 5, the reference oscillator 1 outputs and supplies the reference oscillation signal f, r to first, second, third and fourth phase comparators 21, 22, 23, 24. The first phase comparator 21 phase-compares the reference oscillation signal and a frequency-divided signal of a first frequency divider 26; the second phase comparator 22 phase-compares the reference oscillation signal and a frequency-divided signal of the second frequency divider 27; the third phase comparator 23 phase-compares the reference oscillation signal and a frequency-divided signal of the third frequency divider 28; and the fourth phase comparator 24 phase-compares the reference oscillation signal and a frequency-divided signal of a fourth frequency divider 29.
Phase error signals of the first, second, third and fourth phase comparators 21, 22, 23 and 24 are supplied to and added by an adder 25. The adder 25 supplies a resulting added output through the LPF 4 to the VCO 5. The
VCO 5 supplies the oscillation output fc to the frequency signal output terminal 6 and the first, second, third and fourth frequency dividers 26, 27, 28 and 29. The four frequency dividers 26, 27, 28, 29 switch the frequencydividing ratio between 1/N and 1/(N+1) at every predetermined period where N is an integer. Each of the frequency dividers 26, 27, 28, 29 switches the frequencydividing ratio under the control of a control unit 30.
The first, second, third and fourth frequency dividers 26, 27, 28 and 29 supply the frequency-divided signals to the first, second, third and fourth phase comparators 21, 22, 23 and 24, in which these frequencydivided signals are phase-compared with the reference frequency signals. The fourth frequency divider 29 supplies the frequency-divided signal to the control unit 30. The control unit 30 controls the frequency-dividing ratios of the frequency dividers 26 through 29. Assuming that one period represents an interval in which an output pulse is supplied as the frequency-divided signal, then the control unit 30 sets the frequency-dividing ratios of the frequency dividers 26 through 29 to 1/(N+1) once per 4 periods.
Further, the control unit 30 sets the frequency-dividing ratios of the frequency dividers 26 through 29 to 1/N during other periods. The control unit 30, however, sets the frequency-dividing ratios of the frequency dividers 26 through 29 to l/(N+l) at different timings.
An operation of the frequency synthesizer thus arranged will be described with reference to FIGURES 6A to 6E. When the reference oscillator 1 output the reference frequency signal at the period shown in FIGURE 6A, timings of the frequency-divided output pulses of the frequency dividers 26, 27, 28, 29 are agreed at a certain timing t11 of the reference frequency signal as shown in FIGURES 6B, 6C, 6D and 6E. At the timing till, phase error signals of the phase comparators 21 to 24 are zero.
During first one period from the timing t1l (near a timing t12 and until the frequency-divided pulse is output), the frequency-dividing ratio of the first frequency divider 26 is set to l/(N+1) and the frequency-dividing ratios of the remaining frequency dividers 27, 28, 29 are set to 1/N as shown in FIGURE 6B. During the next one period (near a timing t13 and until the frequency-divided pulse is output), the frequency-dividing ratio of the second frequency divider 27 is set to 1/(N+1) and the frequency-dividing ratios of the remaining frequency dividers 26, 28, 29 are set to 1/N as shown in FIGURE 6C.During the next one period (near a timing t14 and until the frequency-divided pulse is output), the frequency-dividing ratio of the third frequency divider 28 is set to 1/(N+1) and the frequency-dividing ratios of the remaining frequency dividers 26, 27, 29 are set to 1/N as shown in FIGURE 6D. During the next one period (until a timing t15), the frequency-dividing ratio of the fourth frequency divider 29 is set to l/(N+1) and frequencydividing ratios of the remaining frequency dividers 26, 27, 28 are set to 1/N as shown in FIGURE 6E.
Inasmuch as the frequency-dividing ratios of the four frequency dividers 26 to 29 are changed sequentially, at the timing t15 in which four periods had been elapsed, the frequency-divided output pulses from the frequency dividers 26 to 29 are agreed in phase and the phase errors can be cancelled out. The phase errors obtained during the four periods from the timing t11 to the timings t12, t13 t14 are agreed with those of the timings t12, t13 t14 because one frequency divider divides the oscillation signal with the frequency-dividing ratio of 1/(N+1) and the remaining three frequency dividers divide the oscillation signal with the frequency-dividing ratio of 1/N and the adder 25 adds the phase error signals. Thus, the phase errors are cancelled out. Accordingly, the phase errors are cancelled out at each timing and the loop circuit is stabilized.
According to this embodiment, since the frequencydividing ratio is shifted by 1 at every four periods, the frequency synthesizer can generate a frequency signal having a frequency (integer + 0.5) or (integer + 0.25) times the frequency of the reference frequency signal. The frequency synthesizer shown in FIGURE 5 also can achieve the effects similar to those of the frequency synthesizer shown in
FIGURE 3.
While the frequency synthesizer can generate a frequency signal having a frequency (integer + 0.5) or (integer + 0.25) times the frequency of the reference frequency signal as described above, the present invention is not limited thereto and the inventive frequency synthesizer can generate frequency signal having a frequency of a multiple having other decimal points. Specifically, there are provided frequency dividers whose frequencydividing ratios are switched and phase comparators of the number corresponding to the decimal point so that phase error is reduced at every one period by averaging.
Furthermore, the frequencies and the frequencydividing ratios in the aforesaid embodiments are described by way of example and can be freely changed.
Having described preferred embodiments of the invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments and that various changes and modifications could be effected therein by one skilled in the art without departing from the spirit or scope of the invention as defined in the appended claims.
Claims (7)
1. A frequency synthesizer comprising:
voltage-controlled oscillating means;
frequency-dividing means for dividing an output from said voltage-controlled oscillating means with a frequency-dividing ratio of 1/N and 1/(N+1) where N is an arbitrary integer);
a signal source for outputting a reference frequency signal; phase comparing means for phase-comparing signals divided by said frequency-dividing ratios of 1/N and 1/(N+1) by said frequency-dividing means and said reference frequency signal supplied thereto from said signal source;
adding means for adding a signal which results from phase-comparing said reference frequency signal and said signal frequency-divided by said frequency-dividing ratio of 1/N by said phase comparing means and a signal which results from phase-comparing said reference frequency signal and said signal frequency-divided by said frequencydividing ratio of 1/(N+1) by said phase comparing means;
converting means for converting an output from said adding means and supplying a DC output to said voltagecontrolled oscillating means; and
control means for controlling said frequencydividing ratios of said frequency-dividing means, wherein said control means changes said frequency-dividing ratio of said frequency-dividing means to 1/N or 1/(N+1) cyclically.
2. A frequency synthesizer according to claim 1, wherein said frequency dividing means includes at least two frequency dividers for dividing an input signal by said frequency-dividing ratios of 1/N and l/(N+1) and said control means switches said frequency-dividing ratio to 1/N or 1/(N+1) based on an output signal from any one of said two frequency dividers.
3. A frequency synthesizer according to claim 2, wherein said phase comparing means includes at least two phase comparators supplied with said reference frequency signal from said signal source and phase-comparing signals output from said two frequency dividers and said reference frequency signal from said signal source and output signals from said phase comparators are supplied to said adding means.
4. A frequency synthesizer according to claim 1, wherein said frequency dividing means includes first and second frequency dividers for dividing an input signal with said frequency-dividing ratios of 1/N and 1/(N+1), said control means controls said first frequency divider such that said frequency-dividing ratio of said first frequency divider is cyclically changed to 1/N and 1/(N+1), said control means controls said second frequency divider such that said frequency-dividing ratio of said second frequency divider is cyclically changed to 1/(N+1) and 1/N and said voltage-controlled oscillating means outputs a frequency signal having a frequency (N + 0.5) times the frequency of said reference frequency signal.
5. A frequency synthesizer according to claim 1, wherein said frequency dividing means includes first, second, third and fourth frequency dividers for dividing an input signal with said frequency-dividing ratios of 1/N and 1/(N+1), said control means sets a frequency-dividing ratio of any one of said first, second, third and fourth frequency dividers to 1/(N+1) and changes frequency-dividing ratios of other remaining frequency dividers to 1/N cyclically and said voltage-controlled oscillating means outputs a frequency signal having a frequency (N + 0.25) times the frequency of said reference frequency signal.
6. A frequency synthesizer according to any one of the preceding claims, wherein said converting means is formed of a low-pass filter.
7. A frequency synthesizer constructed and arranged to operate substantially as hereinbefore described with reference to and as illustrated in Figures 3 to 4C or
Figures 5 to 6E of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6092557A JPH07297713A (en) | 1994-04-28 | 1994-04-28 | Frequency synthesizer |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9508511D0 GB9508511D0 (en) | 1995-06-14 |
| GB2288931A true GB2288931A (en) | 1995-11-01 |
| GB2288931B GB2288931B (en) | 1998-09-23 |
Family
ID=14057725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9508511A Expired - Fee Related GB2288931B (en) | 1994-04-28 | 1995-04-26 | Frequency synthesizer |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH07297713A (en) |
| KR (1) | KR100343078B1 (en) |
| CN (1) | CN1099763C (en) |
| GB (1) | GB2288931B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6522183B2 (en) | 1999-01-29 | 2003-02-18 | Sanyo Electric Co., Ltd. | PLL device and programmable frequency-division device |
| WO2020148517A1 (en) * | 2019-01-17 | 2020-07-23 | CML Microcircuits (UK) Ltd | Phase-locked loop circuitry |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19816656C2 (en) * | 1998-04-15 | 2000-08-10 | Suedwestrundfunk Anstalt Des O | Method of generating frequencies |
| JP5229081B2 (en) * | 2009-04-10 | 2013-07-03 | 富士通株式会社 | Semiconductor device |
| US9019016B2 (en) * | 2011-05-18 | 2015-04-28 | Asahi Kasei Microdevices Corporation | Accumulator-type fractional N-PLL synthesizer and control method thereof |
-
1994
- 1994-04-28 JP JP6092557A patent/JPH07297713A/en active Pending
-
1995
- 1995-04-26 GB GB9508511A patent/GB2288931B/en not_active Expired - Fee Related
- 1995-04-27 KR KR1019950010085A patent/KR100343078B1/en not_active IP Right Cessation
- 1995-04-28 CN CN95104195A patent/CN1099763C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6522183B2 (en) | 1999-01-29 | 2003-02-18 | Sanyo Electric Co., Ltd. | PLL device and programmable frequency-division device |
| WO2020148517A1 (en) * | 2019-01-17 | 2020-07-23 | CML Microcircuits (UK) Ltd | Phase-locked loop circuitry |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9508511D0 (en) | 1995-06-14 |
| KR100343078B1 (en) | 2002-12-16 |
| KR950035076A (en) | 1995-12-30 |
| CN1113053A (en) | 1995-12-06 |
| JPH07297713A (en) | 1995-11-10 |
| GB2288931B (en) | 1998-09-23 |
| CN1099763C (en) | 2003-01-22 |
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| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20100426 |