CN1099763C - Frequency synthesizer - Google Patents
Frequency synthesizer Download PDFInfo
- Publication number
- CN1099763C CN1099763C CN95104195A CN95104195A CN1099763C CN 1099763 C CN1099763 C CN 1099763C CN 95104195 A CN95104195 A CN 95104195A CN 95104195 A CN95104195 A CN 95104195A CN 1099763 C CN1099763 C CN 1099763C
- Authority
- CN
- China
- Prior art keywords
- frequency
- signal
- divider
- dividing ratio
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000010355 oscillation Effects 0.000 claims description 15
- 238000007792 addition Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
- H03J7/18—Automatic scanning over a band of frequencies
- H03J7/20—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element
- H03J7/28—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element using counters or frequency dividers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A frequency synthesizer includes a voltage-controlled oscillator, frequency dividing circuits, a signal source, phase comparing circuits, an adding circuit, a converting circuit and a control circuit. The frequency dividing circuits divide an output supplied thereto from the voltage-controlled oscillator by with frequency-dividing ratios of 1/N and 1/(N+1) where N is an arbitrary integer. The signal source outputs a reference frequency signal. The phase comparing circuits phase-compare a signal divided by the N supplied thereto from the frequency dividing circuit and a signal divided by the (N+1) supplied thereto from the frequency dividing circuit and the reference frequency signal from the signal source. The adding circuit adds a signal which results from phase-comparing the reference frequency signal output from the phase comparing circuit and the signal divided by N and a signal which results from phase-comparing the reference frequency signal output from the phase comparing circuit and the signal divided by (N+1). The converting circuit converts an output from the adding circuit to a DC signal. The control circuit controls frequency-dividing ratios of circuits.
Description
Technical field
The present invention relates to frequency synthesizer, specifically, relate to the frequency synthesizer that constitutes by phase-locked loop (PLL) circuit.
Background technology
The frequency synthesizer that is made of the PLL circuit produces and exports a frequency signal, and this signal has the frequency of the fundamental frequency signal frequency integral multiple of reference oscillator output.Its frequency of the frequency synthesizer that below obtains can change over the frequency that is in less than integral multiple.
Fig. 1 illustrates the example of this frequency synthesizer.This frequency synthesizer is the N score system, and the fundamental frequency signal of reference oscillator 1 is outputed on the phase comparator 2.
The work of frequency synthesizer is described to the sequential chart of 2C with reference to Fig. 2 A.Suppose that reference oscillator 1 exports the fundamental frequency signal of one-period shown in Fig. 2 A, then frequency divider 7 has the frequency dividing ratio of 1/N as a certain moment ta of Fig. 2 fundamental frequency signal that B is shown in.When fundamental frequency signal when moment ta enters constantly tb, frequency divider 7 changes the frequency dividing ratio of 1/N into the frequency dividing ratio of 1/ (N+1).When fundamental frequency signal when moment tb changes to constantly tc, the frequency dividing ratio with 1/ (N+1) returns to 1/N again.Thereby at each constantly, frequency divider 7 repeatedly switches frequency dividing ratio 1/ (N+1) and 1/N.
After frequency dividing ratio is as above set, the predetermined phase error Φ 1 that phase comparator detected shown in Fig. 2 C a moment, at that point, per two cycles of fundamental frequency signal go up frequency dividing ratio and are switched to 1/ (N+1) from 1/N.As a result, the frequency of oscillation of VCO5 is upset.
In frequency synthesizer shown in Figure 1, automatic phase interpolating circuit 9 is interpolation phase error Φ 1 output interpolated signal in per two cycles of fundamental frequency signal.Subsequently, adder 3 is added on the phase error signal interpolated signal to eliminate disable bit error Φ 1, like this, and the vibration output that VCO5 output is stable.
So VCO5 can be output as the frequency signal of fundamental frequency signal frequency (N+0.5) overtones band.Like this, frequency synthesizer can make its frequency shift be the intermediate frequency less than integral multiple.
Yet in the frequency synthesizer of Fig. 1, it is more complicated that automatic phase interpolating circuit 9 and peripheral circuit become.Specifically, automatic phase interpolating circuit 9 is to be made of the D/A that digital control data is converted to analog level.Like this, the circuit structure of automatic phase interpolating circuit 9 is just complicated.If frequency synthesizer comprises the automatic phase interpolating circuit, then the PLL circuit will be more complicated.
Summary of the invention
The object of the present invention is to provide a kind of frequency synthesizer that solves foregoing problems.
According to a kind of frequency synthesizer provided by the invention, comprising: voltage-controlled oscillation unit; First and second frequency dividers, both are used for the frequency dividing ratio of 1/N or 1/ (N+1) output signal of described voltage-controlled oscillation unit being carried out frequency division, and wherein N is an arbitrary integer; A signal source that is used to export fundamental frequency signal; One first phase comparator is used for and will carries out bit comparison mutually with described fundamental frequency signal from described signal source from the output signal behind the frequency division of described first frequency divider; One second phase comparator is used for and will carries out bit comparison mutually with described fundamental frequency signal from described signal source from the output signal behind the frequency division of described second frequency divider; Adder is used for from one first signal of described first phase comparator with from a secondary signal addition of described second phase comparator; Low pass filter is used for converting the output signal from described adder to a direct current output, to be used to control described voltage-controlled oscillation unit; With, control device, be used to receive one of them from the described output signal of described first and second frequency dividers, to control the described frequency dividing ratio of described frequency divider, wherein said control device is changed into 1/N or 1/ (N+1) with the described frequency dividing ratio of described frequency divider periodically and alternately.
According to the present invention, because the frequency dividing ratio of frequency dividing circuit had periodically in the variant moment, then the phase difference between fractional frequency signal and fundamental frequency signal changes periodically.After result that fractional frequency signal and fundamental frequency signal bit comparison are mutually obtained was added into, it is equal that average phase-difference can become.As a result, voltage controlled oscillator can be controlled with being stabilized, and the vibration of voltage controlled oscillator output can combine by the frequency dividing ratio 1/N and 1/ (N+1) that makes frequency dividing circuit and comes control.
Description of drawings
Fig. 1 is a block diagram, and an example of frequency synthesizer circuit structure is shown;
Fig. 2 A-2C is a sequential chart, is used for the work of the frequency synthesizer of key diagram 1;
Fig. 3 is a block diagram, and the frequency synthesizer according to first embodiment of the invention is shown;
Fig. 4 A-4C is a sequential chart, is used to illustrate the work of frequency synthesizer shown in Figure 3;
The block diagram of Fig. 5 illustrates the frequency synthesizer according to second embodiment of the invention; With
Fig. 6 A-6C is a sequential chart, is used to illustrate the frequency synthesizer according to second embodiment of the invention.
The embodiment explanation
At first, with reference to Fig. 3 and Fig. 4 A to 4C frequency synthesizer according to first embodiment of the invention is described.In Fig. 3 and Fig. 4 A-4C, the parts identical with Fig. 1 are marked with same numeral and repeat no more.
Fig. 3 is a block diagram, and the circuit structure according to the frequency synthesizer of first embodiment of the invention is shown.
As shown in Figure 3, reference oscillator 1 is added to fundamental frequency signal fr on first and second phase comparators 11,12.Fundamental frequency signal fr frequency is 600MHz.First comparator 11 detects the fractional frequency signal of first frequency divider 14 and the phase error between fundamental frequency signal.Second phase comparator 12 detects the fractional frequency signal of second frequency divider 15 and the phase error between the fundamental frequency signal.
Adder 13 is with the phase error signal addition of two phase comparators, 11,12 outputs.Adder 13 is added to VCO5 with the phase error signal after the addition through LPF4 and goes up as control signal.The VCO5 output fc that will vibrate is added on frequency signal output 6 and first, second frequency divider 14,15.
First and second frequency dividers 14,15 switch frequency dividing ratio at each predetermined period (promptly 1/2744/ and/1/2745) between 1/N and 1/ (N+1).First and second frequency dividers 14,15 switch frequency dividing ratio under the control of control unit 16.
First frequency divider 14 is added to frequency division output on first phase comparator 14 and the control unit 16.Second frequency divider is added to frequency division output on second phase comparator 12.Control unit 16 switches the frequency dividing ratio of first and second frequency dividers 14,15 according to each cycle of the frequency division output of first frequency divider 14.In the case, when the frequency dividing ratio of first frequency divider 14 was made as 1/2744, the frequency dividing ratio of second frequency divider 15 was made as 1/2745, and vice versa.
The work of the frequency synthesizer of first embodiment of the invention is described with reference to Fig. 4 A-4C.
Suppose the fundamental frequency signal of reference oscillator 1 at the moment of Fig. 4 A output 600MHz.Then the frequency dividing ratio of first frequency divider 14 is set to 1/2744 at the t1 sometime of the fundamental frequency signal shown in Fig. 4 B, and the frequency dividing ratio of second frequency divider 15 is revolved t1 and is set to 1/2745 when certain of the fundamental frequency signal shown in Fig. 4 C.The frequency of oscillation of VCO5 output is 1.6 gigahertz (GHZ)s.
When after first and second frequency dividers 14,15 are activated under this state, after the moment t1 of first frequency divider 14 fundamental frequency signal in a period shown in Fig. 4 B before the t2 constantly a bit promptly early than the moment output frequency division output pulse of t20.3 nanosecond.0.3 the time of nanosecond is corresponding to half of 1.6 gigahertz (GHZ) cycles.Second frequency divider 15 a bit promptly lags behind the moment output frequency division output pulse of t20.3 nanosecond after moment t2 after the moment of the fundamental frequency signal shown in Fig. 4 C t1.That is to say, the time of second frequency divider, 15 output frequency division pulses with the half period time corresponding of 1.6 gigahertz (GHZ)s in.
First phase comparator 11 detects the output pulse of first frequency divider 14 and the phase signal between the fundamental frequency signal.Second phase comparator 12 detects the frequency division output pulse of second frequency divider 15 and the phase signal between fundamental frequency signal.First and second phase comparators 11 and 12 detect corresponding phase signal (phase signal that promptly is equivalent to the difference of 0.3 nanosecond) respectively.Phase signal is respectively the phase signal that is ahead of 0.3 nanosecond of fundamental frequency signal and lags behind the fundamental frequency signal phase signal of 0.3 nanosecond.Like this, adder 13 is exported the phase error signal that its phase difference has been eliminated mutually with above-mentioned two phase error signals.
Therefore, adder 13 is added on the VCO5 through the phase error signal that LPF4 has eliminated phase difference wherein.Subsequently, can make VCO5 constantly export stable vibration output.
After first frequency divider, 14 output frequency divisions output pulse, first frequency divider 14 switched under the control shown in Fig. 4 B at control unit 16 on 1/2745 the frequency dividing ratio.Second frequency divider 15 is also switching under the control of control unit 16 as Fig. 4 B on 1/2744 the frequency dividing ratio.As a result, delay the moment t3 of one-period at the moment t2 from fundamental frequency signal, first comparator 11 detects between the frequency division output pulse of first frequency divider 14 and the fundamental frequency signal does not have phase difference.In addition, second phase comparator 12 is also measured between the frequency division output pulse of second frequency divider 15 and the fundamental frequency signal does not have phase difference.Specifically, constantly to the cycle of between the moment t3 period ratio fundamental frequency signal of output pulse grow 0.3 nanosecond in t2 at first frequency divider 14 before slightly.This time cycle be equivalent to when first frequency divider 14 with 1/2745 frequency dividing ratio required time cycle during with the frequency of oscillation frequency division of 1.6 gigahertz (GHZ)s.Omit the period ratio fundamental frequency signal of pulse is exported in the back to moment t3 output frequency division behind moment t2 one-period 0.3 nanosecond of weak point at second frequency divider 15.This cycle is equivalent to second frequency divider 15 with the 1/2744 frequency dividing ratio one-period that the frequency of oscillation frequency division of 1.6 gigahertz (GHZ)s is required.
Therefore, be zero at moment t3 by first and second phase comparators, 11,12 measured phase differences.Like this, after adder 13 was with two phase error signal additions, the phase error signal of phase difference had been eliminated in adder 13 outputs.So the phase error signal of zero phase difference is added on the VCO5.Below will repeat is process from moment t1 to moment t3.
As a result, VCO5 output and the oscillating phase of when frequency dividing ratio is 1/2744.5, exporting signal together.Subsequently, the frequency signal of about 1.6 gigahertz (GHZ)s that obtained when frequency dividing ratio is 1/2744.5 comes out from terminal 6.Under loop stability and accurate situation, the frequency of oscillation of VCO5 will be 1646.7 megahertzes.
The frequency (integer+0.5) that exportable its frequency of such frequency synthesizer is fundamental frequency signal frequency signal doubly.The circuit arrangement of frequency synthesizer of the present invention is owing to need the phase error signal of interpolation to be different from the frequency synthesizer of Fig. 1, thereby simple in structure.In addition, in the frequency synthesizer of Fig. 3, under the situation of loop stability, being added to phase error signal on the VCO5, to have constant be zero phase difference.Like this, loop can stably vibrate.
Because exportable its frequency of frequency synthesizer of the present invention is fundamental frequency signal frequency (integer+a 0.5) frequency signal doubly, then the frequency of benchmark oscillator signal can be high enough to obtain the signal of required frequency.In addition, can reduce and loop is reached stablize the required time.Also have, owing to can increase the frequency of benchmark oscillator signal, the parasitic signal that is produced by the benchmark oscillator signal can easily be attenuated by LPF4.Thereby, can eliminate the bad influence that parasitic signal causes.
The frequency synthesizer of second embodiment of the invention is described with reference to Fig. 5 and Fig. 6 A-6E.In Fig. 5, the parts identical with Fig. 1 are marked with identical label and repeat no more.According to a second embodiment of the present invention, exportable its frequency of this frequency synthesizer is fundamental frequency signal frequency (integer+a 0.5) frequency signal doubly.
As shown in Figure 5, reference oscillator 1 is added to benchmark oscillator signal fr on the first, second, third and the 4th phase comparator 21,22,23,24.First phase comparator 21 carries out bit comparison mutually with the benchmark oscillator signal with the fractional frequency signal of first frequency division 24; Second phase comparator 22 carries out bit comparison mutually with the benchmark oscillator signal with the fractional frequency signal of second frequency divider 27; It is low that third phase bit comparator 23 carries out bit comparison mutually with the benchmark oscillator signal and the fractional frequency signal of tri-frequency divider 28; The 4th phase comparator 24 carries out bit comparison mutually with the benchmark oscillator signal with the fractional frequency signal of four-divider 29.
First, second and third phase error signal with four phase comparators 21,22,23 and 24 is added on the adder 25 and carries out addition.Adder 25 is added to the result of addition on the VCO5 through LPF4.The VCO5 output fc that will vibrate is added on frequency signal output 6 and first, second and third and the four- divider 26,27,28 and 29.Four frequency dividers 26,27,28,29 switch its frequency dividing ratio at each predetermined period between 1/N and 1/ (N+1), wherein N is an integer.Each frequency divider all switches frequency dividing ratio under the control of control unit 30.
First, second, third and fourth frequency divider 26,27,28,29 will be wherein be added on first, second, third, fourth phase comparator 21,22,23 and 24 with fractional frequency signal after fundamental frequency signal carries out bit comparison mutually.Four-divider 29 is added to fractional frequency signal on the control unit 30.The frequency dividing ratio of control unit 30 control frequency divider 26-29.Suppose that one-period representative wherein exports the interval that pulse adds with fractional frequency signal, then control unit 30 each 4 frequency dividing ratios that frequency divider 26-29 is set periodically are 1/ (N+1).In addition, in other cycle, the frequency dividing ratio of control unit 30 frequency divider 26-29 is set to 1/N.Yet control unit 30 is made as 1/ (N+1) in the different moment with the frequency dividing ratio of frequency divider 26-29.
The frequency synthesizer of such structure is described with reference to Fig. 6 A-6E.When reference oscillator 1 during at the cycle shown in Fig. 6 A output fundamental frequency signal, frequency divider 26,27, the sequential of 28 and 29 frequency division output pulse is at Fig. 6 B, 6C, and certain of 6D and the fundamental frequency signal shown in the 6E is consistent during t11 constantly.At moment t11, the phase error signal of phase comparator 21-24 is zero.
From first cycle of moment t11 (t12 is output the back up to divided pulse near the moment), the frequency dividing ratio of first frequency divider 26 is made as 1/ (N+1), and the frequency dividing ratio of all the other frequency dividers 27,28,29 is made as 1/N shown in Fig. 6 B.In next cycle (t13 is output the back up to divided pulse near the moment), the frequency dividing ratio of second frequency divider 27 is made as 1/ (N+1), and the frequency dividing ratio of all the other frequency dividers 26,28,29 is made as 1/N shown in Fig. 6 C.Following one-period again (being output the back up to divided pulse near t14 constantly), the frequency dividing ratio of tri-frequency divider 28 is set as 1/ (N+1), and the frequency dividing ratio of all the other frequency dividers 26,27,29 is made as 1/N shown in Fig. 6 D.So cycle (up to moment t15) of following in, the frequency dividing ratio of four-divider 29 is made as 1/ (N+1), and the frequency dividing ratio of all the other frequency dividers 26,27,28 is made as 1/N shown in Fig. 6 E.
Because the moment t15 of frequency dividing ratio after four period expires of four frequency dividers 26 to 29 sequentially changed, the frequency division output impulse phase of frequency divider 26-29 is consistent, and phase error is removed.From the time revolve t11 to t12 constantly, t13, the phase error that is obtained in four cycles of t14 with the time revolve the consistent of t12, t13, t14, because, frequency divider with the frequency dividing ratio of 1/ (N+1) with oscillation signal frequency dividing, and all the other will be with the frequency dividing ratio of 1/N with oscillation signal frequency dividing at three frequency dividers, and adder 25 is with these phase error signal additions.So phase error is removed.Therefore, all be removed in each phase error constantly, loop is working stability also.
According to this embodiment, because frequency dividing ratio moves 1 in per four cycles, then can to produce the phase frequency be fundamental frequency signal frequency (integer+0.5) or (integer+0.25) frequency signal doubly to frequency synthesizer.Frequency synthesizer shown in Figure 5 also can reach the effect similar to frequency synthesizer shown in Figure 3.
As mentioned above, though it is fundamental frequency signal frequency (integer+0.5) or (integer+0.25) frequency signal doubly that this frequency synthesizer can produce its frequency, but the present invention is not limited to this, and frequency synthesizer of the present invention can produce the frequency signal of its frequency for other mixed decimal point decimal system multiple.Specifically, frequency divider and a plurality of phase comparator corresponding to decimal point that can provide its frequency dividing ratio to be switched like this, reduce by on average making the phase error in each cycle.
In addition, each frequency in the previous embodiment and frequency dividing ratio are described by means of example, and they can change arbitrarily.
Claims (5)
1. frequency synthesizer comprises:
Voltage-controlled oscillation unit;
First and second frequency dividers, both are used for the frequency dividing ratio of 1/N or 1/ (N+1) output signal of described voltage-controlled oscillation unit being carried out frequency division, and wherein N is an arbitrary integer;
A signal source that is used to export fundamental frequency signal;
One first phase comparator is used for and will carries out bit comparison mutually with described fundamental frequency signal from described signal source from the output signal behind the frequency division of described first frequency divider;
One second phase comparator is used for and will carries out bit comparison mutually with described fundamental frequency signal from described signal source from the output signal behind the frequency division of described second frequency divider;
Adder is used for from one first signal of described first phase comparator with from a secondary signal addition of described second phase comparator;
Low pass filter is used for converting the output signal from described adder to a direct current output, to be used to control described voltage-controlled oscillation unit; With
Control device, be used to receive one of them from the described output signal of described first and second frequency dividers, to control the described frequency dividing ratio of described frequency divider, wherein said control device is changed into 1/N or 1/ (N+1) with the described frequency dividing ratio of described frequency divider periodically and alternately.
2. frequency synthesizer as claimed in claim 1 is characterized in that, described control device switches to 1/N or 1/ (N+1) according to any one output signal of described two frequency dividers with described frequency dividing ratio.
3. frequency synthesizer as claimed in claim 2 is characterized in that, described from signal source fundamental frequency signal and be added on the described adder from the output signal of described phase comparator.
4. frequency synthesizer as claimed in claim 1, it is characterized in that, described control device is controlled described first frequency divider, like this, the described frequency dividing ratio of described first frequency divider changes to 1/N and 1/ (N+1) periodically, and described control device is controlled described second frequency divider, like this, the described frequency dividing ratio of described second frequency divider changes to 1/ (N+1) and 1/N periodically, and described voltage-controlled oscillation unit to export its frequency be described fundamental frequency signal frequency (N+0.5) frequency signal doubly.
5. frequency synthesizer as claimed in claim 1, it is characterized in that, comprise first, second, third and the four-divider that input signal are carried out frequency division with the described frequency dividing ratio of 1/N and 1/ (N+1), described control device with described first, second, three and any one frequency dividing ratio of four-divider be made as 1/ (N+1), and change the frequency dividing ratio of the surplus frequency divider of tool into 1/N periodically, and described voltage-controlled oscillation unit is exported the frequency that its frequency is described fundamental frequency signal (N+0.25) frequency signal doubly.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6092557A JPH07297713A (en) | 1994-04-28 | 1994-04-28 | Frequency synthesizer |
| JP092557/1994 | 1994-04-28 | ||
| JP092557/94 | 1994-04-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1113053A CN1113053A (en) | 1995-12-06 |
| CN1099763C true CN1099763C (en) | 2003-01-22 |
Family
ID=14057725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95104195A Expired - Fee Related CN1099763C (en) | 1994-04-28 | 1995-04-28 | Frequency synthesizer |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH07297713A (en) |
| KR (1) | KR100343078B1 (en) |
| CN (1) | CN1099763C (en) |
| GB (1) | GB2288931B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19816656C2 (en) * | 1998-04-15 | 2000-08-10 | Suedwestrundfunk Anstalt Des O | Method of generating frequencies |
| WO2000045515A1 (en) | 1999-01-29 | 2000-08-03 | Sanyo Electric Co., Ltd. | Pll apparatus and variable frequency-division device |
| JP5229081B2 (en) * | 2009-04-10 | 2013-07-03 | 富士通株式会社 | Semiconductor device |
| CN102959868B (en) * | 2011-05-18 | 2015-09-16 | 旭化成微电子株式会社 | Accumulator type fractional-n pll synthesizer and control method thereof |
| GB2580631B (en) * | 2019-01-17 | 2022-04-27 | Cml Microcircuits Uk Ltd | Phase-locked loop circuitry |
-
1994
- 1994-04-28 JP JP6092557A patent/JPH07297713A/en active Pending
-
1995
- 1995-04-26 GB GB9508511A patent/GB2288931B/en not_active Expired - Fee Related
- 1995-04-27 KR KR1019950010085A patent/KR100343078B1/en not_active IP Right Cessation
- 1995-04-28 CN CN95104195A patent/CN1099763C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR950035076A (en) | 1995-12-30 |
| CN1113053A (en) | 1995-12-06 |
| GB9508511D0 (en) | 1995-06-14 |
| GB2288931A (en) | 1995-11-01 |
| JPH07297713A (en) | 1995-11-10 |
| KR100343078B1 (en) | 2002-12-16 |
| GB2288931B (en) | 1998-09-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1127200C (en) | Frequency synthetic circuit regulated by digit | |
| CN1118937C (en) | Digital PLL circuit and clock generation method | |
| US5521948A (en) | Frequency synthesizer | |
| CN1158768C (en) | Fractional-N frequency synthesizer with jitter compensation | |
| EP1249936A2 (en) | Lock detection circuit | |
| US20100301953A1 (en) | Phase lock loop with a multiphase oscillator | |
| CN101419483B (en) | Clock generator based on phase-locked loop and clock generating method | |
| JPH08223037A (en) | Frequency synthesizer | |
| CN1099163C (en) | High frequency digital phase locking circuit | |
| CN1084088C (en) | Frequency synthesizer | |
| CN1118205A (en) | A signal processing circuit and a method of delaying a binary periodic input signal | |
| CN1099763C (en) | Frequency synthesizer | |
| US4575867A (en) | High speed programmable prescaler | |
| JPH04356804A (en) | Method and device for synthesizing digital signal | |
| KR100414864B1 (en) | Digital Counter and Digital PLL Circuit | |
| JPH066212A (en) | Phase comparator circuit and phase locked loop oscillation circuit with the same | |
| CN86101017A (en) | Oscillating circuit | |
| JPH09261048A (en) | Variable frequency devider | |
| JP2007142791A (en) | Frequency synthesizer | |
| CN1166061C (en) | Digital phase-locked loop circuit | |
| CN114710154A (en) | Open-loop fractional frequency divider and clock system based on time division multiplexing gain calibration | |
| CN1761157A (en) | Dynamic voltage mode phase interpolation circuit suitable to phase locked loop of each annular oscillation | |
| US5160894A (en) | Digital frequency synthesizer and method of frequency synthesis | |
| CN114337661B (en) | Decimal frequency dividing and dynamic phase shifting system based on PLL circuit | |
| JP2002280897A (en) | Fully digital pll circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20030122 Termination date: 20100428 |