JPH09261048A - Variable frequency devider - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable frequency divider which is able to make N+1/2 frequency divisions by using a programmable frequency divider operated at the same speed as frequency division by N. SOLUTION: A programmable frequency divider means 1 frequency-divides an input signal at a frequency division ration N (N is an integer) and at a frequency division ration N+1 alternately. A 1st signal generating means 4 generates a 1st signal synchronized with an output signal of the programmable frequency divider means. A 2nd signal generating means 6 generates a 2nd signal that is obtained by delaying the 1st signal by a half period of the input signal. An output means 13 selects alternately the 1st signal or the 2nd signal and outputs the selected signal as a frequency division signal. A delay means 7 outputs a delay signal obtained by delaying the 1st signal by one period of the input signal. A preset signal generating means 9 selects the delay signal or the 1st signal alternately to preset the programmable frequency divider means by this selected signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable frequency divider used for a frequency synthesizer or the like composed of a phase locked loop (PLL), and more specifically, N + 1/2.
The present invention relates to a variable frequency divider that can perform frequency division.

The present invention also relates to a variable frequency divider capable of performing N + B / C frequency division.

The present invention also relates to a PLL using the variable frequency divider as described above.

[0004]

2. Description of the Related Art Generally, a frequency synthesizer composed of a PLL has a voltage controlled oscillator (VCO) as shown in FIG.
181, a variable frequency divider 182, a phase comparator 183 and a low frequency filter (LPF) 184. By changing the frequency division ratio N of the programmable frequency divider 185 in the variable frequency divider 182, the reference frequency is changed. Local oscillation frequency fo = N × fr of the voltage controlled oscillator (VCO) 181 that is an integer N times fr
It is possible to stably oscillate, by configuring the local oscillator circuit of the receiver with this frequency synthesizer, making the reference frequency fr correspond to the inter-station frequency of the reception band, and changing the division ratio N by 1 , A synthesizer receiver that can obtain a local oscillation frequency fo in an inter-station frequency step is used.

Thus, in the conventional frequency synthesizer,
Since the local oscillation frequency fo oscillates at an integer multiple of the reference frequency fr, for example, the reference frequency fr is 100 KH in the receiver.
When set to z, there is a problem that a station having an inter-station frequency of 50 KHz cannot receive. Therefore, it is desired to lock the PLL at a fractional multiple of the reference frequency fr, and PLLs that meet such a request are disclosed in Japanese Patent Publication No. 51-49540 and Japanese Utility Model Publication No. 62-30352. 36 shows an example of a circuit as shown in FIG.

As shown in the figure, the local oscillation frequency fo is input to the presettable counter 192 via the gate circuit 193. The gate circuit 193 inverts the phase of the output each time the count value of the counter 192 reaches a predetermined value. Therefore, as shown in FIG. 36, the counter 192 counts the rising edge of the signal of the local oscillation frequency fo in a certain counting cycle, and counts the falling edge in the next counting cycle. In this way, N + 1/2 frequency division is performed.

[0007]

However, in the above configuration, the output of N + 1/2 is input to the presettable counter as a preset signal. Therefore,
When switching the counting cycle (when N in FIG. 36 changes to 1)
Needs to be counted in a half cycle of the local oscillation frequency, and the operating speed of the presettable counter has to be doubled.

As another frequency divider, the fractional frequency divider ICSA8025 manufactured by Philips is capable of fractional frequency division of N + B / C (B and C are integers and B≤C). This fractional frequency divider has an N frequency divider circuit and combines N'frequency division and N '+ 1 frequency division into N'based on the overflow of the accumulator.
+ B / C frequency division is performed.

The operation of the fractional frequency divider for N '+ 2/5 frequency division (B = 2, C = 5) will be described with reference to FIG. In this case, 2 (value of numerator B) is added to the accumulator every time, and overflow occurs when it is 5 (value of denominator C) or more. When the first addition is performed, the value of the accumulator becomes 2, and since no overflow has occurred, the frequency division is performed by N '. When the second addition is performed, the value of the accumulator becomes 4, and since no overflow has occurred, the N'frequency division is performed. When the third addition is performed, the result of the addition is 6, and overflow occurs, so 5 is subtracted and the value of the accumulator becomes 1. Since overflow occurs, N '+ 1 division is performed. When the fourth addition is performed, the value of the accumulator becomes 3, and since no overflow has occurred, N 'division is performed. When the fifth addition is performed, the value of the accumulator becomes 5, and since overflow occurs, 5 is subtracted and becomes 0. Since overflow occurs, N ′ + 1 division is performed. Thus, the average division ratio of the 5-minute cycle is N '+ 2/5, and thus N' + 2/5 division is achieved.

However, the above-described fractional frequency divider produces an error corresponding to the value of the accumulator. This error may be corrected by estimating the phase error based on the value of the accumulator and subtracting the error from the output of the phase comparator (eg, 183 in FIG. 34) in the PLL. However, in reality, a low frequency filter (for example, 18 in FIG. 34) in the PLL is used.
4) Match the current of the internal charge pump,
Complete correction is not performed because it is difficult to output the correction at the same time as the output of the charge pump and to scale correctly to the N ′ frequency division number. Therefore, the error corresponding to the value of the accumulator of the fractional frequency divider cannot be ignored and it is necessary to reduce this error.

The present invention has been made to solve the above problems, and an object thereof is to use a counter that operates at the same speed as N division or a programmable frequency divider including the counter to divide N + 1/2. It is to provide a variable frequency dividing device capable of performing frequency division.

Another object of the present invention is to provide a fractional frequency divider having a smaller error than a conventional fractional frequency divider which divides a fraction by combining N frequency division and N + 1 frequency division. is there.

Still another object of the present invention is to use a phase comparator which has a variable frequency dividing circuit capable of dividing by N + 1/2 and which can perform phase comparison only on the rising edge or the falling edge, An object of the present invention is to provide a PLL capable of performing phase comparison at both rising and falling edges of a reference signal.

[0014]

According to the present invention, a programmable frequency dividing means for alternately dividing an input signal by a frequency dividing ratio N (N is an integer) and a frequency dividing ratio N + 1, and an output signal of the programmable frequency dividing means. First signal generating means for generating a first signal synchronized with the input signal, second signal generating means for generating a second signal obtained by delaying the first signal by 1/2 cycle of the input signal, and A variable frequency divider having an output means for alternately outputting a first signal and the second signal.

The present invention also provides a two-modulus prescaler for dividing an input signal by a division ratio M (M is an integer) or a division M + 1, and the division of the two-modulus prescaler by P2.
And a swallow counter section for performing M + 1 division of the 2 modulus prescaler P1 times out of P2 times, and the input signal is divided by a division ratio M × P.
A pulse swallowing means for dividing the frequency by 2 + P1, and when the pulse swallowing means is set to a mode with a division ratio N, M
× P2 ′ + P1 ′ frequency division is performed, and when the mode is set to the frequency division ratio N + ½, M × P2 ′ + P1 ′ frequency division and M ×
Control means for alternately performing P2 '+ P1' + 1 frequency division, first signal generating means for outputting a first signal in synchronization with the output of the course counter section, and the first signal for the input signal Second signal generating means for outputting a second signal delayed by ½ cycle, and selecting the first signal when set to a mode of frequency division ratio N, and a mode of frequency division ratio N + 1/2 The variable frequency divider further includes output means for alternately outputting the first signal and the second signal when set to 1.

The present invention also provides a dividing means for dividing by a dividing ratio N or a dividing ratio N + 1/2 according to a given integer N and given integers N ', B and C (where B < C), N'and N '+ 1 are given to the dividing means to perform N'division or N' + 1 division, and / or N'to the dividing means to give N '. A variable frequency divider having a control means for performing +1/2 frequency division and controlling the frequency division means such that the average of the frequency division ratios of the C frequency division of the frequency division means is N ′ + B / C. It is provided.

The present invention further includes a fixed frequency divider which divides P by a frequency division ratio P with an integer fixed value, and an output of the fixed frequency divider N / P with N an integer variable value. A variable frequency divider having a variable frequency divider for frequency division.

The present invention further includes a voltage controlled oscillator, a variable frequency divider for dividing the output of the voltage controlled oscillator by a frequency division ratio of N + 1/2 (N is an integer), and an output pulse of the variable frequency divider. With an odd number and an even number, a first phase comparator that compares the phase of the reference signal with the phase of the odd number pulse, an inverting means that inverts the reference signal, and an output of the inverting means. A second phase comparator that compares the phases of the even-numbered pulses, and the outputs of the first phase comparator and the second phase comparator are converted into control voltages and input to the voltage controlled oscillator. And a low frequency filter.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a variable frequency divider according to an embodiment of the present invention, and FIG. 3 is an operation explanatory diagram of FIG.

The signal P0 (fi) is a signal input to the variable frequency divider, and for example, a signal of a local oscillation frequency (fo) supplied from a voltage controlled oscillator (VCO) or it is shown in FIG. It is divided by a non-prescaler (for example, the one indicated by reference numeral 25 in FIG. 7). The signal P0 is a clock pulse whose ON / OFF times are equal to each other, as shown in FIG. A programmable frequency divider 1 has a presettable counter circuit 2 and a coincidence circuit 3. The counter circuit 2 uses, for example, signals J1 to J4 (1 (H
High) or 0 (Low)) and the signal at the terminal PE becomes High, a preset value is loaded and the countdown of the input pulse applied to the terminal CP is started with the preset value as an initial value. In the following description, a pulse input to the variable frequency divider, that is, the terminal C in the embodiment of FIG.
The pulse applied to P is sometimes called the input pulse, and its period is sometimes called the input period (or simply "period").

A counter circuit of a variable frequency divider having a large frequency division ratio which is often used in practice is, for example, as shown in FIG.
Multiple decimal down counters 2 (3 in FIG. 2)
Input terminals Ja1 to Ja4, Jb1 to Jb4, Jc1 to Jc are formed by connecting a, 2b, and 2c in cascade.
4 (each signal of High = 1 or Low = 0) is given each digit (4 bits each) of the preset value represented by the binary coded decimal code, but as shown in FIG. , The preset value is represented by 4-bit signals J1 to J4.

The coincidence circuit 3 has a terminal E1 of the counter circuit 2.
The detection output P1 becomes H (High) when the output of E4 becomes a predetermined value, for example, "2".

The D-flip-flop 4 outputs a signal P2 obtained by delaying the output P1 of the coincidence circuit 3 by one input cycle of P0 using P0 as a clock pulse.

The inverter 5 is a D-flip-flop 4
Outputs a signal that is the inverted output of. Here P0 is
Since the clock pulses have the same ON / OFF time, P3 is shifted by 1/2 the input period with respect to P0. The D-flip-flop 6 is the inverter 5
Is used as a clock pulse to output a signal P4 obtained by delaying the output P2 of the D-flip-flop 4 by one cycle of P3. Since P3 is shifted by ½ input period with respect to P0, P4 is delayed by ½ input period of P0 with respect to P2.

The D-flip-flop 7 receives the output P2 of the D-flip-flop 4 as P by using P0 as a clock pulse.
The signals P5 delayed by one cycle of 0 and the signal P6 obtained by inverting the signal P5 are output.

The D-flip-flop 8 uses the inverted output P6 of the D-flip-flop 7 as a clock pulse, and feeds back the inverted output P8 as an input signal.
ON / OFF (High to L
signal P that repeats (low, inversion from Low to High)
7 and P8 are output.

The logic circuit 9 alternately outputs pulse signals having a one-input cycle difference, and has three NAND gates 1
0, 11, and 12 are provided, and the output P2 of the D-flip-flop 4 and the output P5 of the D-flip-flop 7 are alternately selected in synchronization with the outputs P7 and P8 of the D-flip-flop 8 to output the signal P11. Is output as a preset signal. Since P2 and P5 are shifted by one input cycle, P11
Is a pulse signal in which N division and N + 1 division are alternately repeated. The preset signal P11 is input to the preset terminal PE of the counter circuit 2.

The logic circuit 13 outputs a pulse divided by N + 1/2 and has three NAND gates 1
4, 15 and 16 in synchronization with the outputs P7 and P8 of the D-flip-flop 8 and the output P2 of the D-flip-flop 4 and the output P4 of the D-flip-flop 6 alternately (every 1 minute cycle). ), And outputs the selection signal P14 as a frequency division signal. Since the ON / OFF times of P7 and P8 are different by 1 minute cycle, and P2 and P4 are shifted by 1/2 input cycle, P14 becomes a pulse signal of N + 1/2 frequency division. This signal P14 (frequency fv) is input to the phase comparator as an output signal of the variable frequency divider.

The operation of the above apparatus will be described in detail with reference to FIG. In order to cause the above frequency divider to perform N + 1/2 division, the signals J1 to J4 are set to indicate the preset value N. In the following description, it is assumed that N = 7. The input signal P0 (fi) is input to the counter circuit 1, and when the coincidence circuit 3 detects "2", the detection signal P1 is output.
The output P2 of the D-flip-flop 4 is delayed by one input cycle from P1. The output P4 of the D-flip-flop 6 is delayed from the output P3 of the inverter by 1/2 the input period from P2.
The outputs P5 and P6 of the D-flip-flop 7 are 1 from P2.
Input cycle is delayed. The output P7 of the D-flip-flop 8,
P8 turns ON / OFF (Hi
Inversion from gh to Low and Low to High) is repeated.

P9 is a NAND output of P2 and P7, and is OFF only when P7 is ON and P2 is ON. In other words, while P7 is ON, P2 is ON and P9.
Is detected by P10 is a NAND output of P5 and P8, and is OFF only when P7 (inversion of P8) is OFF and P5 (P2 delayed by one input cycle) is ON.
It is. In other words, P10 detects ON of P5 while P7 is OFF. P11 (PE) is P9 and P1
0 output of NAND, P2 ON signal, P5
The ON signals (those obtained by delaying P2 by one input cycle) are alternately output. The programmable frequency divider 1 is preset by this signal P11 and counts down from "7" as shown in FIG. At this time, by continuing the ON time of P11,
The count of "7" continues for two input cycles. That is, 7, 7, 6, 5, until the next preset ON signal is received.
Continue counting down with 4, ... Thus, the preset signal has N (= 7) input periods and N + 1 (=
8) Generated at alternating intervals of the input period. In order to delay the preset from the preceding preset to the (N + 1) th input cycle, a pulse (P5) delayed by one input cycle from the pulse (P2) generated in the Nth input cycle is used.

P12 is a NAND output of P2 and P7, and is a signal for detecting ON of P2 while P7 is ON,
O only when P7 is ON and P2 is ON
It becomes FF. In other words, P2 is ON while P7 is ON.
Is detected by P12. P13 is NA of P4 and P8
ND output, P4 (P2 is 1 /
(Phase delayed by 2 input cycles) is detected.
It is OFF only when (inversion of P8) is OFF and P4 (P2 delayed by 1/2 input cycle) is ON. In other words, while P7 is OFF, P4 ON is P1
3 is detected.

P14 (fv) is a NAND of P12 and P13
As outputs, P2 and P4 (P2 delayed by 1/2 input cycle) are alternately selected and output as P14. The resulting signal P14 is the N + 1/2 divided signal. Because, every 2N + 1 input cycles, 2
There are two pulses, and one division cycle of each two divisions has (P
This is because a pulse that is delayed by 1/2 input period is selected (for the formation of P14) and a pulse that is not delayed (for the formation of P14) is selected for the other one-minute period of the two-minute period. .

As described above, the variable frequency divider of the present embodiment alternates the pulse generated in the Nth input cycle from the preceding preset and the pulse generated in the N + 1th input cycle from the preceding preset. Means (logic circuit 9) for selecting and presetting the programmable frequency divider by the selection pulse (P11), a signal synchronized with the output of the programmable frequency divider, and a signal obtained by shifting the signal by 1/2 the input period are alternated. And means for outputting the selection signal (P14) as a frequency-divided signal (logic circuit 13).

As can be seen from the above description, the programmable frequency divider 1 is preset by using the signal shifted by one input period, not the signal shifted by 1/2 input period. Therefore, even if the counter circuit 2 of the programmable frequency divider 1 does not operate at double speed, N + 1/2 frequency division is possible. That is, the counter circuit 2 may operate at the same speed as in the case of dividing by N.

FIG. 4 is a block diagram showing a schematic configuration of a variable frequency divider according to another embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same or corresponding members and signals.

The variable frequency divider of FIG. 4 is generally the same as the variable frequency divider of FIG. The difference is that the signal J0 instructing the frequency division mode is input to the PE terminal of the D-flip-flop 8. The signal J0 is H (High) when N + 1/2 is instructed and L (Low) when N frequency division is instructed. When the signal J0 is H, P6
ON / OFF synchronized with the rise of (CP terminal input)
The signals P7 and P8 are repeated, and when the signal J0 is L, the signal P7 maintains H and the signal P8 maintains L.

N + 1 of the variable frequency divider having the above configuration
The operation of 1/2 frequency division will be described. The signals J1 to J4 are set to indicate N as in the case of FIG. J0 input to the PE terminal of the D-flip-flop 8 is H (Hi
gh), and the mode is set to the N + 1/2 frequency division mode. The operation at this time is similar to that described with reference to FIG. 1, and the variable frequency divider 1 outputs the signal P0 having the input frequency fi.
Is divided by a dividing ratio N + 1/2.

Next, the operation of dividing the variable frequency divider by N will be described with reference to FIG.
It will be described based on. Also at this time, the signals J1 to J4 are set to indicate N. J0 input to the PE terminal of the D-flip-flop 8 is L (Low) and is set to the N frequency division mode.

Therefore, when the input signal P0 (fi) is input to the counter circuit 2 and the matching circuit 3 detects "2", the detection signal P1 is output. D-flip-flop 4
Output P2 is delayed by one input cycle from P1. The output P4 of the D-flip-flop 6 is delayed from the output P3 of the inverter 5 by 1/2 the input period from P2. The outputs P5 and P6 of the D-flip-flop 7 are delayed from P2 by one input cycle. D-
The output P7 of the flip-flop 8 is always H and P8 is always L.

P9 is the NAND output of P2 and P7, but since P7 is always H, P9 becomes a negative signal of P2. P10 is the NAND output of P5 and P8.
Is always L, so P10 is always H. P11
(Input to the PE terminal of the counter circuit 2) is P9 and P
Although it is the NAND output of 10, P11 is the same as P2 because P9 is the negation of P2 and P10 is always H. The counter circuit 2 is preset by this signal P11 and counts down from "7" as shown in FIG. At this time, the count of "7" continues for two times due to the continuation of the ON time of P11. That is, until the next preset ON signal is received, the countdown continues to "7, 7, 6, 5, 4, ..." When P2 becomes "2", P2 turns ON again.
Becomes

P12 is a NAND output of P2 and P7. Since P7 is always H, P9 becomes a negative signal of P2. P13 is the NAND output of P4 and P8.
Is always L, so P10 is always H. P14
(Fv) is the NAND output of P12 and P13, but P1
P1 because 2 is the negation of P2 and P13 is always H
4 becomes the same as P2, and P14 becomes a signal of N frequency division.

As described above, P of the D-flip-flop 8
When J0 input to the E terminal is L, the variable frequency divider divides the input signal P0 having the frequency fi by the frequency division ratio N. Therefore,
The variable frequency divider according to the embodiment of FIG. 4 has a frequency division ratio N + 1 /
The frequency division can be selectively performed by either 2 or the frequency division ratio N.

Similarly to FIG. 1, the output P14 (fv) shifted by 1/2 input cycle is not fed back to the programmable frequency divider 1 as a preset signal, and P is not shifted by 1/2 input cycle.
11 is used for presetting. For this reason, the counter circuit 2 of the programmable frequency divider 1 may operate at the same speed as in the case of N frequency division, even if the frequency division is N + 1/2.

Next, as a first application example of the variable frequency divider of FIG. 4, an example of configuring a PLL using the variable frequency divider of FIG. 4 will be described with reference to FIG.

The variable frequency divider 21 is the variable frequency divider of FIG. 4, and can selectively perform frequency division by the frequency division ratio N or frequency division by the frequency division ratio N + 1/2. The variable frequency divider divides the local oscillation frequency fo by the division ratio NA to obtain the reference frequency fo
In the case of the conventional variable frequency dividing device in which the frequency division ratio N + 1/2 is impossible to obtain the frequency fv controlled to be equal to and in phase with each other, the frequency division ratio NA is changed by one. On the other hand, in the variable frequency divider of the present embodiment, the frequency division ratio can be changed by 0.5. Therefore, the local oscillation frequency can be doubled (2fo) and the frequency division ratio NA can be halved (NA / 2). This can be expressed as follows.

First, NA = (2N + 1) / 2 = ((N +
By considering 1/2) × 2) / 2, fo = NA ×
fr becomes fo = (NA / 2) × 2fr. This will be described by applying to the AM band. AM band is 522K
Hz to 1629 KHz, with an intermediate frequency fm of 45
If 9 KHz is used, the sweep range is 522 KHz + 45
9KHz-1629KHz + 459KHz = 981KH
z to 2088 KHz. In the present embodiment, the reference frequency is 18 KHz, and the frequency division ratio is changed by 0.5 in the range of 54.5 to 116. On the other hand, in the conventional configuration, the reference frequency is set to 9 KHz, and the frequency division ratio is changed by 1 in the range of 109 to 232.

Thus, the frequency division ratio is halved and the reference frequency is doubled, so that the loop gain is increased and the lockup time is shortened.

FIG. 7 is a block diagram showing a second application example, and FIG. 8 is a block diagram showing a conventional example equivalent to FIG. In an FM radio receiver having a high frequency, the oscillation output required by the local oscillator is usually near the operating speed limit of the TTL or C-MOSIC that constitutes the programmable frequency divider, which makes designing difficult. The prescaler method is used for this purpose. As shown in FIG. 8, the conventional prescaler system halves the frequency of a local oscillation frequency fo by a fixed frequency divider 25 to a programmable frequency divider 2 of a variable frequency divider 27.
I was entering 1. Then, as the correction of the fixed frequency divider 25, the fixed frequency divider 26 is added to halve the reference frequency fr input to the phase comparator 22.

4 is used as the variable frequency divider 21 of FIG. 7, a frequency division ratio of N + 1/2 is possible. Therefore, even if the fixed frequency divider 25 is added as shown in FIG. Remains fr and the fixed frequency divider 26 can be omitted. That is, the operating frequency of the variable frequency divider 27 can be doubled. Moreover, if the same operating frequency is used, power consumption can be reduced.

As described above, the variable frequency dividing device 21 capable of the frequency dividing ratio N + 1/2 has many applications. It can be embedded in the PLL,
The variable frequency dividing device 21 capable of the frequency dividing ratio N + 1/2 is not limited to that shown in FIG. 4, but may be, for example, a method of inverting the local oscillation frequency fo (FIG. 35). However, the conventional variable frequency divider has a problem in that the built-in counter must be capable of operating at a high frequency. The variable frequency divider of the present embodiment can solve this problem as described above.

FIG. 9 is a block diagram showing the configuration of a variable frequency divider according to still another embodiment of the present invention. The same reference numerals as those in FIGS. 1 and 4 denote the same or corresponding members and signals.

The adder 31 receives the same input signals J1 to J4 as those shown in FIGS. 1 and 4 at the input terminals B1 to B4, and when the signal P24 (described later) input to the terminal A is low, the terminals B1 to B4.
The value N represented by the signals J1 to J4 representing N input to the counter 4 is directly supplied to the preset value input terminals D1 to D4 of the counter circuit 2 through the output terminals C1 to C4,
When P24 is High (1), a value obtained by adding "1" to the set value N represented by the signals J1 to J4 is output terminals C1 to C1.
Preset value input terminal D of the counter circuit 2 via C4
1 to D4. Similar to the embodiment of FIGS. 1 and 4,
When dividing N + 1/2 and N, J1 to J4 are N
Is set to indicate.

The counter circuit 2 uses the input signal P0 (fi) as a clock pulse and counts down using the preset value (N or N + 1) supplied to the terminals D1 to D4 as an initial value. The counter circuit 2 is preset when a later-described signal P25 applied to the terminal PE becomes High.

The D-flip-flop 34 uses P1 as a clock pulse, and its inverted output P24 is A of the adder 31.
It is returning to the input terminal. When the signal J0 input to the terminal PE is Low, a signal P23 that repeats ON / OFF in synchronization with the rising of P1 is output from the terminal Q, and an inverted signal P24 of P23 is output from the terminal inversion Q. . When the signal J0 is High, P23 is High
And P24 becomes Low.

The D-flip-flop 35 outputs from the terminal Q a signal P25 obtained by delaying the output P1 of the coincidence circuit 3 by one input cycle (one cycle of P0) using P0 as a clock pulse.

The inverter 36 outputs a signal P26 which is an inversion of P0. Since P0 is a clock pulse whose ON / OFF time is equal to each other, P26 is P
A shift of 1/2 the input period will be made for 0.

Since the D-flip-flop 37 uses P26, which is shifted by 1/2 input cycle with respect to P0, as a clock pulse, a signal P27 obtained by delaying P25 by 1/2 input cycle is applied from the terminal Q. Output.

The NAND gate 38 outputs a signal P28 which is a NAND output of P23 and P25. The NAND gate 39 outputs a signal P29 which is the NAND output of P24 and P27. NAND gate 40 has P28 and P
The signal P30 (fv) which is the NAND output of 29 is output. P30 synchronizes with P23 and P24, and P25 and P27
Are output alternately. That is, the selection circuit 41 composed of the three NAND gates 38, 39 and 40 is D-
The two signals P25 and P27 are alternately switched and output depending on the output cycle of the flip-flop 34.

The operation of the variable frequency divider having the above configuration will be described. The variable frequency divider performs N + 1/2 division when J0 is Low (“0”) and N division when J0 is High (“1”).

First, the operation of N + 1/2 frequency division (here, 5.5 frequency division) will be described with reference to FIG.

J0 is "1", J1 to J4 are set values "N =
5 ”. First, when P24 is Low, this set value "N = 5" is directly input to the counter circuit 2, and the counter circuit 2 sets P5 as an initial value to P0.
Count down the pulse of. On the other hand, P24 is High
If it is h, "6" which is obtained by adding "1" to "5" is supplied to the counter circuit 2, and the counter circuit 2 counts down from "6". When “2” is detected by the matching circuit 3,
The detection signal P1 that becomes High at "2" is output.

First, it is assumed that P24 is Low. D-
As for the outputs P23 and P24 of the flip-flop 34, J0 is L
Since it is ow, Low / is synchronized with the rising edge of P1.
Repeat High. The output P25 of the D-flip-flop 35 is delayed by one input cycle from P1. P25 High
Presets the counter circuit 2. The output P27 of the D-flip-flop 37 is delayed from the input P26 of the inverter 36 by 1/2 the input period from P25.

The output P28 of the NAND gate 38 is P23.
And the NAND output of P25, and the pulse of the signal P25 delayed by one input cycle from P1 is extracted. The output P29 of the NAND gate 39 is the NAND output of P24 and P27, and extracts the pulse of the signal P27 which is delayed by ½ input period from P25. Output P30 (f of NAND gate 40
v) is the NAND output of P28 and P29, and the pulses of P25 and P27 are combined, that is, they are alternately selected in synchronization with the D-flip-flop 34 to form P30.

Since P24 is input to the terminal A of the adder 31, when P24 is Low, P25 is Hi.
When it becomes gh, the counter circuit 2 is preset to 5 and P
When P25 becomes High when 24 is High, the counter circuit 2 is preset to "6". Therefore, the count of the counter circuit 2 is 5, 5, 4, 3, 2, 6, 6,
Repeat steps 5, 4, 3, and 2. Thus, when J0 is "0", the counter circuit 2 counts down to 2
Then, the preset is switched from "5" to "6" or from "6" to "5". Then, when the preset is "5" (division by 5), the High of the detection signal P25 of "2" synchronized with the rise of P0 is extracted, and when the preset is "6" (division by 6), the rise of P0 is extracted. High of P27 which is synchronized with the falling and is delayed by a half cycle from P25 is extracted. By such alternate extraction, pulses are obtained every 5.5 input cycles. That is, the frequency division is performed by 5.5. That is, when J0 is "0", the variable frequency divider can divide the input signal P0 having the frequency fi by the division ratio N + 1/2.

In the above example, the initial value of P24 is set to Low.
However, when the initial value of P24 is High, the first preset value of the counter circuit 2 becomes "6", and P27
Is selected first, but otherwise the same operation is performed.

Next, the operation of dividing by N (in this case, dividing by 5) will be described with reference to FIG.

J0 is a signal representing "1" (High), and J1 to J4 are signals representing "5", which are input to the counter circuit 2 and the value thereof is supplied from the adder 31 to the counter circuit 2. The counter circuit 2 counts down P0, and when the coincidence circuit 3 detects "2", the detection signal P1 becomes High.
Becomes Since J0 of the D-flip-flop 34 is High, P23 becomes High and P24 becomes Low. P24 input to the terminal A of the adder 31 is always L
Since it is ow, the preset value of the counter circuit 2 is always 5. In addition, P23 is always High, P2
Since 4 is always Low, the selection circuit 41 continues to select P25. That is, P30 (fv) is the same as P25.

Similar to the description of N + 1/2 division, P25 is one input cycle later than P1, and P25
The counter circuit 2 is preset by 25 pulses.

Thus, when J0 is "1", D-
The flip-flop 34 operates so that the counter circuit 2 is always divided by 5, and the selection circuit is always selected so as to select P25. That is, when J0 is "1", the variable frequency divider can divide the input signal P0 having the frequency fi by the division ratio N.

As described above, the variable frequency divider uses the signal (J0).
Thus, the operation of dividing by N and dividing by N + 1/2 can be switched. This switching is performed at a predetermined timing (for example,
Immediately after the signal of P25 or P27 becomes Low).

As a result, the frequency division ratio can be changed by 1/2. Therefore, as in the case of the embodiment shown in FIG. 4, the division ratio is halved and the reference frequency is 2
Since it is doubled, the loop gain is increased and the lockup time is shortened.

Also in the present embodiment, since the pulse shifted by 1/2 the input period is not used for presetting the counter circuit 2, the counter circuit is divided into N + 1/2 even if the division ratio is N + 1/2. It can operate at a speed similar to the division ratio.

Next, another embodiment in which the embodiment of FIG. 9 is adapted to the pulse swallow system will be described. In recent years, the pulse swallow system has been used for FM and shortwave broadcast receivers.
This principle is shown in FIG. Reference numeral 46 denotes a 2-modulus prescaler, which has a division ratio M (M is a positive integer) or a division ratio M + 1.
Frequency division. The total number of times of the one cycle is the frequency division ratio P2 set in the course counter 48, and of these, the number of times M + 1 frequency division is performed is the frequency division ratio P1 set in the swallow counter 47.

Therefore, the division ratio of one cycle is (M + 1)
× P1 + M × (P2-P1) = M × P2 + P1.
Here, P2 ≧ P1. In this way, in the pulse swallow variable frequency divider, the frequency division ratio can be variously changed by changing P1 and P2. Moreover, the frequency division number of the programmable frequency divider operating at a high frequency is only switched between two types (M and M + 1), the propagation delay time can be reduced, and the operation speed is improved.

If M = 10, the frequency division ratio is 10 × P2.
+ P1 and P1 represents the value of 1's place, and P2 (P
If 2 ≦ 9), it becomes a two-digit number representing the value of the tens digit.

By applying the circuit described with reference to FIG. 9 to the above-mentioned pulse swallow method, it is possible to obtain a variable frequency divider capable of performing frequency division with a frequency division ratio M × P2 + P1 + 1/2.

Hereinafter, M = 10, P2 = 5, and P1
= 2, a pulse swallow-type variable frequency divider that performs 52.5 or 52 division will be described. FIG. 13 is a block diagram showing the configuration of this embodiment. The same components as those of FIG. 9 are designated by the same reference numerals, and the description thereof will be omitted.

To the variable frequency divider, a signal J0 which becomes "0" when N + 1/2 division is performed and becomes "1" when N division is performed, and a signal which designates a lower division ratio P1. J1
To J4 and signals J5 to J8 designating the higher division ratio P2
And the input signal P0 (fi) is input. J0 to J8 are L
ow (“0”) or High (“1”) signal, P
0 is a pulse signal whose Low / High times are equal to each other.

51 is a two-modulus prescaler,
When the signal R4, which will be described later, input to the terminal 10/11 is High, a signal R2 obtained by dividing the input signal P0 by 10 is output,
If it is ow, the signal R2 divided by 11 is output. 52 is an OR gate, which is a signal R3 which is the logical sum of R2 and R4
Is output. Reference numeral 53 is an adder, and when the signal R7 input to the terminal A is Low, the set values of the signals J1 to J8 input to the terminals B1 to B8 are directly used in the swallow counter 54.
And to the course counter 55. When R7 is High, the value obtained by adding "1" to the set values of J1 to J4 is P1.
Is supplied to the swallow counter 54 via the terminals C1 to C4. If there is a carry along with the addition, J5
1 is also added to the set value of J8. Such a carry is P
The number of digits of 2 (when expressed in decimal) is (10
This occurs when the number of digits is larger than the number of digits (when expressed in a decimal number), for example, P2 has two digits and P1 has one digit.

The swallow counter 54 counts down R3 with the set value input from the adder 53 as an initial value,
The coincidence circuit 56 outputs a signal R4 which becomes High when "0" of the swallow counter 54 is detected. The course counter 55 and the coincidence circuit 57 (2 detections) correspond to the counter circuit 2 and the coincidence circuit 3 in the embodiment of FIG. 9, respectively, and detailed description thereof will be omitted.

D-flip-flops 58, 59 and 60 are respectively D-flip-flops 34 and 34 in the embodiment of FIG.
35 and 37, and detailed description thereof is omitted. The clock pulse of the D-flip-flop 59 is R2, and its output R8 is input to the PE terminals of the coarse counter 55 and the swallow counter 54.

The clock pulse of the D-flip-flop 60 is the output R10 of the D-flip-flop 62 which receives the inverted signal R9 of P0 inverted by the inverter 61 as a clock pulse and inputs R2. This makes (1) D
The output R11 of the flip-flop 60 lags the output R8 of the D-flip-flop 59 by a half cycle of P0.

Because of the connection as described above, when J0 is Low, when the swallow counter 54 counts down to 0, the 2 modulus prescaler 51 becomes 11
Divide from 10 to 10. That is, (2) swallow counter 5
Divide by 11 by the preset value of 4 (the number of times given by).

Further, R4 becomes High and is kept High until it is preset by R8. R4 and R
The frequency division is continued by the logical sum output R3 of 2. This R8 is obtained by delaying the signal R5 which becomes High when the value of the course counter 55 becomes "2" by one cycle of R2. Therefore, (3) the frequency division is performed 10 times by subtracting the preset value (2 or 3) of the swallow counter 54 from the preset value (5) of the course counter 55.

According to the above (1), (2), and (3), when J0 is "0", the division ratio M × P2 + P1 + 1/2, and when J0 is "1", the division ratio M × The frequency division can be performed by P2 + P1.

Incidentally, FIG. 14 shows the configuration of 52. of the embodiment of FIG.
It is a figure which shows 5 division operation, at this time, J0 is "0", J
1 to J4 are "2", and J5 to J8 are "5". FIG.
FIG. 14 is a diagram showing a divide-by-52 operation of the embodiment of FIG.
At this time, J0 is "1", J1 to J4 are "2", J5 to J
8 is "5".

As described above, the embodiment of FIG. 9 can be applied to the pulse swallow system. That is, even if the pulse swallow method is used, the matching circuit 57 of the course counter 55 is used.
The signal R7 whose state is inverted on the basis of the output R5 from 1 is used to add 1 by the adder at intervals of 1 minute to alternately output M × P2 + P1 frequency division and M × P2 + P1 + 1 frequency division. By alternately outputting a signal R8 synchronized with R5 and a signal R11 obtained by delaying R5 by 1/2 cycle of the input signal P0, M × P2 + P
1 + 1/2 frequency division can be performed.

FIG. 16 is a block diagram showing the structure of a variable frequency divider according to still another embodiment of the present invention. Figure 1,
The same reference numerals as those in FIGS. 4 and 9 denote the same or corresponding members and signals.

The OR gate 71 receives P0 and a signal P7 described later.
A signal P62 which is the logical sum of 4 is output. Counter circuit 2
Is a clock pulse P6 input to the terminal CP with the preset value N applied to the input terminals D1 to D4 as an initial value.
2 is counted down, and the count is restarted from the initial value N by Low of a signal P65 described later applied to the terminal inversion PE. The coincidence circuit 3 outputs the detection signal P1 which becomes High when the output of the counter circuit 2 becomes "2".

The D-flip-flop 74 outputs from the terminal Q a signal P64 obtained by delaying the output P1 of the coincidence circuit 3 by one input cycle using P0 as a clock pulse, and outputs a signal P65 obtained by inverting P64 from the terminal inversion Q. To do. The D-flip-flop 75 uses P0 as a clock pulse to generate P6.
A signal P66 obtained by delaying 4 by one input cycle is output from the terminal Q, and a signal P67 obtained by inverting P66 is output from the terminal inversion Q.

The D-flip-flop 76 uses P67 as a clock pulse and feeds its inverted output P69 back to the D input terminal. Then, the signal J0 input to the inverted PE
When is High, it turns on in synchronization with the rising edge of P67.
The signal P68 that repeats ON / OFF is output from the terminal Q, and P
A signal P69 obtained by inverting 68 is output from the terminal inversion Q. When the signal J0 is Low, P68 becomes High and P69 becomes Low.

The inverter 77 outputs a signal P70 which is an inversion of P0. Since P0 is a clock pulse whose ON / OFF time is equal to each other, P70 is P
A shift of 1/2 the input period will be made for 0. D-
The flip-flop 78 outputs from the terminal Q a signal P71 which is obtained by delaying P64 by one cycle with P70 as a clock pulse. Since P70 is shifted by 1/2 the input period with respect to P0, P71 is 1/2 with respect to P64.
The input cycle will be delayed.

The D-flip-flop 79 is a signal P obtained by delaying P66 by one input cycle using P0 as a clock pulse.
72 is output from the terminal Q. AND gate 80 has P7
A signal P73 which is the logical product of 2 and J0 is output. AND
The gate 81 receives the signal P7 which is the logical product of P73 and P68.
4 is output.

The NAND gate 82 outputs a signal P75 which is a NAND output of P64 and P68. The NAND gate 83 outputs a signal P76 which is a NAND output of P71 and P69. NAND gate 84 has P75 and P
The signal P77 which is the NAND output of 76 is output. P6
In this case, P77 is synchronized with P68 and P69, and P64 and P71 because P8 and P69 are inverse to each other.
It becomes a signal which outputs the pulse of alternately. That is, three N
Selection circuit 8 composed of AND gates 82, 83, 84
5 alternately outputs the two signals P64 and P71 according to the cycle of the D-flip-flop 76.

The operation of the variable frequency divider having the above configuration will be described. N is set in J1 to J4, N + 1/2 division is performed when J0 is "1", and N division is performed when J0 is "0".

First, the operation of N + 1/2 division (here, 5.5 division) will be described with reference to FIG. J0 to J4
Is set to represent "5". In this state, the signal P0 having the frequency fi is input to the OR gate 71. P74
Since the value of is unknown, P62 is considered to be the same as P0 for the time being. When P62 is input to the counter circuit 2 and "2" is detected by the coincidence circuit 3, the detection signal P1 which becomes High at "2" is output.

The output P64 of the D-flip-flop 74,
P65 lags behind P1 by one input cycle. Low of P65 causes the counter circuit 2 to be preset. The outputs P66 and P67 of the D-flip-flop 75 are delayed by one input cycle from P64. Outputs P68 and P6 of the D-flip-flop 76
In J9, since J0 is High, ON / OFF is repeated in synchronization with the rising edge of P67. The output P71 of the D-flip-flop 78 lags behind P64 by 1/2 input cycle because of the output P70 of the inverter 77.

The output P72 of the D-flip-flop 79 is delayed by one input cycle from P66. The output P73 of the AND gate 80 is the logical product of J0 and P72, and J0 is High.
Is the same as P72. The output P74 of the AND gate 81 is the logical product of P68 and P73, and Hi of P73 is output.
Every other gh part becomes a signal deleted by P68.

Therefore, OR which is the logical sum of P74 and P0
The output P62 of the gate 71 is a pulse train similar to P0, but the two pulses in the period of P74 being High are one. Therefore, the preset value of the counter circuit 2 is "5", but the coincidence signal P1 becomes High only after 6 pulses of P0 are input.

Then, the output P75 of the NAND gate 82
Is a NAND output of P64 and P68, and extracts High of P64 with one input cycle delayed from P1. The output P76 of the NAND gate 83 is the NAND output of P71 and P69.
Extract gh. The output P77 of the NAND gate 84 is P
These are the NAND outputs of P75 and P76, and combine the extraction units of P75 and P76. That is, as described above, P77 is D-
It becomes a signal for alternately outputting P64 and P71 in synchronization with the flip-flop 76. Since P64 and P71 are shifted by 1/2 input cycle, P77 is divided by 5.5.

In this way, when J0 is 1, the variable frequency divider can frequency-divide the input signal P0 with the frequency division ratio N + 1/2.

Next, the operation of dividing by N (in this case, dividing by 5) will be described with reference to FIG. J0 is set to "0" and J1 to J4 are set to "5". In this state, the input signal P0 (fi) is input to the OR gate 71.

Since J0 is Low, the output P73 of the AND gate 80 becomes Low. A because P73 is Low
The output P74 of the ND gate 81 becomes Low.

Since P74 is Low, the OR gate 7
The output P62 of 1 becomes the same as P0. Therefore, J0 is 1
The rising edge of the pulse of P0 is not decreased by one as in the case of. That is, every time five pulses of J0 are input, the coincidence signal P1 becomes High, and the counter circuit 2 is preset by the signal P65 which is delayed by one input cycle, and the countdown with "5" as the initial value is started.

Further, since J0 is "0", the output P68 of the D-flip-flop 76 is kept High and P0
69 is kept low. Therefore, the signal P64 obtained by delaying P1 by one input cycle continues to be selected and becomes P77 (fv).

Therefore, P77 is the same as P1 and P64,
It consists of pulses generated every 5 input cycles,
It is a signal divided by 5.

As described above, when J0 is 0, the variable frequency divider can divide the input signal P0 having the frequency fi by the division ratio N.

As described above, the variable frequency divider shown in FIG. 16 can also switch between the N frequency division and N + 1/2 frequency division operations by the signal J0. This switching is a predetermined timing (for example, immediately after the signal of P77 becomes Low)
Done in

Next, still another embodiment in which the embodiment of FIG. 16 is adapted to the pulse swallow system will be described with reference to FIG. The same components as those of FIG. 16 are denoted by the same numbers with “′” added, and description thereof is omitted.

To the variable frequency dividing device, a signal J0 for designating whether or not the 1/2 frequency division is performed, signals J1 to J4 for designating a preset value P1 of the swallow counter 93, and a preset value P2 of the course counter 98. Signals J5 to J8 specifying
And the input signal P0 (fi) is input. J0 to J8 are L
ow (“0”) or High (“1”) signal, P
0 is a pulse signal whose Low / High times are equal to each other.

91 is a two-modulus prescaler,
When a signal R25 described later input to the terminal 10/11 is High, a signal R23 obtained by dividing the input signal P0 by 10 is output, and when it is Low, a signal R23 obtained by dividing 11 is output. An OR gate 92 outputs a signal R24 which is a logical sum of R23 and R25.

The swallow counter 93 counts down R24 with the value P1 set by J1 to J4 as an initial value, and the coincidence circuit (0 detection) 94 becomes a signal R25 which becomes High when "0" of the swallow counter 93 is detected. Is output. The course counter 98 counts down R23 with the value P2 set by J5 to J8 as an initial value,
The coincidence circuit (2 detection) 99 is "2" of the course counter 98.
The signal R26 which becomes High when is detected is output.

The clock pulse of the D-flip-flop 74 'is R23, and its inverted output R28 is input to the PE terminals of the coarse counter 98 and the swallow counter 93.

The clock pulse of the D-flip-flop 78 'is the output R34 of the D-flip-flop 95 which receives the inverted signal R33 of P0 inverted by the inverter 77' as a clock pulse and inputs R23. As a result, (1) the output R35 of the D-flip-flop 78 'is D
-Has a delay of half the period P0 from the output R27 of the flip-flop 74 '.

The High time of the signal R36 corresponding to the signal P72 in the embodiment of FIG. 16 is 10 times as long as P0 or 1
Since there is one time, the D-flip-flop 96 using P0 as a clock delays one cycle of P0, and the signals R37 and R36 are logically ANDed by the AND gate 97, and the signal R38 of the same High time as one cycle of P0 is generated. And R38 is OR
It is input to the gate 71 '. As a result, (2) when R40 becomes High, R22 becomes a signal in which one pulse of P0 is deleted.

Because of the connection as described above, when the swallow counter 93 counts down to 0, the 2-modulus prescaler 91 is divided by 11 to 10. That is, (3) the frequency is divided by 11 by the preset value of the swallow counter 93.

Further, since R24 becomes a constant High, the frequency division is continued until preset by R28. Since R28 is a signal which outputs High in the frequency division cycle of the course counter 98, (4) frequency division is performed 10 times by subtracting the preset value of the swallow counter 93 from the preset value of the course counter 98.

According to the above (1), (2), (3) and (4), when J0 is "1", the frequency division ratio is M × P2 + P1 + 1/2, and J
When 0 is “0”, the frequency division can be performed with the frequency division ratio M × P2 + P1.

As described above, the embodiment of FIG. 16 can also be adapted to the pulse swallow system. That is, even if the pulse swallow method is used, the coincidence circuit 9 of the coarse counter 98 is
By deleting the pulse based on the output R26 from 9 as in FIG. 16, frequency division by M × P2 + P1 and M × P2 + P1
The signals R27 and R26 synchronized with R26 are output by 1/2 of the input signal P0.
By alternately outputting the cyclically delayed signal R35, M × P2 + P1 + 1/2 frequency division can be performed.

FIG. 20 is a block diagram showing a schematic configuration of a fractional frequency divider according to still another embodiment of the present invention. The frequency dividing device of this embodiment is capable of performing frequency division by a mixed number N '+ B / C. Reference numeral 101 denotes a variable frequency dividing circuit, which has an N frequency dividing circuit 102 for performing N frequency division and an N + 1/2 frequency dividing circuit 103 for performing N + 1/2 frequency division.

In FIG. 20, the N frequency dividing circuit 102 and the N + 1/2 frequency dividing circuit 103 are shown separately, but this is for convenience of description, and in the embodiment of the invention, the control is performed. A circuit capable of selectively performing N + 1/2 division and N division according to a signal may be used. As such a variable frequency divider, those shown in FIGS. 4, 9 and 16 can be used. Alternatively, the N frequency dividing circuit and the N + 1/2 frequency dividing circuit may be independent circuits and selectively operated by the control circuit. In this case, as the frequency dividing circuit 103 for performing N + 1/2 frequency division, the circuit shown in FIG. 1 can be used.

The control circuit 104 has an accumulator 105 for storing addition data, and has a frequency division ratio N '+ from the outside.
The variable frequency dividing circuit 101 is controlled based on the designation of B / C.
A ROM 106 stores a program for the control circuit 104 to operate. A RAM 107 stores data necessary for the operation of the control circuit 104.

The control circuit 104 receives signals for designating the frequency division ratios N ′, B and C from the outside, operates according to the program stored in the ROM 106, and outputs the signals from the terminals J0 to J4. Control the behavior of.

The signals from the terminals J1 to J4 represent m (a positive integer), and the signal from the terminal J0 is "0".
In the case of, the variable frequency dividing circuit performs frequency division by m.

The signal from the terminals J1 to J4 represents m, and when the signal from the terminal J0 is "1", the variable frequency dividing circuit performs m + 1/2 frequency division.

The control circuit 104 uses N '+ B as described later.
In order to perform the / C fraction, the value of m is set equal to N ', the value equal to N' + 1, or the signal output from J0 is set to "0" or "1".

Next, the fractional frequency dividing operation of this embodiment will be described. FIG. 21 is a flowchart showing the operation of the control circuit 104. The variable I counts the number of frequency divisions and is stored in the register 104a inside the control circuit 104. The variable A is a variable stored in the accumulator 105 and also indicates an error. Variables B and C are the numerator and denominator of the true fraction of the specified mixed fraction division ratio, and R
It is stored in the AM 107.

When the frequency division ratio N '+ B / C is specified, the control circuit 104 stores the variable I as 0 and the variable A as 0, and stores the variables B and C as the true fraction of the specified mixed fraction division ratio. The numerator and denominator of the part are stored (S1). Next, 2 of molecule B
It is determined whether or not the multiplication is less than or equal to the denominator C (whether 2 × B ≦ C or not) (S2), that is, whether or not N ′ + 1 division is required.

If 2 × B ≦ C (Y of S2), the variable I
Is incremented by "1" (S3). Then, the error for the B / C frequency division is added to the variable A (S4). This B
The error divided by / C represents the error when the N'division is performed. It is checked whether the added variable A is smaller than 1/2 (S5). If the variable A is smaller than 1/2, the frequency is divided by N '(S6), and the process proceeds to step S9. If the variable A is ½ or more in step S5, N ′ + ½ frequency division is performed (S7), and ½ is subtracted from the variable A (S
8) and proceeds to step S9. Accumulator 105 is 1
If the overflow is set to / 2, 1/2 will be automatically subtracted. However, in this case, after step S5, the value of the accumulator A becomes 1 /
Since the value is the value obtained by subtracting 2, it is determined in step S5 whether such an overflow has occurred. In step S9, it is checked whether or not the variable I has become C. That is, it is checked whether or not frequency division for one cycle is performed. If the variable I is not C, the process returns to step S3 to perform the next frequency division. If the variable I is C in step S9, the variable I is returned to 0 (S10) and the process returns to step S3.

If 2 × B ≦ C is not satisfied in step S2, the variable I is incremented by “1” (S11). Then, B / C is added to the variable A (S12). It is checked whether the added variable A is smaller than 1 (S13).
If the variable A is smaller than 1, the frequency is divided by N '+ 1/2 (S14), and 1/2 is subtracted from the variable A (S15).
It proceeds to step S18. If the variable A is 1 or more in step S13, N '+ 1 frequency division is performed (S16), 1 is subtracted from the variable A (S17), and the process proceeds to step S18. In step S18, it is checked whether or not the variable I has become C. That is, it is checked whether or not frequency division for one cycle is performed. If the variable I is not C, the process returns to step S11 to perform the next frequency division. If the variable I is C in step S18, the variable I is returned to 0 (S19) and step S11
Return to

It will be explained that the above operation causes the average frequency division ratio of one cycle (frequency division of C times) to be N '+ B / C. First, consider the case of 2 × B ≦ C (S3 to S10). (1) The initial value of A is 0, and the added B / C is 0 ≦ B
/ C≤1 / 2, and 1/2 when A≥1 / 2
Since it is subtracted, the value (error) of A immediately before step S9 is 0 ≦ A <1/2. (2) The sum of the values added to A in S4 during the frequency division of C times is (B / C) × C times = B (integer), while the sum of the values subtracted from A in S8. Is a multiple of 1/2. Therefore, the difference between the added value and the subtracted value (which is equal to the value of A immediately before step S9 at the time when the frequency division of C times is finished) is also a multiple of 1/2. (3) The value of A that satisfies both the above conditions (1) and (2) is only 0.

Therefore, it can be said that the value of A is 0 immediately before step S9 after the frequency division is performed C times. In this way, B is added by the frequency division of C times, so the average frequency division ratio is N ′ +
It becomes B / C.

When 2 × B> C (S11 to S19),
Since the case of 2 × B ≦ C is shifted by ½, the average is similarly N ′ + B / C.

(4) The initial value of A is 0, and the added B / C is 1/2
<B / C <1, and when A <1, 1/2 is subtracted, and when A ≧ 1, 1 is subtracted.
The value (error) of A immediately before 18 is 0 ≦ A <1/2. (5) The sum of the values added to A in S12 while performing C frequency division is (B / C) × C times = B (integer), while S1
5, the sum of the values subtracted from A in S17 is a multiple of 1/2. Therefore, the difference between the added value and the subtracted value (this is the step S1 at the time when the frequency division of C times is completed).
(Equal to the value of A immediately before 8) is also a multiple of 1/2. (6) The value of A that satisfies both the above conditions (4) and (5) is only 0.

Therefore, it can be said that the value of A is 0 immediately before the step S18 after the frequency division is performed C times. In this way, B is added by C divisions, so the average division ratio is N ′.
It becomes + B / C.

In this way, the error is reduced by N '+ 1/2 division or N' + 1 division just before the error exceeds 1/2 division or 1 division. This method can be implemented with a simple structure using the accumulator 105.

FIG. 22 shows the frequency dividing operation of the frequency division ratio N '+ 2/5 by performing N' + 2/5 frequency division by the above-described embodiment and the conventional example (N frequency division circuit and N + 1 frequency division circuit). ) Is a time chart shown in comparison with FIG. FIG. 23 is a table showing operations and errors. FIG. 24 is a diagram similar to FIG. 22, but the division ratio is N ′ + 4/5. 22 to 2
As is clear from FIG. 4, the fluctuation range of the error in this embodiment, that is, the fluctuation range of the phase is half that of the conventional one.

Next, the operation of another example of the control circuit 104 will be described.
This will be described with reference to FIG. If the control circuit 104 of this example is used, the error becomes smaller than that in the case of performing the operation of FIG.

When the frequency division ratio N '+ B / C is designated, the control circuit 104 stores the variable I as 0 and the variable A as 0, and stores the variables B and C as the true fraction of the designated mixed fractional frequency division ratio. The numerator and denominator of the part are stored (S20). 1 is added to the variable I (S21). Then, the B / C frequency division is added to the variable A (S22).

It is checked whether or not the added variable A is smaller than 1/4 (S23). If the variable A is smaller than 1/4, the frequency is divided by N '(S24) and the process proceeds to step S30. If the variable A is 1/4 or more in step S22, it is checked whether or not the variable A is smaller than 3/4 (S25). When the variable A is smaller than 3/4, the frequency division is performed by N '+ 1/2 (S26), and 1/2 is subtracted from the variable A (S27), and the process proceeds to step S30. Variable A is 3/4 in step S25
If it is above, the frequency is divided by N '+ 1 (S28), 1 is subtracted from the variable A (S29), and the process proceeds to step S30.

It is checked in step S30 if the variable I has become C. That is, it is checked whether or not frequency division for one cycle is performed. If the variable I is not C, the process returns to step S21 to perform the next frequency division. If the variable I is C in step S30, the variable I is returned to 0 (S3
1) and returns to step S21.

In this way, the frequency division is performed by calculating in advance which of the N'division, N '+ 1/2 division and N' + 1 division has the smallest error.

It will be described below that the average frequency division ratio of one cycle (frequency division of C times) becomes N '+ B / C by the above operation.

The initial value of the variable A is 0, and A <
When it is ¼, it returns to S21 without being subtracted in the subsequent steps, and when 1/4 ≦ A <3/4 in S23 and S25, 1/2 is subtracted in S27 before returning to S21 and S
23, S25 3/4 ≤ A (1st round 3/4 ≤ A <1)
In this case, 1 is subtracted in S29 and the process returns to S21. Therefore, the value of the variable A immediately before S21 at the time when the first cycle is finished is -1 / 4≤A <1/4. After the second round, S2
It is the same as in the first round except that 3/4 ≦ A <5/4 immediately before 8, so the value of A immediately before S21 after the second cycle is also −¼ ≦ A <1/4. Under these conditions, and considering that 0 ≦ B / C <1, S2 is set regardless of the first and second rounds.
The variable A immediately before 3 is −1 / 4 ≦ A <5/4. S
Considering the conditions of 23 and S24, -1 / 4≤A <1/4, immediately before S24, 1 / 4≤A <3/4, immediately before S26, and immediately before S28. Three
/ 4 ≦ A <5/4, immediately after S27, −1 / 4 ≦ A <
1/4, even immediately after S29, -1 / 4≤A <1/4, so the value of the variable A immediately before S30 is -1 in any case.
/ 4 ≦ A <1/4.

The sum of the values added to the variable A in S22 during the frequency division of C times is B / C × C = B (integer), and the sum of the values subtracted in S27 and S29. Is 1 /
It is a multiple of 2, and the difference between the sum of the added value and the sum of the subtracted value (which is equal to the value of A immediately before step S30 at the time when the frequency division of C times is finished) is also 1/2. It is a multiple. A that satisfies these conditions is 0. That is, the error becomes 0 after every C frequency divisions, and the average of the frequency division ratios is N ′ + B / C.
Becomes

FIG. 26 shows the frequency division operation of the frequency division ratio N '+ 2/5 by performing N' + 2/5 frequency division by the above embodiment and the conventional example (N frequency division circuit and N + 1 frequency division circuit). ) Is a time chart shown in comparison with FIG. As is apparent from FIG. 26, the fluctuation range of the error in this embodiment, that is, the fluctuation range of the phase is less than half that of the conventional one.

Further, as the N + 1/2 frequency division method of the above embodiment, a method other than those shown in FIG. 1, FIG. 4, FIG. 9, and FIG.
For example, as in Japanese Utility Model Publication No. 62-30352, a method of alternately switching between count-down by rising and falling by inversion may be used.

FIG. 27 shows still another embodiment of the present invention.

The variable frequency divider according to this embodiment includes a fixed frequency divider 131 having a frequency division ratio P and a variable frequency divider 1 having a frequency division ratio N / P.
32 and 32 are connected in cascade. As the variable frequency divider 132, the variable frequency dividing device shown in FIG. 1, FIG. 4, FIG. 9, FIG. 13, FIG. Fixed divider 1
Reference numeral 31 performs frequency division at a frequency division ratio equal to the denominator of the fraction representing the frequency division ratio of the variable frequency divider 132. For example, if the variable frequency divider 132 performs N / 2 frequency division as shown in FIG. 1, the frequency division ratio of the fixed frequency divider 131 is 2.

The combination of the fixed frequency divider 131 and the variable frequency divider 132 of FIG. 27 can be used as the fixed frequency divider 25 and the variable frequency divider 21 of the PLL of FIG. An example of the combination of the circuits of FIG. 27 is shown in FIG. 28 (b). In this figure, the same reference numerals as those in FIG. 7 are used for the fixed frequency divider and the variable frequency divider of the variable frequency divider. FIG. 28 (a) is the same as FIG.
A conventional example having the same frequency division ratio as the variable frequency divider of (b) is shown. The variable frequency divider 21 of FIG. 28B has, for example, the configuration of FIG. 1, and includes four frequency dividing elements 21a each having, for example, a T-FF and a frequency division ratio of “2”. ~ 21d
Are subordinately connected. The conventional variable frequency divider 133 equivalent to this has five frequency dividing elements 133a to 133e.
(Each has a division ratio of 2).

Here, the power saving effect will be described. Frequency-dividing elements 21a to 21d and 133a to 13 connected in cascade.
3e has the same speed efficiency with respect to the input frequency of 20 to 30% due to the time delay of the feedback of the preset signal.
About. Therefore, the frequency fo of the VCO output is 30M.
Assuming that the operating speed efficiency is 30% and the operating speed efficiency is 30%, the result shown in FIG.
In the conventional variable frequency divider 133 shown in (a), the five frequency dividing elements 133a to 133e are required to have the ability to operate at 100 MHz. On the other hand, in the variable frequency divider of the present invention shown in FIG. 28 (b), since the fixed frequency divider 25 is not fed back, it suffices that it has the ability to operate at 15 MHz, and the output of the fixed frequency divider 25. The four frequency dividing elements 21a to 21d of the variable frequency divider 21 which inputs (15 MHz) are 50
It only needs to have the ability to operate at MHz.

By adopting such a configuration in which the fixed frequency divider and the variable frequency divider are connected in cascade, the variable frequency divider elements (21a ...
As 21d), a low operating frequency can be used. By doing so, not only a low-cost device can be used, but also power consumption can be reduced. This is because power consumption increases as the operating frequency increases.

Next, the effect of increasing the clock delay will be described. As disclosed in Japanese Utility Model Publication No. 59-31060, a signal for detecting the content of a counter forming a part of a frequency divider is delayed, and this signal is used as a coincidence signal (preset signal) to allow an allowable propagation delay. A frequency extender method has been considered in which the time can be one clock of the input signal. A long allowable propagation delay time means that it can be used with a higher frequency input signal.

FIG. 1, FIG. 4, FIG. 9, FIG. 13, FIG.
The variable frequency divider shown in 9 is a frequency extender system that delays a signal for detecting the contents of the counter. Therefore, when these variable frequency dividers are used as the variable frequency divider shown in FIG. 27, the input to the variable frequency divider is fixed frequency divider 1
31 is input. Therefore, the allowable propagation delay time of the coincidence signal becomes longer according to the frequency division ratio of the fixed frequency divider. For example, in FIG. 28B, since the frequency division ratio of the fixed frequency divider 25 is 2, the allowable propagation delay time of the coincidence signal is doubled.

Further, the effect of being applicable to the EX-OR phase comparator will be described. Since the EX-OR phase comparator is a perfect straight line in the section -π / 2 ≦ φ ≦ π / 2, there is no dead zone in which an error signal is not output even if there is a phase difference, and there is little noise. However, EX-
There is a condition that the output signal of the variable frequency divider input to the OR phase comparator must be a rectangular wave with a duty ratio of 50% (the ON and OFF times are the same). (Reference: Sogo Denshi Publishing, Ken Yanagisawa, "PLL (Phase Locked Loop) Application Circuit", page 24) FIG. 29 is a block diagram showing an adaptation to an EX-OR phase comparator. FIG. 29 is a PLL circuit diagram in which the phase comparator 134 is used for frequency acquisition and the EX-OR phase comparator 135 is used for phase synchronization. As shown in FIG. 30, N /
The output fv ′ of the variable frequency divider 21 that divides the frequency by 2 is not equal to the OFF time because the ON time is one cycle of fi, and the duty ratio is not 50%, as in the conventional N frequency division. But f
By dividing v'with a fixed divider with a division ratio of 2, fv
Will turn ON and OFF repeatedly in one cycle of fv ', resulting in a duty ratio of 50%. Thus, the division ratio is 1
The use of the / 2 variable frequency divider can enable adaptation to the EX-OR phase comparator.

When the PLL is constructed by using the variable frequency divider described in the above embodiment, for example, with reference to FIG. 1, there are the following problems.

That is, the phase comparator 183 (FIG. 34) for comparing the phase of the signal of the reference frequency with the phase of the output of the variable frequency divider operates only on one of the rising edge and the falling edge of the pulse. FIG. 31 shows a PLL having a variable frequency divider 182 configured to generate a rising pulse at a predetermined timing.
It shows the operation of the circuit. In the case of N + 1/2 division, if the odd-numbered (integer division position) pulse of the output pulse fv of the variable frequency divider 182 is matched with the rising edge of the reference frequency fr, the even-numbered (1/2 division position) pulse Since there is a fall of the reference frequency fr, there is a problem that even-numbered phases cannot be compared.

The embodiments described below are to solve the above problems. 32 is a block diagram showing a schematic configuration of the PLL circuit of the present embodiment, and FIG.
FIG. 33 is an operation explanatory diagram of the PLL circuit shown in FIG. 32.

Reference numeral 141 denotes a variable frequency divider, which outputs the output signal P0 (local oscillation frequency) of the voltage controlled oscillator (VCO) 142.
fo) is divided by N + 1/2.

The operation of the variable frequency dividing device 141 is similar to that of the device shown in FIG. 1, in which the signal P0, which is the local oscillation frequency fo, is divided by the division ratio N + 1/2.

Reference numeral 149 denotes a D-flip-flop, which uses the output R54 (fv) of the variable frequency divider 141 as a clock pulse and feeds back its inverted output R56 as an input signal, turning it on in synchronization with the rising edge of R54. It outputs signals R55 and R56 that repeat ON / OFF.

Reference numeral 150 is an AND gate, which includes R54 and R
55 is input and an odd-numbered pulse signal R57 (integer frequency dividing position) of R54 is output. An AND gate 151 receives R54 and R56 and inputs an even number (1/1) of R54.
The pulse signal R58 at the position (divided by 2) is output. Reference numeral 152 denotes a first phase comparator, which is a signal R5 having a reference frequency fr.
9 and the phase of the signal R57, which is an odd number of the output pulse of the variable frequency divider 141, are compared at the rising edge of the pulse. 1
A second phase comparator 53 compares the phase of the inverted signal R60 of the reference frequency fr inverted by the inverter 154 and the phase of the even-numbered signal R58 of the output pulse of the variable frequency divider 141 at the rising edge of the pulse.

155 is a low frequency filter (LPF),
The output of the first phase comparator 152 and the second phase comparator 15
The output of 3 is converted into a control voltage and input to the voltage controlled oscillator 142.

The operation of the PLL circuit having the above configuration will be described with reference to FIG. First, the operation of the variable frequency dividing circuit 141 is as described with reference to FIG. 3 for the circuit of FIG.

Output R5 of D-flip-flop 149
5, R56 is ON / OF in synchronization with the rising edge of R54
Repeat F. R57 is a logical product of R54 and R55 and is an odd-numbered pulse signal of R54. R58 is R
The logical product of 54 and R56 is an even-numbered pulse signal of R54.

The first phase comparator 152 compares the phases of the signals R59 and R57 having the reference frequency fr. That is, R5
The rising positions (A) of the odd-numbered pulses of 4 are compared.

The second phase comparator 153 compares the phases of the signals R60 and R58 which are the inversions of the reference frequency fr. That is, the rising position of the even-numbered pulse of R54 (B)
Compare.

First and second phase comparators 152 and 15
The output of 3 is converted into a control voltage by the low frequency filter 155 and input to the voltage controlled oscillator 2.

As described above, the variable frequency divider having the frequency division ratio N + 1/2 can be applied to the PLL circuit having the phase comparator which can compare only at the rising edge or the falling edge.

The variable frequency dividing device capable of dividing ratio N + 1/2 used in the PLL of this embodiment is not limited to that shown in FIG. 1, but may be any one of FIG. 4, FIG. 9, FIG. 16, FIG. FIG. 27,
The one shown in FIG. 28 may be used, or one conventionally known, for example, a method of inverting the local oscillation frequency fo as disclosed in Japanese Patent Publication No. 51-49540 may be used.

[0172]

According to the present invention, the counter of the programmable frequency divider can operate at the same speed as the frequency division ratio of N frequency division even if the frequency division ratio is N + 1/2. Therefore, it is possible to supply a variable frequency divider capable of performing N + 1/2 frequency division without increasing the operating speed of the programmable frequency divider. Further, it can be easily adapted to the pulse swallow method. Further, in order to obtain the same local oscillation frequency fo as that of the variable frequency dividing device which can only divide the frequency by N, the reference frequency can be set to 2fr, which is twice the frequency division ratio N. Therefore, the loop gain is increased and the lockup time is shortened.

Further, according to the embodiment described with reference to FIG. 20, there is less error as compared with the conventional fractional frequency divider which divides a fraction by combining N frequency division and N + 1 frequency division. A fractional frequency divider can be provided.

Further, according to the embodiment described with reference to FIG. 32, the PLL having the phase comparator which can compare only with the rising edge or the falling edge is provided.
A variable frequency divider having a frequency division ratio N + 1/2 can be applied to the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a variable frequency divider according to an embodiment of the present invention.

FIG. 2 is a block diagram showing details of an example of the counter circuit of FIG.

FIG. 3 is an operation explanatory diagram of the variable frequency divider according to the embodiment of FIG.

FIG. 4 is a block diagram showing a configuration of another embodiment of the present invention.

5 is an operation explanatory diagram of frequency division by 7 according to the embodiment of FIG. 4. FIG.

FIG. 6 is a block diagram showing a PLL using a variable frequency divider according to still another embodiment of the present invention.

FIG. 7 is a block diagram showing a prescaler-type PLL using a variable frequency divider according to still another embodiment of the present invention.

FIG. 8 is a block diagram showing a prescaler PLL using a conventional variable frequency divider.

FIG. 9 is a block diagram showing a configuration of a variable frequency divider according to still another embodiment of the present invention.

FIG. 10 is an operation explanatory diagram of frequency division by 5.5 according to the embodiment of FIG. 9;

FIG. 11 is an operation explanatory diagram of frequency division by 5 according to the embodiment of FIG. 9;

FIG. 12 is a block diagram showing the principle of the pulse swallow method.

FIG. 13 is a block diagram showing a configuration of still another embodiment of the present invention.

FIG. 14 is an operation explanatory diagram of 52.5 frequency division according to the embodiment of FIG. 13;

FIG. 15 is an operation explanatory diagram of frequency division by 52 according to the embodiment of FIG.

FIG. 16 is a block diagram showing a configuration of a variable frequency divider according to still another embodiment of the present invention.

FIG. 17 is an operation explanatory diagram of frequency division by 5.5 according to the embodiment of FIG. 16;

FIG. 18 is an operation explanatory diagram of frequency division by 5 according to the embodiment of FIG. 16;

FIG. 19 is a block diagram showing a configuration of a variable frequency divider according to still another embodiment of the present invention.

FIG. 20 is a block diagram showing a configuration of a fractional frequency divider according to still another embodiment of the present invention.

FIG. 21 is a flowchart showing an example of the operation of the control circuit according to the embodiment of FIG.

22 is a time chart showing N ′ + 2/5 frequency division by the operation of FIG. 21. FIG.

FIG. 23 is a table showing the operation of FIG. 22.

FIG. 24 is a time chart showing N ′ + 4/5 frequency division by the operation of FIG. 21.

FIG. 25 is a flowchart showing another example of the operation of the control circuit according to the embodiment of FIG.

FIG. 26 is a time chart showing N ′ + 2/5 frequency division by the operation of FIG. 25.

FIG. 27 is a block diagram showing a variable frequency divider according to still another embodiment of the present invention.

FIG. 28 is a block diagram showing a variable frequency divider according to still another embodiment of the present invention.

FIG. 29 is a block diagram showing a variable frequency divider according to still another embodiment of the present invention.

FIG. 30 is a time chart showing the operation of FIG. 29.

31 is an operation explanatory diagram of a PLL circuit incorporating the variable frequency divider of FIG. 1. FIG.

FIG. 32 is a diagram showing P in still another embodiment of the present invention.
It is a block diagram which shows the structure of LL circuit (it equipped with the variable frequency divider of FIG. 1).

FIG. 33 is an operation explanatory diagram of the PLL circuit according to still another embodiment of the present invention.

FIG. 34 is a block diagram showing a configuration of a PLL using a conventional variable frequency divider.

FIG. 35 is a block diagram showing a configuration of a conventional variable frequency divider.

FIG. 36 is an explanatory diagram of the operation of the conventional variable frequency divider.

[Fig. 37] Fig. 37 is a table showing the operation of frequency division by 2/5 in the conventional fractional frequency divider.

[Explanation of symbols]

 1 Programmable frequency divider 2 Counter circuit 3 Matching circuit 4 D-flip-flop 5 Inverter 6 D-flip-flop 7 D-flip-flop 8 D-flip-flop 9 Logic circuit (selection circuit) 13 Logic circuit (selection circuit) 31 Adder 41 Selection circuit 51 2 Modulus prescaler 54 Swallow counter 55 Coarse counter 85 Selection circuit 91 2 Modulus prescaler 93 Swallow counter 98 Coarse counter 101 Variable frequency divider circuit 102 N frequency divider circuit 103 N + 1/2 frequency divider circuit 104 Control circuit 105 Accumulator 142 Voltage control Oscillator (VCO) 149 D-flip-flop 150 AND gate 151 AND gate 152 First phase comparator 153 Second phase comparator 154 Inverter 155 Low frequency filter LPF) 181 voltage-controlled oscillator (VCO) 182 variable frequency divider 183 phase comparator 184 low frequency filter (LPF) 185 programmable divider

 ─────────────────────────────────────────────────── ─── Continuation of the front page (31) Priority claim number Japanese Patent Application No. 8-4215 (32) Priority date Hei 8 (1996) January 12 (33) Priority claiming country Japan (JP) (31) Priority Claim Number Japanese Patent Application No. Hei 8-5769 (32) Priority Date Hei 8 (1996) January 17 (33) Country of priority claim Japan (JP)

Claims (17)

[Claims] 1. A programmable frequency dividing means for alternately dividing an input signal with a frequency dividing ratio N (N is an integer) and a frequency dividing ratio N + 1, and a first frequency synchronizing with an output signal of the programmable frequency dividing means.
Signal generating means for generating a signal, a second signal generating means for generating a second signal obtained by delaying the first signal by 1/2 cycle of the input signal, and the first signal. A variable frequency divider having an output means for alternately outputting the second signal. 2. A delay means for outputting a delay signal obtained by delaying the first signal by one cycle of the input signal, the delay signal and the first signal are alternately selected, and the programmable signal is selected by the selection signal. The variable frequency divider according to claim 1, further comprising preset signal generating means for presetting the frequency dividing means. 3. The output means outputs the first signal when set to a mode with a frequency division ratio N, and the frequency division ratio N + 1 /
And the second signal when the second mode is set.
3. The variable frequency divider according to claim 2, wherein the signal of 1 is output alternately. 4. The preset signal generating means continues to output the first signal as a preset signal to the programmable frequency divider when the mode of the frequency division ratio N is set, and the frequency division ratio N + 1/2 The variable according to claim 2, wherein when the mode is set, the first signal and the delayed signal are alternately selected and the selected signal is output to the programmable frequency divider as a preset signal. Frequency divider. 5. The programmable frequency dividing means outputs a frequency division signal having a frequency division ratio N when the mode is set to the frequency division ratio N, and frequency division is set when the mode is set to the frequency division ratio N + 1/2. The variable frequency dividing device according to claim 1, wherein the frequency dividing signals of the ratio N and the frequency dividing ratio N + 1 are alternately output. 6. The variable frequency divider according to claim 1, wherein the programmable frequency divider presets a frequency division ratio setting value when a preset signal is input. 7. The programmable frequency dividing means includes an adder means for alternately outputting a setting signal of a frequency dividing ratio N (N is an integer) and a frequency dividing ratio N + 1, and a frequency dividing based on the setting signal of the adder means. The variable frequency divider according to claim 1, further comprising a programmable frequency divider that divides the frequency by a ratio. 8. The adder means outputs a setting signal of the frequency division ratio N when the mode is set to the frequency division ratio N, and the frequency division ratio N
Dividing ratio N and dividing ratio N when set to +1/2 mode
Alternately outputs +1 setting signal, and when the output means is set to the mode of the division ratio N,
8. The first signal is output, and when the mode is set to a frequency division ratio N + 1/2, the first signal and the second signal are alternately output, and the second signal is output. Variable frequency divider. 9. The programmable frequency dividing means deletes and outputs one pulse of 2N + 1 pulses of an input signal, and receives the input signal through the deletion circuit and outputs the output of the deletion circuit N times. 2. The variable frequency divider according to claim 1, further comprising a programmable frequency divider that alternately outputs the frequency division of N and the frequency division of N + 1 with respect to the input signal by outputting one pulse for each counting. Peripheral device. 10. The mode of the dividing ratio N is set by the deleting circuit, when the mode of the dividing ratio N + 1/2 is set, deleting one pulse of 2N + 1 of the input signal and outputting the same. When one of the 2N + 1 pulses of the input signal is output without being deleted, the output means outputs the first signal generating means when the mode of the division ratio N + 1/2 is set. Output and the second
The output of the signal generating means is alternately output, whereby the N dividing operation or the N + 1/2 dividing operation is performed on the input signal based on the dividing ratio setting signal. Item 10. The variable frequency divider according to item 9. 11. A two-modulus prescaler that divides an input signal by a division ratio M (M is an integer) or a division ratio M + 1, a course counter unit that divides the two-modulus prescaler P2 times, and And a pulse swallow means for dividing the input signal by a dividing ratio of M × P2 + P1. When the mode is set to, the M × P2 ′ + P1 ′ frequency division is performed, and the frequency division ratio N + 1
Control means for alternately performing M × P2 ′ + P1 ′ frequency division and M × P2 ′ + P1 ′ + 1 frequency division when set to the / 2 mode, and a first signal synchronized with the output of the course counter section. First signal generating means for outputting, second signal generating means for outputting a second signal obtained by delaying the first signal by ½ cycle of the input signal, and a mode of frequency division ratio N When the frequency division ratio N + 1/2 is set, the variable signal further comprises an output means for alternately outputting the first signal and the second signal. Peripheral device. 12. The control means includes adder means for outputting a setting signal for the number of times P1 (P1 is an integer) and the number of times P2 (P2 is an integer), and the course counter section divides the frequency of the two-modulus prescaler. P2 based on the setting signal from the adder means
When the swallow counter section performs the M + 1 division of the 2 modulus prescaler P1 times during P2 times based on the setting signal from the adder means, and when the adder means is set to the division ratio N mode. A setting signal for the number of times P1 and the number of times P2 is output, and the frequency division ratio N + 1/2
When the mode is set, the setting signal indicating the number of times P1 and the number of times P2, the number of times P1 + 1 and the number of times P2, or P1
2. A setting signal representing the addition of a carry that can be generated by the addition of +1 is alternately output.
1. The variable frequency divider according to 1. 13. The control means sets 2 × (M × P2) of the input signal when set to a mode of a frequency division ratio N + 1/2.
12. The variable frequency divider according to claim 11, wherein one pulse out of + P1) +1 is deleted and output, and when the mode of the frequency division ratio N is set, the pulse is output without performing the deletion. apparatus. 14. A division ratio N according to a given integer N.
Alternatively, a dividing means for dividing by a dividing ratio N + 1/2 and a given integer N ′, B and C (where B <C) are given, and N ′ and N ′ + 1 are given to the dividing means. , N'division or N '
+1 frequency division and / or N'is given to the frequency division means to perform N '+ 1/2 frequency division, and the average of the frequency division ratios of the C frequency division cycle of the frequency division means is N' + B. A variable frequency divider having control means for controlling the frequency division means such that the frequency division ratio becomes / C. 15. The control means adds B / C to the accumulated error value A for each division cycle, and subtracts 1/2 from the accumulated value when N ′ + 1/2 division is performed. When N ′ + 1 division is performed, an accumulator for subtracting 1 from the accumulated value A is provided, and in the case of 2 × B ≦ C, the control means is configured to add the accumulated value immediately after the addition of B / C. If A is smaller than 1/2, the frequency dividing means is caused to perform N'frequency division, and if the accumulated value A immediately after the addition of B / C is larger than 1/2, the frequency dividing means is N '+ 1. If the cumulative value A immediately after the addition of B / C is smaller than 1, the control means causes the frequency dividing means to perform N ′ + 1/2 when 2 × B> C. The frequency division is performed, and if the accumulated value A immediately after the addition of B / C is larger than 1/2, the frequency division means is caused to perform N '+ 1 frequency division. Variable frequency device according to 14. 16. A fixed frequency divider that divides P by an integer fixed value by a frequency division ratio P, and an output of the fixed frequency divider that divides N by an integer variable value by a frequency division ratio N / P. And a variable frequency divider having a variable frequency divider. 17. A voltage-controlled oscillator, a variable frequency divider that divides the output of the voltage-controlled oscillator with a frequency division ratio of N + 1/2 (N is an integer), and an output pulse of the variable frequency divider is an odd number And a separation means for separating the even-numbered pulse and a first signal for comparing the phase of the reference signal with the phase of the odd-numbered pulse
A phase comparator for inverting the reference signal, a second phase comparator for comparing the output of the inverting means with the phase of the even-numbered pulse, and an output for the first phase comparator. A low frequency filter for converting the output of the second phase comparator into a control voltage and inputting it to the voltage controlled oscillator.