JPH0590962A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To a frequency synthesizer which can be switched to a desired frequency at a high speed. CONSTITUTION:A phase comparison means 3 of the frequency synthesizer compares a phase of a variable frequency divider output signal fv with a reference frequency signal fr and counts a pulse width in response to a phase lead or lag and applies D/A-conversion convert the county value directly into a DC control voltage of a voltage controlled oscillator(VCO) 5 and is featured to preset the frequency data to initialize the DC control voltage of the VCO 5 oscillating an object frequency at the frequency changeover.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer capable of switching frequencies at high speed.

[0002]

2. Description of the Related Art A conventional example of this type of frequency synthesizer will be described. FIG. 7 shows a conventional example 1 of a frequency synthesizer.
It is a configuration block diagram showing. In the figure, 1 is a reference oscillator,
2 is a fixed frequency divider, 3 is a phase comparator, 4 is a phase comparator,
5 is a voltage controlled oscillator (hereinafter referred to as VCO), 6 is a variable frequency divider, 7A is a control circuit, 25 is a charge pump circuit,
9 is a loop filter. FIG. 8 is a diagram showing another configuration example of the phase comparison means 3 of FIG.
26. In the figure, 11 is an up / down counter and 13 is a DA converter.

Next, the operation of the frequency synthesizer shown in FIG. 7 will be described. In the figure, the output of the reference oscillator 1 is frequency-divided by the fixed frequency divider 2 into a fundamental frequency signal fr. On the other hand, the output of the VCO 5 which outputs the target frequency f _out is divided by the frequency divider 6 by the frequency division number N set by the control circuit 7A to become the variable frequency division signal fv. In the phase comparison means 3, the phase comparator 4 compares the phases of the fundamental frequency signal fr and the variable frequency division signal fv, and if the phases are delayed, EO.
If it has proceeded to D, a pulse having a width corresponding to the phase difference is output to EOU. The charge pump circuit 25 generates a phase comparison signal for driving the loop filter 9 according to the output of the phase comparator. The loop filter 9 takes out the low-frequency component of the phase comparison signal and uses the frequency control voltage V _c to
By changing the oscillation frequency of the VCO 5, the variable frequency division signal f
Construct a phase-locked loop that changes the phase of v. The operation of this phase locked loop is performed by the phase difference output E of the phase comparator 4.
It is continued until OD and EOU are exhausted, and when the phase difference becomes zero, the synchronization state is established. At this time, the output frequency f
_Since the relationship of _out = _Nfr is satisfied, a frequency that is an integral multiple of the fundamental frequency fr can be obtained by changing the frequency division number N (N is an integer).

FIG. 8 is a diagram showing another configuration example of the phase comparison means 3 of FIG. In FIG. 8, the phase comparator 4 compares the phase of fv with the fundamental frequency signal fr as a reference, and outputs a pulse to EOU when the phase is advanced and a pulse to EOD when the phase is delayed. Up-down counter 1
1 counts up EOU pulses and counts down EOD pulses. The DA converter 13 converts the value output from the up / down counter 11 into data and converts it into an analog signal for output.

Next, a conventional example 2 of the frequency synthesizer will be described. FIG. 9 is a block diagram showing a configuration of a second conventional frequency synthesizer, which is disclosed in Japanese Patent Laid-Open No. 2-100519. FIG. 10 is an explanatory diagram of the charge pump circuit 25 and the loop filter 9 of FIG. 9 and 1
In 0, 9 is a loop filter, 13 is an analog switch, 21 is a D / A converter, 25 is a charge pump circuit, 28 is a constant current source, 29 is a switch, 30 is a resistor, 3
1 is a capacitor.

Next, the operation of the frequency synthesizer shown in FIG. 9 will be described. The frequency synthesizer shown in FIG. 9 is a VCO.
5, a variable frequency divider 6, a phase comparator 4, a charge pump circuit 25, and a loop filter 9 constitute a phase locked loop. Here, in a phase locked state in which the reference clock frequency of the output of the reference oscillator 1 is fr, the VCO output frequency is f _out , and the frequency division number of the variable frequency divider is Ndiv, the following equation holds. f _out = Ndiv ・ fr

Next, the phase comparator 4, the charge pump circuit 25, and the loop filter 9 will be described with reference to FIGS. The phase comparator 4 compares the phase (θ _i ) of the reference clock output from the reference oscillator 1 with the output signal phase (θ _o ) of the variable frequency divider 6, and determines the phase error (θ _e = θ _i −θ _o ). Depending on the sign of the phase error θ _e , U
Or output to D. There are three output states. Now, the state of U = D = “H” is N, U = “H”, D =
The state of "L" is U, the state of U = "L", D = "H" is D
Express. As shown in FIG. 10, the charge pump circuit 25 operates as a switch for switching the loop filter 9 to a high impedance state, a charging state by the constant current source 28, or a discharging state according to the above three states of N, U and D, and phase comparison is performed. It has a function of converting the digital signal output from the device 4 into an analog loop filter voltage.

In the frequency synthesizer shown in FIG. 9,
The output frequency f _out can be changed by changing the variable frequency division number Ndiv, but it takes time until the output voltage of the loop filter 9 changes and the phase synchronization loop becomes a new synchronization state. Therefore, conventionally, when changing the output frequency f _out as shown in FIG. 9, the analog switch 13 is closed at the same time when the variable frequency division number is changed, and the D / A converter 2 is changed.
By forcibly applying the output voltage of 1 to the loop filter, the frequency switching time is shortened.

[0009]

Since the conventional example 1 of the frequency synthesizer is configured as described above, the control voltage of the VCO from which the high frequency component contained in the output of the charge pump circuit is sufficiently removed in the loop filter. Otherwise, spurious will occur near the output frequency f _out . Such a loop filter has a large time constant.
Therefore, it has been difficult to speed up the response of the frequency synthesizer when switching the frequency by using the low-pass filter for removing the high-frequency component of the output of the charge pump circuit.
Further, in the other configuration example of the phase comparison means shown in FIG. 8, a loop filter is not necessary, but the output of the phase comparator 4 is directly
Since the counting is performed, it can be detected only whether the phase is delayed or advanced, and the magnitude of the phase difference due to the pulse width cannot be detected. Therefore, it is difficult to switch to the target frequency at high speed.

The invention according to claim 1 has been made to solve the above-mentioned problems.
The VCO control voltage is directly generated to eliminate the need for a loop filter, and when switching the frequency, the up-down counter can be switched to the target frequency at high speed by supplying the initial value data of the target frequency. The purpose is to obtain a perfect frequency synthesizer.

Since the conventional frequency synthesizer 2 is constructed as described above, the output voltage of the D / A converter 21 is forcibly applied to the loop filter.
Although the frequency switching time becomes short, there is a problem that the circuit scale becomes large and the power consumption becomes large by using the D / A converter.

The invention according to claim 2 has been made in order to solve the above problems, and it is an object of the invention to obtain a frequency synthesizer having a smaller circuit scale, less power consumption and a faster frequency switching time than the conventional one. To aim.

[0013]

In order to achieve the above object, a frequency synthesizer of the present invention according to claim 1 comprises a reference oscillator and a fixed frequency divider for dividing the output of the reference oscillator to output a fundamental frequency. , A voltage controlled oscillator that outputs the target frequency, a variable frequency divider that divides the output frequency by a predetermined frequency division ratio, and the phase error of the output of the fixed frequency divider and the variable frequency divider. And a phase comparison means for controlling the voltage controlled oscillator so as to make zero, the phase comparison means compares the phase of the variable frequency divider output signal with the fundamental frequency signal as a reference, and the phase advance or delay phase Means for digitizing the phase difference, converting the output to the DC control voltage of the voltage controlled oscillator, and means for presetting frequency data for initializing the DC control voltage of the voltage controlled oscillator when switching the frequency. Prepare It is obtained by way.

A frequency synthesizer of the present invention according to claim 2 is a voltage controlled oscillator for outputting a target frequency,
A variable frequency divider that divides the oscillator output by a predetermined frequency division number, a reference oscillator, a phase comparator that compares the phases of the reference oscillator output and the variable frequency divider output, and the phase difference is zero. And a second charge pump circuit that forms a phase-locked loop having a loop filter and a second charge pump circuit that connects to a capacitor of the loop filter. During frequency switching, the capacitor of the loop filter is set in a charged state, a discharged state, or a high impedance state for a predetermined time in accordance with the switching frequency difference.

[0015]

In the invention according to claim 1 configured as described above, the phase comparison means compares the phases of the basic frequency signal and the output signal of the variable frequency divider, and the phase advance or the delay is made based on the basic frequency signal. The phase difference is digitized, the count value is DA-converted, and the phase difference is directly converted into the DC control voltage of the VCO, whereby the loop filter becomes unnecessary, and the phase-locked loop has a target frequency. In addition to being able to synchronize at high speed, presetting the target frequency data and initializing the DC control voltage of the VCO at the time of frequency switching reduces the frequency error of the phase synchronization loop after frequency switching and shortens the time. Can converge.

In the invention according to claim 2 configured as described above, the DC control voltage of the VCO is forcibly set to a predetermined value by controlling the charge pump circuit connected to the capacitor of the loop filter at the time of frequency switching. Since the frequency error of the phase-locked loop after switching is reduced and can be converged in a short time because of the setting, the circuit scale and power consumption can be reduced by combining with the charge pump circuit. ..

[0017]

EXAMPLES Example 1. The first embodiment of the present invention will be described below. First Embodiment FIG. 1 is a block diagram showing the configuration of a first embodiment of a frequency synthesizer of the present invention. In the figure, 1 is a reference oscillator, 2 is a fixed frequency divider, 3 is a phase comparator 4, a gate circuit 10, an up / down counter 11, and a latch circuit 1.
2, a phase converter that includes a DA converter 13, a data input circuit 14, a counting pulse oscillator 15, a controller 16 for an up / down counter and a latch circuit, 5 is a VCO, 6 is a variable frequency divider, and 7A is a control. Circuit.

Next, the operation will be described. The same parts as those of the conventional example are designated by the same reference numerals and the description thereof is omitted because they have already been described.
The phase comparison means 3 will be described. The gate circuit 10 has two gates which are opened and closed by the EOU and EOD signals of the phase comparator, and the up / down counter 11 counts up the counting pulse of the output of the gate which is opened and closed by EOU, and the output of the gate which is opened and closed by EOD. Count down counting pulses. This makes EOU, EO
The content of the up / down counter 11 is increased / decreased by the pulse width of the D signal and output as DA converter data.
The content of the up / down counter 11 is reset to a constant value near the center when no pulse is input. This value is the value when the phase difference between the two input signals of the phase comparator 4 is zero.

The latch circuit 12 is an up / down counter 1
It operates immediately after the pulse input to 1 is completed and holds until just before the up / down counter is reset. The counting pulse oscillator 15 generates counting pulses and sends them to the input of the gate circuit 10. The DA converter 13 DA-converts the output of the up / down counter 14 and outputs it, thereby generating a DC voltage and controlling the oscillation frequency of the VCO 5. Therefore, a DC voltage can be applied to the VCO 5 without a loop filter, and the response of the phase locked loop becomes faster. Further, the data input circuit 14 sets the target frequency to VC when switching the frequency.
The control voltage oscillated by O5 is given a numerical value to the up / down counter 11 so that the DA converter 13 can generate it. As a result, the target frequency is initialized, the frequency error after switching of the phase-locked loop becomes small, and the phase-locked loop converges to the target frequency in a short time. By combining the above, it is possible to obtain a frequency synthesizer capable of switching the target frequency at high speed.

2 and 3 are diagrams for explaining the operation of the circuit of the present invention. When the steady phase error is smaller than 0 and the initial frequency is lower than the target frequency in FIG. 2, the steady phase error is 0 in FIG.
An example in which the larger initial frequency is higher than the target frequency is shown. 2 and 3, in common, (A) is a clock of the fundamental frequency signal fr obtained by dividing the output of the reference oscillator 1 by M by the fixed frequency divider 2, and (B) is the output fv of the variable frequency divider 6.
, (C) and (D) are EOD and EOU of the phase comparator 4, respectively.
Output pulses, (E) and (F) are count pulses sent to the input D of the up / down counter 14 and the input U of the up / down counter 14 by the output of the gate circuit 10, and (G) is the count value of the up / down counter 14. , (H) is the output value V _c (I) of the DA converter 13 is the output frequency f of the VCO 5.
_{is out} .

The number of counting pulses after passing through the gate circuit 10 is set to a number proportional to the width of the pulse output from the phase comparator 4, and the number is counted by the up / down counter 14, and the counted value is latched by the latch circuit 12. By holding at, the phase difference is converted into data, and by inputting it to the DA converter 13, the phase difference is directly converted into a DC voltage,
The control voltage of the output frequency of the VCO 5 is used. From the above, this loop operates in the same way as the primary loop.

Example 2. The second embodiment of the present invention will be described below. FIG. 4 is a configuration block diagram showing a second embodiment of the frequency synthesizer of the present invention. In FIG.
9 is a loop filter, 24 is a charge pump drive circuit,
Reference numeral 25 is a first charge pump circuit, and 26 is a second charge pump circuit. The same parts as those of the conventional example are designated by the same reference numerals and have already been described, and thus the description thereof will be omitted. 6 is the same as FIG.
It is a figure which shows the internal structure of the charge pump drive circuit of.
In FIG. 6, 17 is a set time register, 18 is a counter, 19 is a switch, and 20 is a clock generator.

Next, the operation of the frequency synthesizer shown in FIG. 4 will be described. In FIG. 4, the phase comparator 4, the charge pump circuit 25, the VCO 5, the variable frequency divider 6, and the loop filter 9 constitute a phase synchronization loop. When the frequency division number set in the variable frequency divider 2 is changed from N1 to N2, the output frequency of the VCO 1 becomes the frequency of the reference clock by f.
As r, f _out1 = N1 · fr changes from f _out2 = N2 · fr. At this time, it is assumed that the input voltage of VCO1 changes from V _c1 to V _c2 by ΔV _c = V _c2 −V _c1 in the synchronous state. When the capacitance of the capacitor 31 of the loop filter 9 is C and the constant current source 8 of the second charge pump circuit 26 is I amp, the control circuit 7 is
During the period of T = C · | ΔV _c | / I, the charge pump drive circuit 24 is set to output the signal U2 when ΔV _c > 0 and the signal D2 when ΔV _c <0. The second charge pump circuit 26 is in a charge state when U2 = “H” and D2 = “H”.
At the time of, the discharge state is reached, and the capacitor 31 of the loop filter 9 is charged and discharged with the constant current I. Note that U2 = D2 =
When it is “L”, it is in a high impedance state and does not affect the voltage of the capacitor 31.

FIG. 6 shows the internal structure of the charge pump drive circuit 24. The control circuit 7 uses the clock generator 2
When the period of 0 is τ, T / τ is set in the set time register 17.
VCO1 input voltage V _c1 and V _c2
The switch 19 is set according to the magnitude relation of. When the frequency is switched, the counter 18 counts the clock generator 20 by the value of the set time register 17, that is, T
The signal is output to the switch 19 during the period. The switch 19 switches to U2 or D2 according to the setting of the control circuit 7. As described above, the charge pump drive circuit 24 can output the charge state signal U2 or the discharge state signal D2 for a set time when the frequency is switched.

Example 3. The third embodiment of the present invention will be described below. FIG. 5 is a configuration block diagram showing a third embodiment of the frequency synthesizer of the present invention. In FIG.
Reference numeral 23 is a gate circuit. 5, those parts which are the same as those corresponding parts in FIG. 4 are designated by the same reference numerals, and a detailed description thereof will be omitted. In the second embodiment, the second charge pump circuit 26 is separately provided, and the loop filter 9
The capacitor 11 of FIG.
The output of the charge pump drive circuit 24 may be combined with the output of the phase comparator 4 by the OR gate 23 to drive the charge pump circuit 25 as shown in FIG. In this case, there are advantages that the circuit scale can be further reduced and the power consumption can be reduced.

[0026]

As described above, according to the invention of claim 1, the phase difference can be detected for each cycle of the fundamental frequency by using the gate circuit, and the phase difference can be directly detected.
Since it can be converted into the DC control voltage of the VCO, a loop filter having a large time constant is unnecessary, the response speed of the phase locked loop can be increased, and the VCO control voltage is initialized at the time of frequency switching.
Since the error voltage at the time of switching can be reduced and the phase-locked loop can converge in a short time, it is possible to obtain a frequency synthesizer that can switch to a target frequency at high speed.

Further, as described above, according to the second aspect of the invention, the DC control voltage of the VCO is forced by controlling the second charge pump circuit connected to the capacitor of the loop filter at the time of frequency switching. By setting to a predetermined value, the frequency error of the phase-locked loop after switching can be reduced and convergence can be achieved in a short time. A frequency synthesizer that can reduce power can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing a first embodiment of a frequency synthesizer of the present invention.

FIG. 2 is an operation explanatory diagram of FIG.

FIG. 3 is an operation explanatory diagram of FIG. 1.

FIG. 4 is a configuration block diagram showing a second embodiment of the frequency synthesizer of the present invention.

FIG. 5 is a configuration block diagram showing a third embodiment of the frequency synthesizer of the present invention.

FIG. 6 is a diagram showing an internal configuration of the charge pump drive circuit of FIGS.

FIG. 7 is a configuration block diagram showing a first conventional example of a frequency synthesizer.

8 is a diagram showing another configuration example of the phase comparison means in FIG.

FIG. 9 is a configuration block diagram showing a second conventional example of a frequency synthesizer.

10 is an explanatory diagram of a charge pump circuit and a loop filter of FIGS. 4, 5, 7, and 9. FIG.

[Explanation of symbols]

 1 Reference Oscillator 2 Fixed Divider 3 Phase Comparator 4 Phase Comparator 5 VCO 6 Variable Divider 7A, 7B, 7C Control Circuit 9 Loop Filter 10 Gate Circuit 11 Up / Down Counter 12 Latch Circuit 13 DA Converter 14 Data input circuit 15 Counting pulse oscillator 16 Controller 20 Clock generator 23 Gate circuit 24 Charge pump drive circuit 25, 26 Charge pump circuit

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[Procedure amendment]

[Submission date] March 23, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

In the invention according to claim 2 configured as described above, the DC control voltage of the VCO is forcibly set to a predetermined value by controlling the charge pump circuit connected to the capacitor of the loop filter at the time of frequency switching. For setting, the frequency error of the phase-locked loop after switching can be reduced and can be converged in a short time, and the circuit scale and the power consumption can be reduced by combining with the charge pump circuit. be able to.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

Next, the operation of the frequency synthesizer shown in FIG. 4 will be described. In FIG. 4, the phase comparator 4, the charge pump circuit 25, the VCO 5, the variable frequency divider 6, and the loop filter 9 constitute a phase synchronization loop. When the frequency division number set in the variable frequency divider 2 is changed from N1 to N2, the output frequency of the VCO 1 becomes the frequency of the reference clock by f.
As r, f _out1 = N1 · fr changes from f _out2 = N2 · fr. At this time, it is assumed that the input voltage of VCO1 changes from V _c1 to V _c2 by ΔV _c = V _c2 −V _c1 in the synchronous state. When the capacitance of the capacitor 31 of the loop filter 9 is C and the constant current source 8 of the second charge pump circuit 26 is I amp, the control circuit 7 is
During the period of T = C · | ΔV _c | / I, the charge pump drive circuit 24 is set to output the signal U2 when ΔV _c > 0 and the signal D2 when ΔV _c <0. The second charge pump circuit 26 is in a charge state when U2 = “H” and D2 = “H”.
At the time of, the capacitor 31 of the loop filter 9 is charged and discharged with the constant current I for the time T, and the voltage is V _c2.
Set to. It should be noted that when U2 = D2 = “L”, a high impedance state is set and the voltage of the capacitor 31 is not affected.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9182-5J H03L 7/10 A

Claims (2)

[Claims] 1. A reference oscillator, a fixed frequency divider for dividing its output to output a fundamental frequency, a voltage controlled oscillator for outputting a target frequency, and its output frequency divided by a predetermined division ratio. A variable frequency divider and a phase comparison means for controlling the voltage controlled oscillator so as to compare the phases of the outputs of the fixed frequency divider and the variable frequency divider to make the phase error zero, the phase comparison means described above. The frequency of the variable frequency divider output signal is compared with the fundamental frequency signal as a reference, the phase difference of the lead or lag of the phase is digitized, and the output is converted into the DC control voltage of the voltage controlled oscillator, and the frequency is A frequency synthesizer for presetting frequency data for initializing the DC control voltage of the voltage controlled oscillator when switching. 2. A voltage-controlled oscillator that outputs a target frequency, a variable frequency divider that divides the oscillator output by a predetermined frequency division number, a reference oscillator, and the reference oscillator output and the variable frequency divider output. A phase comparator for comparing phases, and a first for generating a control voltage of the voltage controlled oscillator so as to make the phase difference zero.
And a loop filter to form a phase-locked loop, and a second charge pump circuit connected to the capacitor of the loop filter. When the frequency is switched, a predetermined time is set according to the switching frequency difference. A frequency synthesizer characterized by setting and controlling a charge state, a discharge state, or a high impedance state connection of a capacitor of the loop filter.