JP2000040962A - Frequency synthesizer device and mobile radio device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency synthesizer device which is small in power consumption at locking time. SOLUTION: This frequency synthesizer equipped with a 1st variable frequency divider 3 equipped with a prescaler 25, which can have plural frequency division ratios set according to a frequency division ratio control signal and divides the frequency of an input signal, a main counter 22 and a swallow counter 33 which counts the output of the prescaler 25, and a mode control means 24 which controls the frequency division ratio of the prescaler 25 according to the count values of the main counter 22 and a swallow counter 23, a 2nd variable frequency divider 3 which divides the frequency of the output signal of a reference signal source, and a phase comparator 4 which inputs the output signals from the 1st variable frequency divider 2 and 2nd variable frequency divider 3, compares their outputs with each other, and outputs their phase difference to a voltage-controlled oscillator 1 through a low-pass filter 5 varies the frequency division ratio of the prescaler 25, when the output frequency of the 1st variable frequency divider 2 is varied to lower the operating frequencies of the main counter and the swallow counter, thereby reducing the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer used in a mobile radio device or the like, and more particularly to a frequency synthesizer for changing a frequency division ratio of a prescaler according to a frequency division ratio set in a first variable frequency divider. The power consumption at the time of locking can be reduced.

[0002]

2. Description of the Related Art In the case of a communication device, for example, a frequency synthesizer device is used to generate a carrier wave of an arbitrary frequency from a signal of a reference oscillator. As shown in FIG. 6, a conventional frequency synthesizer includes a voltage controlled oscillator (hereinafter, referred to as VCO) 1 that oscillates a signal having a frequency corresponding to an input voltage, and a VCO based on a frequency division ratio set from outside.
1st variable frequency divider 2 for dividing the frequency of the output signal of 1st
A second variable frequency divider 3 for dividing the frequency of the output signal of the reference signal source based on a frequency division ratio set from outside, and an output signal of the variable frequency divider 2 and a variable frequency divider 3 A phase comparator 4 that compares the phase with the output signal and outputs a phase difference, and a low-pass filter (hereinafter, L) that averages the output of the phase comparator 4
PF) 5.

As described in Japanese Patent Application Laid-Open No. Hei 7-297712, a conventional frequency synthesizer first raises the comparison frequency (ie, at the time of switching in) when switching the frequency of the VCO 1 (hereinafter referred to as “pull-in”). The response of the loop is increased by reducing the frequency ratio, and the output signal (fvco) of the VCO 1 is rapidly brought close to the target frequency. When the signal is almost pulled in, the comparison frequency is lowered (that is, the frequency dividing ratio is increased). Stabilizes (locks) at the target frequency.

Assuming that the dividing ratios at the time of pull-in which are set in the variable frequency divider 2 and the variable frequency divider 3 are M1 and R1, respectively, at the time of pull-in, the variable frequency divider 2 outputs the output signal (fvco ) Is divided by the division ratio M1 to output a signal (fdiv1), and the variable frequency divider 3 outputs the output signal (fos) of the reference oscillator.
A signal (fref1) obtained by dividing c) by the dividing ratio R1 is output.

The phase comparator 4 compares the phases of fref1 and fdiv1 and outputs a phase difference. The output signal of the phase comparator 4 is input to the control voltage terminal of the VCO 1 after being averaged by the LPF, and the VCO 1 changes the frequency of the output signal according to the voltage applied to the control voltage.

This signal is output to the outside and is input to the feedback loop of the variable frequency divider 2 to operate so that the frequency and phase of fref1 and fdiv1 match.
Then, when the frequencies of fref1 and fdiv1 substantially match, the frequency division ratio set in the variable frequency divider 2 and the variable frequency divider 3 is switched (here, S times). After this, the frequency becomes 1
When the frequency and phase of fref2 and fdiv2 multiplied by / S match, the output signal of VCO1 is stabilized. Where f
If the contents of vco are represented by an expression, fvco at the time of pull-in
Is as shown in the following equation (1). fvco = M1 × fref1 (1) fvco at the time of stability is expressed by the following equation (2). fvco = S × M1 × fref2 (2) (however, fref2 = fref1 / S)

Next, the configuration of the variable frequency divider 2 shown in FIG. 6 will be described. The variable frequency divider 2 is a generally known pulse swallow type variable frequency divider. The pulse swallow variable frequency divider includes a prescaler 21, a main counter 22, a swallow counter 23, and mode control means 24.

The operation of the pulse swallow type variable frequency divider 2 will be described below. The prescaler 21 outputs a signal fck obtained by dividing the frequency of the input signal fvco by P or (P + 1) to the main counter 22 and the swallow counter 23. The main counter 22 and the swallow counter 23 simultaneously start counting fck, and output the count value to the mode control means 24. The mode control means 24 sets the division ratio of the prescaler 21 to (P + 1) until the count value of the swallow counter 23 becomes A, and sets the prescaler until the count value of the main counter 22 is A to N (where A <N). A mode control signal is output to the prescaler 21 so that the frequency division ratio of P becomes P. When the count value of the main counter 22 becomes N, the A value is loaded into the swallow counter 23 and the N value is loaded into the main counter 22, and the signal fdiv is output at the same time. Thereafter, this operation is repeated.

That is, the total frequency division ratio M of the variable frequency divider 2 is expressed by the following equation (3). M = (P + 1) · A + P · (NA) = P · N + A (3)

Therefore, the output signal fvco of the frequency synthesizer device at the time of pull-in is represented by the following equation (4). f _VCO = M1 · fref1 = (P · N + A) · fref1 (4)

[0011]

In a frequency synthesizer device, it is important to reduce the pull-in time and reduce power consumption. In order to shorten the pull-in time in the frequency synthesizer of FIG. 6, it is preferable to increase the comparison frequency fref1 at the time of pull-in as much as possible.

In the above equation (3), when N <P, the condition of N> A may not be satisfied, and a continuous dividing ratio cannot be set. Therefore, if the desired frequency division ratio M is determined, it is necessary to determine P so as to satisfy the following equation (5). M ≧ P ² (5)

In the frequency synthesizer device shown in FIG. 6, the frequency division ratios at the time of pull-in and at the time of lock are different. M with small dividing ratio
1 must satisfy the above equation (5), and P must be a small value. In this case, there is a problem that the frequency of the clock fck supplied to the main counter 22 and the swallow counter 23 increases, and power consumption increases.

An object of the present invention is to solve the above-mentioned conventional problem, and an object of the present invention is to provide a frequency synthesizer which changes a comparison frequency between a pull-in state and a lock state and consumes low power in the lock state.

[0015]

Therefore, the frequency synthesizer of the present invention is provided with frequency division ratio control means for changing the frequency division ratio of the prescaler when switching the comparison frequency during the pull-in process.

Further, according to the frequency dividing ratio changing method of the present invention, the frequency dividing ratio of the prescaler is set according to the frequency dividing ratio set from the outside, the operating frequency of the main counter and the swallow counter is lowered, and the power consumption during locking is reduced. We try to reduce the power.

By applying the frequency synthesizer apparatus and the dividing ratio changing method of the present invention configured as described above to a mobile radio, a mobile radio with a long battery life can be obtained.

[0018]

According to the first aspect of the present invention, a plurality of frequency division ratios can be set based on a frequency division ratio control signal.
A prescaler for dividing the frequency of the input signal, a main counter and a swallow counter for counting the output of the prescaler, and mode control means for controlling a division ratio of the prescaler based on count values of the main counter and the swallow counter. 1 variable frequency divider, a second variable frequency divider for dividing the frequency of the output signal of the reference signal source, and input signals from the first variable frequency divider and the second variable frequency divider. A phase comparator that compares phases and outputs the phase difference to a voltage-controlled oscillator via a low-pass filter, a voltage-controlled oscillator that outputs a signal having a frequency corresponding to an input voltage to a prescaler, and the voltage-controlled oscillator. When changing the output frequency of the first variable frequency divider, the first variable frequency divider is configured to change the output frequencies of the first variable frequency divider and the second variable frequency divider at the same rate. And a means for switching a frequency division ratio set in the second variable frequency divider, wherein when the output frequency of the first variable frequency divider is changed, the frequency division ratio of the prescaler is changed. By changing the prescaler division ratio to a large value during locking when the division ratio increases, the operating frequency of the main counter and the swallow counter can be reduced, and power consumption can be reduced. It has the action of:

The invention according to claim 2 of the present invention provides:
2. The frequency synthesizer according to claim 1, wherein 2 ⁿ
Alternatively, a prescaler capable of setting a dividing ratio of 2 ⁿ (where n is a natural number) and a dividing unit for outputting a dividing ratio control signal for changing n based on the dividing ratio set in the first variable divider. A frequency ratio control means is provided, and there is no need to externally set a frequency division ratio control signal during the pull-in process, which has the effect of simplifying control.

The invention according to claim 3 of the present invention provides:
In the frequency synthesizer device according to the second aspect, the operation of a part of the prescaler is stopped based on the frequency division ratio control signal, and has an effect of eliminating unnecessary power consumption at the time of locking.

Further, the invention described in claim 4 of the present invention is as follows.
The frequency synthesizer device according to any one of claims 1 to 3 is provided in a mobile wireless device, and has an effect that power consumption of the mobile wireless device can be reduced and battery life can be extended.

The invention according to claim 5 of the present invention provides:
In the method of changing the frequency division ratio of the prescaler constituting the frequency synthesizer device, when changing the frequency of the output of the voltage controlled oscillator, the frequency division ratio of the prescaler is set based on the frequency division ratio set in the first variable frequency divider. Is changed to reduce the operating frequency of the main counter and the swallow counter, and has an effect that power consumption can be reduced.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. The same components as those in the conventional technology shown in FIG. 6 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

(First Embodiment) FIG. 1 shows a configuration of a frequency synthesizer device according to a first embodiment of the present invention, in which a frequency division ratio control signal is input to a prescaler 25. However, this is different from the conventional example of FIG.

FIG. 2 shows an example of the configuration of the prescaler 25. The frequency division ratio can be changed to 4 or 5 by controlling the signal C, and the two-modulus prescaler 251 for outputting the signal fmod obtained by dividing the frequency of the input signal fvco by four or five, and the four-stage two-divider are arranged vertically. Signal fmod / 8, which is frequency-divided and frequency-divided by 8, and signal fmod, which is frequency-divided by 16.
/ Synchronous frequency divider 252 for outputting to the selecting means 253, selecting means 253 for selecting and outputting either fmod / 8 or fmod / 16 according to the frequency dividing ratio control signal, and a frequency dividing ratio control signal AND gate 254 which takes the logical product of fmod / 16 and fmod / 16, the output of the 4-stage frequency divider in the asynchronous frequency divider 252 and the AND gate 2
And a NOR gate 255 for taking a logical sum with the output of the 54 and outputting a signal C.

Next, the operation of the prescaler shown in FIG. 2 will be described. When the signal C is at the L level, the 2-modulus prescaler 251 outputs the signal fmod obtained by dividing the frequency of fvco by four.
And outputs a signal fmod obtained by dividing the frequency of fvco by 5 when the signal C is at the H level.

First, the case where the frequency division ratio control signal is at the H level will be described. The signal C when the mode control signal is at the H level
Is at L level, a signal obtained by dividing the frequency of fvco by 64 is selected by the selection means 253 and output as fck. When the mode control signal is at the L level, the mode signal is a 64-pulse f
The H level is maintained for one pulse of the mod signal, and the L level is maintained for the others. That is, a signal obtained by dividing the frequency of fvco by 65 is output as fck. In other words, the variable frequency divider 2 of FIG. 1 operates as a pulse swallow type variable frequency divider of P = 64. Therefore, according to the above equation (5), if the frequency division ratio is 4096 or more, it can be set continuously.

Next, a case where the frequency division ratio control signal is at the L level will be described. The signal C when the mode control signal is at the H level
Is an L level, a signal obtained by dividing the frequency of fvco by 32 is selected by the selection means 253 and output as fck. When the mode control signal is at the L level, the mode signal is a 32-pulse f
The H level is maintained for one pulse of the mod signal, and the L level is maintained for the others. That is, a signal obtained by dividing the frequency of fvco by 33 is output as fck. That is, the variable frequency divider 2 of FIG. 1 operates as a pulse swallow type variable frequency divider of P = 32. Therefore, according to the above equation (5), if the frequency division ratio is 1024 or more, it can be set continuously.

The operation of the frequency synthesizer of FIG. 1 having the above-described variable frequency divider will be described below.

The frequency synthesizer shown in FIG. 1 has a VCO like the conventional frequency synthesizer shown in FIG.
When switching the frequency of 1, the pull-in time is increased, the comparison frequency is increased (ie, the frequency division ratio is reduced), the response of the loop is increased, and the output signal (fvco) of the VCO 1 is rapidly increased.
To the target frequency. Here, it is assumed that the frequency division ratio at this time is 1024 or more and less than 4096. Thus, the frequency division ratio control signal is set to L level. That is, fck at this time
Is about fvco / 32, and the main counter 22 and the swallow counter 23 operate at this frequency.

When the reference frequency is almost reached, the comparison frequency is lowered (that is, the frequency dividing ratio is increased) to lock to the target frequency. Here, the division ratio is 8 times (S = 8)
Let's say Since the frequency division ratio is 4096 or more, it can be operated at P = 64. At the same time, the frequency division ratio is increased by 8 and the frequency division ratio control signal is set to the H level. That is, the frequency of fck at this time is about fvco / 64, and the main counter 22 and the swallow counter 23 operate at this frequency, and their power consumption is reduced by half.

As described above, in the frequency synthesizer device in which the frequency division ratio is different between the pull-in time and the lock time, by setting the value of P of the pulse swallow type variable frequency divider to be large at the lock time when the frequency division ratio becomes large. The operating frequency of the main counter and the swallow counter can be reduced, and power consumption can be reduced.

Although specific numerical values are used for P and S here for easy understanding of the description, other values can be similarly used.

The configuration of the prescaler 25 is not limited to the configuration shown in FIG. Also, the prescaler 25
Two values of P can be selected (32 and 6 in the first embodiment).
4) can be similarly implemented in two or more ways.

Further, at the time of pull-in, the frequency synthesizer apparatus can be similarly implemented by changing the frequency division ratio of the first variable frequency divider with time so as to equivalently obtain the frequency division ratio including the decimal part. .

Further, by applying the frequency synthesizer of the above embodiment to a mobile radio, the power consumption of the mobile radio can be reduced, and a mobile radio with a long battery life can be obtained.

Second Embodiment A frequency synthesizer according to a second embodiment of the present invention, as shown in FIG. 3, outputs a frequency division ratio control signal based on a frequency division ratio. Control means 6 is provided. Others are the same as the first embodiment (FIG. 1).

FIG. 4 shows the structure of the frequency division ratio control means 6. An OR gate 61 for calculating the logical sum of the eleventh and twelfth bits from the LSB of the m-bit division ratio, and a NAND gate 62 for calculating the logical product of the inversion of the thirteenth bit or more and the OR gate 61 are provided.

The frequency division ratio control means 6 outputs an L level frequency division ratio control signal when the frequency division ratio is not less than 1024 and less than 4096. When the division ratio becomes 4096 or more, an H-level division ratio control signal is output.

By adopting such a configuration, it is not necessary to externally set the frequency division ratio control signal. Here, the configuration has been described in which the division ratio control signal is at L level when P = 32 (= 2 ⁵ ). However, even when P = 2 ^k (k is a natural number), the division ratio is If the configuration is such that P = 2 ^k is selected when it is ^{equal to} or more than ^{22 k and} less than ^{22 (k + 1)} , it can be similarly implemented.

(Third Embodiment) In a frequency synthesizer device according to a third embodiment of the present invention, as shown in FIG. It is input to the divide-by-2 frequency (4). Others are first and second
There is no difference from the embodiment (FIG. 2).

In FIG. 5, when the frequency division ratio control signal is at the L level, fmod / 8 is selected and fmod / 16 is ignored. In other words, if the operation of the last-stage frequency divider (4) is controlled to be stopped by the frequency division ratio control signal, useless power consumption is eliminated, and power consumption is reduced as compared with the first embodiment. be able to.

[0043]

As is clear from the description of the above embodiment, the present invention has an effect that the power consumption at the time of locking can be reduced in a frequency synthesizer device that changes the comparison frequency at the time of pull-in.

Also, by applying this frequency synthesizer device to a mobile radio, the power consumption of the mobile radio can be reduced, and a mobile radio with a long battery life can be obtained.

Further, the frequency dividing ratio changing method of the present invention has an effect that the power consumption of the frequency synthesizer device for changing the comparison frequency at the time of locking can be reduced when locked.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a frequency synthesizer device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a configuration example of a prescaler according to the first embodiment of the present invention;

FIG. 3 is a diagram showing a configuration of a frequency synthesizer device according to a second embodiment of the present invention;

FIG. 4 is a diagram showing a configuration example of a frequency division ratio control unit according to a second embodiment of the present invention;

FIG. 5 is a diagram showing a configuration example of a prescaler according to a third embodiment of the present invention;

FIG. 6 is a diagram showing a configuration of a conventional frequency synthesizer device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Voltage controlled oscillator 2 1st variable frequency divider 3 2nd variable frequency divider 4 Phase comparator 5 Loop filter 6 Division ratio control means 21, 25 Prescaler 22 Main counter 23 Swallow counter 24 Mode control means 61 NAND gate 62 OR gate 251 Two modulus prescaler 252 Asynchronous frequency divider 253 Selection means 254 AND gate 255 NOR gate

Claims (5)

[Claims] 1. A prescaler for dividing a frequency of an input signal, a main counter and a swallow counter for counting an output of the prescaler, a plurality of division ratios being set based on a division ratio control signal, A first variable frequency divider having mode control means for controlling a frequency division ratio of the prescaler based on a count value of the swallow counter, and a second variable frequency divider for dividing a frequency of an output signal of a reference signal source And input the output signals from the first variable frequency divider and the second variable frequency divider, compare the phases, and output the phase difference to the voltage controlled oscillator via a low-pass filter. Phase comparator, the voltage-controlled oscillator that outputs a signal having a frequency corresponding to the input voltage to the prescaler, and when changing the frequency of the output of the voltage-controlled oscillator, A frequency division ratio set in the first variable frequency divider and the second variable frequency divider so that the output frequencies of the first variable frequency divider and the second variable frequency divider are changed at the same rate Switching means for changing the frequency of the output signal of the first variable frequency divider, wherein the frequency division ratio of the prescaler is changed when the output frequency of the first variable frequency divider is changed. 2. A prescaler capable of setting a dividing ratio of 2 ⁿ or 2 ⁿ +1 (n is a natural number), and changing the n based on a dividing ratio set in the first variable frequency divider. 2. The frequency synthesizer device according to claim 1, further comprising frequency division ratio control means for outputting a frequency division ratio control signal. 3. The frequency synthesizer device according to claim 2, wherein an operation of a part of said prescaler is stopped based on said frequency division ratio control signal. 4. A mobile wireless device comprising the frequency synthesizer device according to claim 1. 5. A method for changing a frequency division ratio of a prescaler constituting a frequency synthesizer device, the method comprising: changing a frequency of an output of a voltage controlled oscillator according to a frequency division ratio set in a first variable frequency divider. A method for changing the frequency division ratio of a prescaler, wherein the frequency of operation of a main counter and a swallow counter is reduced by changing the frequency division ratio of a prescaler.