JP3516785B2 - Frequency synthesizer device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop (PLL) type frequency synthesizer device which operates so that an output signal frequency always matches a set frequency.

[0002]

2. Description of the Related Art FIG. 5 shows the configuration of a conventional frequency synthesizer device. In FIG. 5, 1 is a voltage controlled oscillator (hereinafter referred to as VCO), 2 is a variable frequency divider, 3 is a phase comparator, 4 is a charge pump, and 5 is a low-pass filter (hereinafter referred to as LPF).

The above-mentioned conventional frequency synthesizer device will be described in more detail below together with its operation. The variable frequency divider 2 uses the VCO based on the frequency division ratio set from the outside.
The signal fdiv which is obtained by dividing the frequency of the output signal of No. 1 (hereinafter referred to as fvco) is output. The phase comparator 3 is fdiv
And the phase of a reference signal (hereinafter, referred to as fref) are compared, and pulse signals U and D corresponding to the phase difference are output to the charge pump 4. The charge pump 4 charges and discharges electric charge in the LPF 5 based on the pulse signals U and D output from the phase comparator 3, so that a DC voltage is input to the control voltage terminal of the VCO 1. The output of the VCO 1 whose frequency changes according to the voltage applied to the control voltage terminal is output to the outside and also to the variable frequency divider 2. As described above, in the frequency synthesizer device, the VCO 1, the variable frequency divider 2, the phase comparator 3, the charge pump 4, and the LPF 5 form a feedback loop, and the lock state is established when the frequencies and phases of fref and fdiv match. , VCO1 output signals are stable.

FIG. 6 shows the configuration of a pulse swallow-type variable frequency divider used in the frequency synthesizer device. In FIG. 6, 6 is a 2 modulus prescaler, 7
Is a main counter, 8 is a swallow counter, and 9 is a mode control means.

The pulse swallow type variable frequency divider will be described in more detail below together with its operation. The 2-duras prescaler 6 outputs a signal fck obtained by dividing the frequency of the input signal fvco by P or (P + 1) to the main counter 7 and the swallow counter 8. The main counter 7 and the swallow counter 8 simultaneously start counting fck and output the count value to the mode control means 9. Until the count value of the swallow counter 8 becomes A, the mode control means 9 sets the frequency division ratio of the 2 modulus prescaler 6 to (P + 1) and the count value of the main counter 7 becomes A.
Between -N (however, A <N), the mode control signal is output to the 2-modulus prescaler 6 so that the frequency division ratio of the 2-modulus prescaler 6 becomes P. When the count value of the main counter 7 becomes N, the A value is given to the swallow counter 8.
The main counter 7 is loaded with N values, respectively, and at the same time, the signal fdiv is output. After that, this operation is repeated. That is, the total frequency division ratio M of the variable frequency divider of the pulse swallow method
Becomes (Equation 1).

[0006]

[Equation 1] When the pulse swallow type variable frequency divider that operates as described above is used in the side variable frequency divider 2 of FIG. 5, the output signal fvco of the frequency synthesizer device in the locked state becomes as shown in (Equation 2).

[0007]

[Equation 2]

[0008]

In a frequency synthesizer device, it is important to reduce the time until the output signal stabilizes at the set frequency (hereinafter referred to as pull-in time) and to reduce the power consumption. is there. In order to shorten the pull-in time, it is necessary to increase fref. In (Equation 1), when N <P, the condition of N> A may not be satisfied, and it becomes impossible to set continuous frequency division ratios. Therefore, the minimum division ratio Mmi that can be set continuously is
n is as in (Equation 3).

[0009]

[Equation 3] Therefore, the maximum fref can be expressed by (Equation 4).

[0010]

[Equation 4] To increase the frequency of fref, P may be decreased, but in that case, the frequency of the clock fck of the main counter 7 and the swallow counter 8 becomes high, and power consumption increases. Therefore, P must be increased, and in this case, the frequency of fref cannot be increased, and the pull-in time cannot be shortened sufficiently.

The present invention solves the above-mentioned conventional problem. The minimum frequency division ratio that can be continuously set without decreasing P is reduced, and the frequency of fref is increased to shorten the pull-in time. It is an object of the present invention to provide a frequency synthesizer device capable of performing the above.

[0012]

In order to achieve the above object, the frequency synthesizer device of the present invention compares the phases of the reference signal and the output signal of the variable frequency divider with a phase comparator, and based on the phase difference. Output a signal whose pulse width increases or decreases to the voltage controlled oscillator through the charge pump and low pass filter, and divides the frequency of the output of the voltage controlled oscillator based on the frequency division ratio set externally by the variable frequency divider. In the frequency synthesizer device that performs frequency division and outputs, the variable frequency divider has P (P is a positive integer), (P + 1) and (P + 2 ^k ).
(K is an integer greater than or equal to 1)
And a counter for counting the output of the prescaler, and a mode control means for controlling the frequency division ratio of the prescaler based on the count value of the counter.

[0013]

In the above frequency synthesizer device, the prescaler divides the input signal by two modulus prescalers and n (where n is an integer of 1 or more) subordinates by which the output signals of the two modulus prescalers are divided. The logical sum of the connected frequency divider, the first logical gate that takes the logical product of the output of this frequency divider and the signal output from the mode control means, and the output of this first logical gate In other words, a second logic gate for controlling the frequency division ratio of the two-modulus prescaler can be provided.

[0015]

According to the present invention configured as described above, the minimum frequency division ratio that can be set continuously can be reduced by switching a plurality of frequency division ratios of the prescaler based on the count value of the counter. Therefore, the frequency of the reference signal can be increased.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention. In the embodiment of the present invention, the variable frequency divider 2 of the conventional frequency synthesizer device shown in FIG. 5 has a new configuration, and the other same components are given the same reference numerals and the description thereof will be omitted.

The variable frequency divider 2 has (k + 2) ways (however,
(k is an integer equal to or greater than 1), and a signal fck obtained by dividing the frequency of fvco based on the frequency division ratio set by the mode control means 9 is output (k + 2) modulus prescaler 10. , Fck is counted based on a count value set from the outside, the count value is output to the mode control means 9, and a signal fdiv generated at the end of counting is output. k + 2) signal for controlling the dividing ratio of the modulus prescaler 10 S, and a mode control means 9 for outputting the S ₁ to S _K.

FIG. 2 is a block diagram of the (k + 2) modulus prescaler 10 of FIG. The frequency division ratio can be changed to Q or (Q + 1) by controlling the mode signal, and the frequency of the input signal fvco is divided by Q or (Q + 1) to output a signal fmod, and a two-modulus prescaler 12; n two-frequency divider (where, n is n ≧ k an integer greater than or equal to 1) and outputs a signal fdiv that 2 ⁿ division a cascaded with fmod frequency, and 2 ⁿ divider 13, 2 ⁿ divider of n 2 divider in 13 outputs a signal S ₁ to S _K aND gate 14 ANDing each, aND gates 1
It is composed of k AND gate outputs in 4 and a NOR gate 15 which takes the logical sum of the signals S.

The operation of the frequency synthesizer device of the embodiment of the present invention constructed as above will be described below.

The operation of the (k + 2) modulus prescaler shown in FIG. 2 will be described with reference to FIG. The 2-modulus prescaler 12 of FIG. 2 outputs a signal fmod obtained by dividing the frequency of fvco by Q when the mode signal is at the L level, and outputs a signal obtained by dividing the frequency of fvco by (Q + 1) when the mode signal is at the H level. Output fmod.

The mode signal when S is at H level is L level.
The frequency of fvco by P (≡2 ⁿ・ Q) Divided signal
No. fck is output. S is L level and S₁~ S_KIs H
The mode signal when the bell is 2ⁿPulsed fmod signal
H level during one pulse of
It That is, the frequency of fvco is divided by (P + 1).
The signal fck is output. S and S₁Is H level and S₂~ S
_KMode signal when H level is 2ⁿFmo of the pulse
H level during 2 pulses of d signal, L level
Become That is, the frequency of fvco is equal to (P + 2)
The rounded signal fck is output. S, S₁, S₂Is L level
Le S₃~ S_KMode signal when H level is 2ⁿPa
At the H level for four pulses of the lus fmod signal,
Others become L level. That is, the frequency of fvco
The (f + 4) frequency-divided signal fck is output.

In the same way, the signals S, S ₁ -S ₂ are considered.
(Table 1) shows the relationship between and the division ratio (* mark: Do
n't Care).

[0023]

[Table 1] As described above, the (k + 2) modulus prescaler in FIG. 2 can set (k + 2) frequency division ratios by controlling S and S _{1 to} S _k .

In FIG. 1, a (k + 2) modulus prescaler 10 calculates the frequency of an input signal fvco as a signal S,
Based on S _{1 to} S _k , the signal fck divided by the division ratio shown in (Table 1) is output to the counter 11. Counter 11 is f
ck is counted and the count value is output to the mode control means 9. As shown in the timing chart of FIG. 4, the mode control means 9 uses the (k + 2) modulus prescaler 1
Control the division ratio of 0.

In FIG. 4, until the counter 11 counts A ₁ , the (k + 2) modulus prescaler 10
The frequency division ratio of (P + 1), and then the count value becomes A ₂
Until (k + 2), the frequency division ratio of the modulus prescaler 10 is set to (P + 2). Similarly, every time the count value becomes A ₃ , A ₄ , ... A _j (where j = k + 1), (k +
2) The frequency division ratio of the modulus prescaler 10 is switched to (P + 2 ^{j -1} ). After that, the frequency division ratio of the (k + 2) modulus prescaler 10 is set to P until the counter 11 counts A _{j + 1} . At the end of counting, the above operation is repeated. That is, the total frequency division ratio M of the variable frequency divider 2 is as in (Equation 5).

[0026]

[Equation 5] Therefore, the output signal fvco of the frequency synthesizer device in the locked state is as shown in (Equation 6).

[0027]

[Equation 6] An example showing the effect of the present invention is shown in (Table 2). (Table 2)
Is, for example, P = 32, 64, 128 (where P = 4.
2 ² , n ≧ k) and for each k 1, 2,
In the case of 3, the minimum frequency division ratio Mmin that can be continuously set is calculated. Further, FIG. 6 calculated from (Equation 3)
(Table 2) also shows the minimum frequency division ratio that can be continuously set by the pulse swallow type variable frequency divider.

[0028]

[Table 2] As shown in (Table 2), even if the value of P is the same, the value of Mmin can be made smaller than that of the conventional example. Further, Mmin can be further reduced by increasing the value of k. That is, Mmin can be reduced without reducing the frequency division ratio of the prescaler. As a result, the maximum frequency of fref expressed by (Equation 7) can be increased, and the pull-in time can be shortened.

[0029]

[Equation 7] In (Table 2), P is 32, 64, 128 (Q = 4)
And Mmi for k of 1, 2, and 3, respectively.
Although n has been calculated, the present invention is not limited to this, and the same configuration is possible even if each has an arbitrary value.

Further, in this embodiment, the (k + 2) modulus prescaler 10 is based on the count value of the counter 11.
Although the frequency division ratio is switched, the counter 11 may be divided into a plurality of counters and the frequency division ratio of the (k + 2) modulus prescaler 10 may be switched based on the count value of each counter.

[0031]

As described above, according to the present invention, a plurality of frequency division ratios of the prescaler are switched based on the count value of the counter that counts the output signal of the prescaler. The pull-in time can be shortened by increasing the frequency of the reference signal of the frequency synthesizer device by decreasing the minimum frequency division ratio that can be continuously set by the variable frequency divider without increasing the frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing a frequency synthesizer device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a prescaler used in the same frequency synthesizer device.

FIG. 3 is a timing chart showing an operation of a prescaler used in the frequency synthesizer device.

FIG. 4 is a timing chart showing the operation of the variable frequency divider used in the frequency synthesizer device.

FIG. 5 is a block diagram showing a conventional frequency synthesizer device.

FIG. 6 is a block diagram showing a variable frequency divider used in the same frequency synthesizer device.

[Explanation of symbols]

1 Voltage Controlled Oscillator 2 Variable Divider 3 Phase Comparator 4 Charge Pump 5 Low Pass Filter 6 2 Modulus Prescaler 7 Main Counter 8 Swallow Counter 9 Mode Control Means 10 (k + 2) Modulus Prescaler 11 Counter 12 2 Modulus Prescaler 13 2 ⁿ 14 AND Gate 15 NOR gate

Claims (2)

(57) [Claims] 1. A phase comparator compares the phases of a reference signal and a signal output from a variable frequency divider, and a signal whose pulse width increases or decreases based on the phase difference is sent to a voltage controlled oscillator via a charge pump and a low pass filter. In the frequency synthesizer device for outputting and frequency-dividing the frequency of the output of the voltage controlled oscillator based on a frequency division ratio externally set by the variable frequency divider, the variable frequency divider outputs P (P Is a positive integer),
Represented by (P + 1) and (P + 2 ^k ) (k is an integer of 1 or more)
A prescaler capable of setting k division ratios (k + 2 in total) , a counter for counting the output of the prescaler, and a mode control means for controlling the division ratio of the prescaler based on the count value of the counter. Frequency synthesizer device equipped with. 2. A prescaler divides an input signal by 2.
A modulus prescaler, n (where n is an integer of 1 or more) cascade-connected divide-by-2 frequency dividers for dividing the output signals of the two-modulus prescaler, the output of the divide-by-2 divider and the mode control means. A first logic gate for taking the logical product of the signals output from the second logic gate and a second logic gate for taking the logical sum of the outputs of the first logic gate and controlling the frequency division ratio of the two-modulus prescaler. The frequency synthesizer device according to claim 1 .