JP3090790B2 - Phase locked oscillator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fluctuation component such as jitter.
A stable frequency output signal from an input signal containing
Phase-locked oscillators, especially when the frequency of the reference
This is applicable when the frequency does not become an integral multiple of the frequency of the force signal.
The present invention relates to a phase-locked oscillator. 2. Description of the Related Art A phase-locked oscillator can be easily integrated into an LSI.
To reduce the size of the circuit and stabilize the oscillation frequency.
Is needed. FIG. 8 shows a conventional phase locked oscillator.
You. In the figure, 11 is a voltage controlled oscillator, 12 is a voltage controlled oscillator
Frequency conversion circuit for frequency-converting the oscillation output signal of
13 is an input clock and an output signal of the frequency conversion circuit 12.
A phase comparator for comparing the phases of the signals;
This is a loop filter that smoothes the phase error signal of
Output voltage of the loop filter 14 of the voltage controlled oscillator 11
Control the oscillation frequency of The frequency conversion circuit 12 usually has an M
A circuit (where M is an integer of 2 or more) is used,
The oscillation frequency of the voltage controlled oscillator 11 is
If it does not become an integral multiple, for example,
Non-equi-periodic frequency divider circuit as described in No. 11049
Is used. A phase-locked oscillator using this non-equi-periodic frequency dividing circuit
The shaker is shown in FIG. As shown, non-equi-periodic frequency division
The path is dual M switchable to M and (M + 1)
Modulus-type frequency divider 121 and frequency divider 121
A frequency divider 122 for controlling the switching of the frequency ratio;
AND gate 123 for controlling the passage of
It is composed only. [0006] Conventional phase-locked oscillator
Has a voltage controlled oscillator and a loop filter,
These cannot be composed of digital circuits,
Therefore, it is not suitable for circuit LSI, and the circuit
Not suitable for power consumption. [0007] The free-running frequency of the voltage controlled oscillator depends on the environment.
Oscillation frequency is susceptible to temperature or power supply fluctuations
There is also a problem of lack of stability. For this reason, a voltage controlled oscillator is used as a reference frequency source.
A small and highly stable fixed oscillator can be used instead of a vibrator.
And all other circuit parts are digital circuits
A phase-locked oscillator that can be used is desired. [0009] However, as shown in FIG.
In a phase-locked oscillator composed of a period divider,
The divider circuit provides a highly accurate division ratio (ie,
Frequency division ratio that has many digits in the
The circuit configuration becomes very complicated and the frequency changes.
It can be created programmably to support further
could not. Therefore, using this fixed oscillator
It could not be applied to a phase locked oscillator. When performing non-equi-periodic frequency division, phase comparison is performed.
Of the phase comparison timing in the
Perform frequency switching at any timing
As a result, the phase comparison result becomes stochastic and
Phase error increases or decreases with each
Large fluctuations, resulting in stable output phase of control clock
There is a problem not to do. On the other hand, the above-mentioned non-equi-periodic frequency divider uses
In a phase-locked oscillator, a fixed oscillator is used.
When the number is an integral multiple of the required frequency, the period of the counter
Phase change caused by changing the phase of the low frequency
Fluctuations, and it is difficult to remove the effects. The present invention has been made in view of such circumstances.
The purpose is to replace the voltage-controlled oscillator.
Instead, a small and highly stable fixed oscillator is used and other circuit parts
The phase can be configured with digital circuits,
An object of the present invention is to make an oscillator smaller and more stable. FIG. 1 shows the principle of the present invention.
FIG. The phase locked oscillator of the present invention has a basic
Fixed state oscillating at least one fixed frequency
The oscillation output signals of the oscillator 101 and the fixed oscillator 101 are
Non-equi-periodic division ratio variable type that converts frequency by equal-period division
Non-equi-periodic frequency dividing circuit 102 and input signal
Phase comparator 1 for comparing the phase with the output signal of circuit 102
03 based on the phase comparison result of the phase comparator 103.
The unequal frequency division of the unequal-period frequency dividing circuit 102 so as to eliminate the phase error
Control means 104 for performing control for changing the period division ratio.
You. The above-mentioned non-equi-periodic frequency dividing circuit 102 has M (
Where M is an integer)N division (for example, (M + 1)
Division)Frequency divider and non-equi-periodic frequency division ratio
The frequency divider divides by M or N by the initial value data
A control signal generator for generating a control signal for controlling
IncludingIs done. [0015]ThisThe control signal generator of the
Carry output to the next stage countern vertical columns
(N ≧)It consists of connected multi-stage counters.
The counter refers to the initial value data and the count value of the next stage counter
In response to theperiodCan be switchedIs done. [0016]The above-mentioned control means sets the control signal generator.
The initial value data to be output to the oscillation frequency of the fixed oscillator and the output signal.
And the frequency of the signal. The frequency of each counter of the control signal generator is
The phase comparator 103 compares the phases based on the end-of-term information.
Create phase comparison timing Create phase comparison timing
Means can be provided. Further, the phase comparison timing generating means
The non-equi-periodic frequency dividing circuit 102 is synchronized with the phase comparison timing.
It can be configured to reset. The control means converts the initial value data into a phase.
The correction initial value data corrected according to the error is obtained in advance and stored.
The phase comparison result information from the phase comparator 103
The correction initial value is given to the non-equi-periodic frequency dividing circuit 102 in accordance with
It can be configured to obtain. The phase-locked oscillator according to the present invention has a normal input.
The unequal period of the unequal frequency divider when the force signal is lost
Keep the previous value as the division ratio
It can be made to have a dover function. [Action]In the non-equi-periodic frequency dividing circuit 102, the frequency divider may be, for example,
Switching to M or (M + 1) frequency division is possible, and a control signal is issued.
Based on the initial value data corresponding to the non-equi-periodic frequency division ratio
Controls whether the divider divides by M or (M + 1)
Generate control signals. This control signal generator
Counter carry output to the next stage counter
It is composed of a plurality of vertically connected counters. Control means
Sets the initial value to be set in the control signal generator for the fixed oscillator.
It is created based on the oscillation frequency and the frequency of the output signal.
In such a configuration,Fixed oscillation generated by the fixed oscillator 101
The frequency is unequally frequency-divided by the unequal-period frequency dividing circuit 102 and
Input to the phase comparator 103, and the input signal
And phase comparison. And the phase error of the phase comparison result is small.
Unequal-period division ratio of unequal-period division circuit 102
Is controlled by the control means 194 so as to change. This
The input signal frequency is an integer of the oscillation frequency of the fixed oscillator 101
Even if it is not double, it performs phase comparison and follows the input signal.
Output signal with a stable frequency. [0022]AlsoEquipped with phase comparison timing creation means
The control signal generator
Phase comparator 10 based on the cycle end information of each counter
3 can create a phase comparison timing for phase comparison
And the phase error detected by the phase comparator 103 can be reduced.
To ensure stable control by minimizing fluctuations
Can be. The position of the phase comparison timing generating means
The non-equi-periodic frequency dividing circuit 102 is synchronized with the phase comparison timing.
When reset, the counter of the non-equi-periodic frequency divider 102
Eliminate discontinuities in count values, etc., and smooth processing
Will be able to do it. In the above control means,Is a productInitial value made
Corrected initial value data obtained by correcting the data according to the phase error
Obtained and held in advance, the phase from the phase comparator 103
The correction initial value is divided by the non-equal period according to the comparison result information.
To the road 102,
Immediate unequal circumference according to the phase comparison result information from the phase comparator
It becomes possible to send initial value data to the period divider 102.
You. You. The phase-locked oscillator of the present invention has a normal input.
When the input signal is lost, the unequal period divider circuit
If you keep the previous one as the circumference ratio,
Continuously generates a signal with almost the same frequency as the output signal of
To implement the holdover function.
Can be. Embodiments of the present invention will be described below with reference to the drawings.
I do. FIG. 2 shows a phase-locked oscillation as one embodiment of the present invention.
Vessels are shown. Figure2, The fixed oscillator 1 has 51.8
It oscillates and outputs a frequency of 4 MHz.
The force signal is input to the phase comparator 2 through the frequency divider 3. The frequency divider 3 divides the input signal by 33 or 34.
Dual-modulus type that divides by any division ratio of division
And a non-oscillator output signal from the fixed oscillator 1
Outputs an output signal of 1.544 MHz by dividing the frequency by an equal period.
It is. The frequency divider 3 controls a non-equi-periodic frequency division described later.
3 when a control pulse is input from the pulse generator 4
By dividing the frequency by 3 to advance the phase of the divided signal, the control pulse
If not input, the frequency is divided by 34 to
PhaseLateIt works to make it work.Specifically, 1.
Since one cycle of 544 MHz is approximately 648 nS,
1.84 MHz divided clock (approximately 1.571 MHz)
One cycle of z) is approximately 637 ns and a phase advance of -11 ns
, A 51.84 MHz frequency-divided 34 clock (approximately 1.52
One cycle of 5 MHz) is approximately 656 ns and a phase delay of +8 ns
It becomes.This frequency divider 3 is provided with a control pulse generator 4 described later.
Together, they constitute a non-equi-periodic frequency dividing circuit. Here, the frequency divider 3 operates at a certain time.
The number of times of operation as a 33 frequency divider is the control frequency and the 34 frequency divider is
The number of working times is referred to as the non-controlling number.This embodiment
In this example, the number of times of this control is represented by B, and the total number of times is represented by A.
The total number of times A is the sum of the number of times of control and the number of times of non-control.
And The total number of times A = the number of times of control B + the number of times of non-control. The control pulse generator 4 has a frequency division ratio of the frequency divider 3.
A control pulse for performing the switching of the
Initial value data k [0], k from the
[2]... K [19], the frequency divider 3
Non-equi-periodic division ratio (ie, 51.84 / 1.544 =
33.57612953 ...)
1.544 MHz of the frequency divider 3 as an operation clock
Output from a phase comparison timing creation unit 7 described later.
Reset and initial value loading by timing pulse
Is to be done.This control pulse generator 4
Is the number of controls B calculated by the method described below and the total
When dividing frequency by B / A (B for A) based on body frequency A
And the following formula (Equation 1) Generates control pulses to achieve the non-equi-periodic division ratio expressed by
Is a circuit configuration that realizes this equation
It is. FIG. 3 shows a schematic structure of the control pulse generator 4.
An example is shown. As described above, this control pulse generator 4
Is a control pulse for controlling the unequal period division ratio of the frequency divider 3.
51.8 as a non-equi-periodic frequency division ratio
To divide the frequency from 4 MHz to 1.544 MHz unequally,example
In order to control the accuracy of ± 40 ppm, for example,An example
For example, do not set the unequal-period division ratio by taking the average for one second.
In other words, the vertical connection of 21 counters is more accurate.
Therefore, if average control is performed with data for 8 seconds, 26 steps
The vertical connection of the counter is necessary.ExampleThen
A 20-stage counter is used. That is, as shown in FIG.
4 uses an input clock of 1.544 MHz as an operation clock.
(A0), (a1), ... (a19)
20 counters 40 each performing a counting operation₀~ 40
₁₉And their counters 40₀~ 40₁₉Count value of
20 comparison / judgment circuits 41 for monitoring and making a comparison / judgment₀~
41₁₉Consists of Each counter 40₀~ 40₁₉Carry of
The output is sequentially counted to the lower counter with the larger number of divisions
Entered as a value. The control pulse is the top counter 4
0₀Judgment circuit 41 for comparing and judging₀From
TA 40₀Counter value C_a0= K [0]
Is output to In this configuration, each counter 40₀~ 40₁₉
Is the lower one, that is, the number of (an) increases
The number of divisions increases as the
Counter 40_nIs the upper counter 40_n-1Leaves the carry
When no force is applied, the lower counter 40_{n + 1}To
Configuration should not be output.These mosquitoes
Unta 40 ₀ ~ 40 ₁₉ Is, as described above, the frequency divider 3
Using 1.544 MHz as the operation clock, the frequency divider 3
It operates in synchronization with the clock output from the
The lower counter (upper counter) is the upper counter
(Lower counter) controlled by carry. For example,
If a simple decimal counter is configured,
When the car gives a carry (it becomes 9), the next clock
The tens place counter is incremented by one, and the ones place
And the tens counter both carry out (99
), And the next clock has one hundredth counter
When counting up, the same operation is performed. Each counter 40₀~ 40₁₉(A
0), (a1)... (A19) are initial values k
[0], k [1],... K [19] and each comparison and judgment circuit
41₀~ 41₁₉Is determined based on the determination result. this
These initial values k [n] are based on the number of times of control and the number of times of non-control described above.
Then, the control counter initial value creating unit 5 creates the initial value. For example, the comparison judgment circuit 41_TwoCorresponds to
Counter 40_TwoCount value C_a2Monitoring
And the count value C_a2Is the initial valuek [2]When becomes
Previous stage counter 40₁A1 = k [1]
+1; otherwise, a1 = k [1]
The result of the determination is output so as to set. (An) base counter 40_nofDivision numberTo k
As a method of switching between [n] base and k [n] +1 base
Is an (an) base counter 40_nTok [n]+1 decimal counsel
Data,an = k [n]When you do
Count value C before und_nAdd 1 to
Such methods are possible.That is, k [n] / k [n]
As a method for operating as a +1 counter,
The initial value of the counter as k [n] or k [n] +1.
Instead of comparing the count value with the initial value, a counter
Is always set to k [n] +1 and the counter is set to “1”.
Counting from "2" and counting from "2"
Is switched to respond. Now, the counter 40_nIs the initial value k [n] of
In the case of “0”, the counter 40 in the preceding stage_n-1For
Increase its initial value by oneIf you do not control (+1)
Absent. That is, the counter whose initial value is “0” counts.
Must not participate in the work, so cows with an initial value of "0"
No counter stages are required. The comparison and judgment circuit 41_nCouncil in
G value C_nIs compared with the initial value k described above.
It is not necessarily limited to [n].
For example, setting "1" or k [n] / 2
It may be.That is, in the above example, the count value is
When the value becomes large (when it matches the initial value), it goes up by one
Counter cycle is increased by one.
To increase the cycle of Taunta by one at the beginning of
Or in the middle of counting (that is, k [n] / 2
) To increase the cycle of Taunta by one.
Good. Depending on which of these methods is used, the same
Output clock phase obtained when a control pulse train is given
Changes, but as long as they operate in the same one way,
It does not change in the middle, and this phase difference
The final output phase that is reflected in the comparison result
Will be the same. Therefore, any of these methods can be used for ease of circuit configuration.
What is necessary is just to select whether to use. FIG. 4 shows an outline of the control counter initial value creating section 5.
A schematic configuration example is shown. Here, as mentioned above,
The number of times is the number of times the output frequency of the fixed oscillator 1 is divided by 34,
The control count B is the number of divisions by 33, and the total count A is not controlled.
Number of times + number of times of control B. Note that this non-control count and control
The value of the number of times is determined by the output frequency of the fixed oscillator 1 (that is, 5
1.84 MHz) and the required frequency (ie 1.544 MHz)
z) determines the non-equi-periodic frequency division ratio required by frequency divider 3.
Then, it can be determined as a value corresponding thereto.concrete
Is a master clock (fixed) of 51.84 MHz in this embodiment.
Using the output frequency of the constant oscillator 1) (1.54
4M), the total number of times A is 1,
544,000 Control times B × 33 + non-control times × 34 = 51,840,
000 Total number of times A = 1,544,000 = Control number B + Non-control
Number , The control frequency B for dividing by 33 is 656,00
The number of non-control operations for dividing 0 times and dividing by 44 is 888,000 times.
Is calculated. Reference numeral 51 denotes a division for calculating the initial value k [n].
An arithmetic unit that converts the data in the numerator setting unit 52 into a denominator setting unit 53
And quotient and remainder are output. This divider 51
May be constituted by a subtraction circuit. Here, the divider 51
The quotient obtained as a result of this calculation becomes the initial value k [n], and the remainder
Is the minute for the division calculation to find the next initial value k [n + 1].
The value of the mother is set in the denominator setting unit 53, and
The value previously set in the denominator setting unit 53 is the numerator setting unit
52 is set. The control counter initial value creation unit 5 first
A method of obtaining the period value k [n] will be described with reference to the flowchart of FIG.
You. First, the values of all initial values k [0] to k [19] are
Clear the held register and set the total number of times A
The control count B is set in the denominator setting section 53 in the setting section 52, respectively.
(Step S1), and division of the numerator / denominator by the divider 51
Is performed (step S2). Initialize the resulting quotient
Stored as k [0]. Also set in the denominator setting unit 53
The value that has been set is transferred to the numerator setting unit 52, and division
The remainder obtained as a result is set in the molecule setting unit 53 (step
Step S3), the division is again performed by the divider 51 (step S3).
S2) The obtained quotient is set as an initial value k [1]. Below,
Is repeated until the remainder becomes "0".
Determine the value k [n] and process when the remainder becomes "0"
To end.Specifically, 51.84 MHz of this embodiment
Using master clock (output frequency of fixed oscillator 1)
To create a signal of 1 second (1.544 MHz)
Calculates the initial values by the above method. k [0] = 2 k [1] = 2 k [2] = 1 k [3] = 4 k [4] = 1 k [5] = 4 k [6] = 0 ...Becomes Therefore, the non-equi-periodic division ratio is (Equation 2) When this equation is realized by the circuit configuration of FIG. Zero-order counter: frequency division by 2 Primary counter: Divide by 2 Secondary counter: 1 division Tertiary counter: divided by 4 4th counter: 1 division Fifth-order counter: divided by 4 Becomes In this case, the counters of the sixth and subsequent orders have an initial value of 0.
Therefore, it does not contribute to the counting operation. In this example, the total number of times A and the number of times of control B
The initial value k [n] is determined based on
The invention is not limited to this.
Using the number of times of control, based on the number of times of non-control and the number of times of control B,
Alternatively, the initial value may be determined. In this case, the initial value k [0]
When calculating, the number of uncontrolled times is the numerator and the number of controlled times is the
To divide. In this way, control and non-control
When switching by output, add `` frequency × control time ''
This counter controls the number of non-controls after one control.
In the case of controlling, "non-control number" is given. That is, the figure
Counter 40 at the top of the control pulse generator 4₀To
A (a0 + 1) base counter is used. The lead / lag data selector 6 is provided with a phase comparator 2
The phase comparison result signal from the
Data obtained by correcting the initial value created by the
Control pulse generator 4 based on the phase comparison result of
To pass. That is, the lead / lag data selector 6
Is based on the initial value from the control counter initial value creation unit 5.
Depending on the lead / lag of the phase of the input clock and the output signal
Set non-equi-periodic frequency division ratio to eliminate lead / lag
Compensation initial value to be calculated and stored in advance, and phase comparison
The phase comparison result from the detector 2 is advanced or delayed according to whether it is advanced or delayed.
Control pulse generation by selecting the correction initial value corresponding to the
Hand over creature 4Specifically, this initial correction value is controlled.
The “advance control data” created by the
Data and delay control data.
A fixed value m is added to the initial control value B.
(B + m) or (B-m) obtained by addition or subtraction
Is an initial value calculated based on This m is the system
Although it is obtained by calculation at the time of design, for example, 0.00
It can be set to be about 5 ppm or the like. The frequency divider 8 is a phase comparison timing generator 7
A frequency divider for creating the specified time to be used.
1.544 MHz input from 3 is divided by 65,536
0.042SecondGenerates a pulse with a specified period and generates a phase ratio
This is supplied to the comparison timing creating unit 7.This specified time is
It is set for such a reason. In other words, the dice according to the present invention
Digitally controlled phase-locked oscillator.
In order to perform the same operation as a phase-locked oscillator,
Switching of control frequency (that is, phase comparison) in a short time
I prefer to go, but not too long
With time, the phase actually changes even when the control frequency is switched.
It does not always change, resulting in useless switching operation. Can get. An example
For example, according to the results of computer simulation, 0.1 seconds
Below this level, even if the control value is switched,
It turns out that the same series of signals (control pulses) are generated
ing. Therefore, if the maximum cycle is three times the specified time,
The counter while keeping the total time to about 0.1 seconds.
As a result of examining the value that simplifies
Divided by 36 (approximately 0.13 in the case of a cycle three times 0.042 seconds)
Seconds) is set. The phase comparison timing generator 7 controls the control pulse
The carry signal of the counter of each stage of the generator 4 is inputted.
And the detection of the phase comparator 2 based on these carry
Phase error is stable and each stage of the control pulse generator 4
Extracts the timing when the counter is virtually clear
At that timing, the timing pulse is output to the phase comparator.
2 for the frequency divider 8 as the phase comparison timing.
Control pulse generation as reset timing
Reset and load timing for unit 4
Is to give. This phase comparison timing generator 7
The detailed operation will be described later. The operation of this embodiment will be described below.
The control counter initial value creation unit 5 calculates the oscillation frequency of the fixed oscillator 1.
Based on number 51.84 MHz and output signal frequency 1.544 MHz
Unequal-period division ratio of the frequency divider 3
Calculate the number of times of control and the number of times of non-control to obtain the period division ratio.
Control pulse generator 4 based on the number of times of control and the number of times of non-control
Calculates the initial value k [n] of each counter of
Sent to the control pulse generator 4 via the delay data selector 6
You.To restate the specific values calculated earlier, Control frequency B = 656,000 Non-control times = 888,000 Total number of times = 1,544,000 And the initial value is k [0] = 2 k [1] = 2 k [2] = 1 k [3] = 4 k [4] = 1 k [5] = 4 k [6] = 0 ...It is. The control pulse generator 4 calculates the initial value k [n].
Each counter 40 based on₀~ 40₁₉Control the control
The frequency is generated and sent to the frequency divider 3.Each of the above calculated values
A specific example of the generation pattern of this control pulse based on
And 33 division by the output of the control pulse
“A”, 34 due to no control pulse output
When the frequency division is represented by "b", it is shown in FIG.
Sea urchin b → b → a → b → a → b → b → a → b → a → b → a → b
→ b → a → b → a... This pattern is 19
Generates a control pulse only 82 times during 3 clocks
Thus, control is performed in a 193 clock cycle, and this cycle is 1
/ 8000 seconds (125 μs). In the frequency divider 3, it is assumed that a control pulse has been input.
When the frequency is not input, the frequency is divided by 34.
YouRukoAnd non-equi-periodic frequency division, and the input 51.84
The frequency is divided from 1.5 MHz to 1.544 MHz.That is, the number of control
And the total number of non-control times is 1.544 × 10 ⁶ And Frequency division
The number of input clocks to the unit 3 is 33 × 656,000 + 34 × 888,000 = 51.
84 × 10 ⁶ It is. The phase comparator 2 generates a phase comparison timing.
At the timing when the timing pulse is input from the unit 7,
Output signal of frequency divider 3 and input clock (including jitter etc.)
1.544 MHz) and the phase error (lead
/ Delay information) to the advance / delay data selector 6. The lead / lag data selector 6 calculates the phase error
Initial correction based on information to eliminate the phase error
The value is selected and sent to the control pulse generator 4. The phase comparison timing generator 7 controls the control pulse
Carry of each stage counter from generator 4 and frequency divider 8
Timing pulse based on the notification information of the specified time
appear. The phase ratio is determined by the timing of this timing pulse.
The comparator 2 performs a phase comparison, and the control pulse generator 4
Reset in synchronization with the initial value of each stage (control pattern
Switch). Next, the phase comparison timing generator 7
The creation of the phase comparison timing will be described. Control pal
The control output signal of the generator 4 causes multi-order vibration
The phase is changing. High frequency and large vibration amplitude
If the timing is set at a low-order oscillation cycle, the phase leads / lags
Becomes stochastic, and the phase obtained at each timing changes.
Moving width is large. Therefore, the vibration cycle is long and the vibration amplitude
Each timing with a small high-order vibration cycle
Phase comparison is performed so that the fluctuation range of the phase obtained in
It must be made. Specifically,N-stage counter with phase
The number of stages of the counter that takes out the comparison timing is the αth stage.
Then,In an N-stage configuration counter as shown in FIG.
Therefore, the count value of the controlled signal up to the α stage is small.
Immediately before resetting (the counter in the α-th stage is reset
The cycle of the α-th stage has been completed at
Therefore, the phase condition is the most stable
This is the phase comparison timing. That is, control
The counter at the α-th stage of the pulse generator 4 outputs a carry.
Is a phase comparison timing.Paraphrase
For example, an N-stage (e.g., three-stage) counter is non-equi-
Perform frequency division And a signal having a phase output as shown in FIG.
It is what is done. In FIG. 6, the cycle of the primary counter is completed.
Output phase change at the end is primary oscillation, secondary counter
The change of the output phase at the completion of the cycle is secondary vibration. As well
The change in the output phase at the completion of the cycle of the tertiary counter is tertiary.
Vibration. As shown in FIG.
The phase at the completion of the data cycle is the completion of the cycle of the lower-order counter.
It can be seen that the phase is more stable than at the time. Low order
When phase comparison is performed with the phase at the
Because the phase of the signal has changed significantly, it is
Instead, the point of completion of the cycle of the higher-order counter is
It can be seen that it is desirable to perform the imaging. However, the counter at the α-th stage outputs carry.
If it takes a very long time to apply force,
It is inconvenient that no phase comparison is performed
Therefore, based on the condition as shown in FIG.
Generate the phase comparison timing by the method of (1) or (2)
I do. (1) The cycle has not ended before the specified time
Phase comparison of the cycle timing of the lowest order counter
The specified time is 65536/1, as described above.
544000 = 0.042 seconds. Exceeding this specified time
N-th counter that does not output carry before
(The counter at the (N-1) th stage outputs a carry.)
The phase comparison time is set when the carry is issued after the specified time has elapsed.
This is a method for making a picture. [0056]In addition,Control pulse generator 4 within specified time
If the cycle of the counter with the maximum number of stages has ended
If (the carry is output), the specified time
The cycle of the counter of the maximum number of stages ends first after exceeding
(When the carry is output)
Ming. This is the case of the term in FIG.This is concrete
As an example, create 1.544MHz from 51.84MHz
In this case, the division by 33 is 656,000 times, and the division by 34 is
Generate 888,000 times and control Do. In this case, 6
56,000 / 1,544,000 = 82/193 and about
Control at 193 clock cycles
This period is 1/8000 second (125 μs),
Sufficiently shorter than the specified time (0.042 seconds)
There is a counter whose cycle has not ended before
Absent. Therefore, in such a case, the maximum
The phase comparison timing is the time when the cycle ends first.
It is. (2) Termination method at three times the specified time The counter of the N-th stage whose cycle is not completed within the specified time
Waiting for the end of the cycle (the carry is output)
This is the same as the above (1). At the N-th stage until the time reaches twice the specified time.
When the taunter cycle ends (carry is output
), The end timing is
And That is, this is the case in the section of FIG. However, even if it reaches twice the specified time, its N
If the cycle of the second stage counter has not ended, the phase comparison
Wait for termination to prevent the cycle from becoming unnecessarily long.
The number of counters is lowered by one to (N-1) th,
(N-1) Phase comparison of the timing at which the cycle of the stage ends
Limit the cycle time by using timing
To do. That is, this is the case of the term in FIG. this
In this case, the cycle of the next lower counter (N-1) is equal to the specified time.
Cycle should be at most 3 times the specified time
Will be completed. Note that the counter of the maximum stage number
If the cycle has ended, the above (1) and
Similarly, after the specified time has elapsed,
The end of the cycle is defined as the comparison timing (see FIG. 7)
reference). As described above, the phase comparison timing generator 7
When the phase comparison timing is determined by
The phase error obtained as a result of the phase comparison has a small fluctuation range.
And stable control becomes possible. Control pulse generation
Unit 4 is a timer that outputs a carry from each of its internal counters.
Ming (ie virtually clearWhenSame stateToBecame Thailand
Reset) and a new initial value is loaded
Therefore, the counting operation is not discontinuous,
A smooth process becomes possible. In the above-described phase locked oscillator, the input clock
In the event that is refused,
When the control pulse generator 4 is in the previous control state (that is,
If you continue to hold the data,
Output 1.544MHz output signal continuously
Can have a holdover function.
it can. The method of giving an external instruction is as follows.
And gives an instruction to the comparator 2 so that the phase comparator 2
Lead / lag signals that do not need to be controlled (signals without phase error)
You may make it always output to the data selection part 6. this
In this case, the lead / lag data selection unit 6 does not switch the selection.
Therefore, the control pulse generator 4 maintains the previous control state.
Will be. Another method for giving an external instruction is as follows.
And gives an instruction to the advance / delay data selection unit 6,
Output data from the leading / lagging data selector 6
Period data) is fixed, and the comparison result from the phase comparator 2 is set.
Regardless of the result, a new phase control is performed by the control pulse generator 4.
May not be performed. Various modifications may be made in implementing the present invention.
Is possible. For example, in the above embodiment, the control counter
The initial value creating unit 5 is composed of a divider composed of a hardware circuit.
However, the present invention is not limited to this.
Optimal clock control using a processor (CPU)
Calculate the division ratio of the pattern or counter
You may. The control counter initial value creation unit 5 is set to R
OM, and control parameters corresponding to various unequal-period division ratios
Calculate in advance the cycle of each stage counter of the loose generator 4.
And store the cycle data in ROM.
An optimal one may be selected from these. This is going
The same applies to the / delay data selection unit 6,
If the control counter initial value creation unit 5
It is preferable that the selection units 6 are put together and stored in a ROM. In the above embodiment, the loop filter is used.
Although the configuration was removed, of course, the output of the phase comparator 2
Insert a loop filter on the side, unnecessary from the phase comparison result
It is also possible to adopt a configuration that can remove high frequency components. In the above-mentioned phase-locked oscillator, the unequal
Suppresses jitter components generated in the period divider
Therefore, the output signal of this phase locked oscillator is further
(Phase-locked loop) input to circuit
Alternatively, pass the output signal of the phase locked oscillator through a bandpass filter.
You may do so. In the above-described embodiment, the phase-locked oscillator
The output signal has almost the same frequency as the input signal
However, the present invention is not limited to this.
Output signal of the phase-locked oscillator via the frequency divider.
The output signal frequency may be changed by changing the signal. Another minute
The output signal from the frequency divider 3 is passed to the phase comparator 2 through the frequency divider.
May be entered, in which case the phase ratio
A phase comparator from the comparison timing generator 7 to the phase comparator 2
It is also configured to input the imaging pulse through the frequency divider.
You. In the above embodiment, the control pulse generator
The counter of each stage in 4 is the counter of the counter of the lower stage.
According to the comparison decision result of the comparison decision circuit based on the
The N / N + 1 base number is switched.
However, the switching pattern is not limited to this.
And calculate and store all
Set when the control pattern of generator 4 is switched
In such a case, the comparison / judgment circuit becomes unnecessary.
You. As described above, according to the present invention,
For example, instead of a voltage controlled oscillator as a reference oscillator,
High stability fixed oscillator can be used and other circuits
Since the part can be composed of digital circuits,
The downsizing and high stability of the vessel can be realized. Also, the phase comparison timing is set to
Stable control is possible by selecting with less timing
Become. Further, a PLL circuit is provided after the phase-locked oscillator.
Or if a bandpass filter is provided, the phase fluctuation
If they do occur, remove them easily.
Can be.

[Brief description of the drawings]

FIG. 1 is an explanatory view of the principle according to the present invention.

FIG. 2 is a diagram showing a phase locked oscillator as one embodiment of the present invention.

FIG. 3 is a diagram showing a control pulse generator of non-equi-periodic frequency division in the apparatus of the embodiment.

FIG. 4 is a diagram illustrating a control counter initial value creation unit in the apparatus according to the embodiment.

FIG. 5 is a flowchart showing an initial value creation procedure in a control counter initial value creation unit.

FIG. 6 is a diagram for explaining how to determine a phase comparison timing.

FIG. 7 is a diagram for explaining a phase determination timing.

FIG. 8 is a diagram showing a conventional phase-locked oscillator.

FIG. 9 is a diagram showing a conventional phase-locked oscillator using a non-equi-periodic frequency divider.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Fixed oscillator 2 Phase comparator 3 33/34 frequency divider 4 Control pulse generator 5 Control counter initial value creation part 6 Lead / lag data selection part 7 Phase comparison timing creation part 8 65536 frequency divider 11 Voltage controlled oscillator 12 Frequency Conversion circuit 13 Loop filter 14 Phase comparator 40 Counter 41 Comparison judgment circuit 51 Divider 52 Numerator setting unit 53 Denominator setting unit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03L ⁷ /06-7/23

Claims (6)

(57) [Claims] 1. A fixed oscillator (101) for oscillating at least one fixed frequency, and an unequal-period division ratio variable type non-equi-periodic division ratio for converting the oscillation output signal of the fixed oscillator by non-equi-periodic division. A frequency dividing circuit (102) , which is divided by M or N (where
M and N are integers) switchable frequency divider and unequal period
Based on the initial value data corresponding to the frequency division ratio, the frequency divider
Control signal for controlling whether to divide or divide by N
Control signal generator, the control signal generator
The carry output of the counter is input to the next stage counter.
And a counter connected in n stages (n ≧ 2).
Each counter has its cycle set by referring to the initial value data.
And the cycle is cut according to the count value of the next stage counter.
A phase comparator (103) for comparing the phase of an input signal with the output signal of the non-equi-periodic frequency divider; and a phase error based on the phase comparison result of the phase comparator. Control means (104) for performing control to change the unequal-period division ratio of the unequal-period division circuit so as to eliminate the occurrence of the control signal
The initial value data to be set in the generator is the oscillation frequency of the fixed oscillator.
Number and the frequency of the output signal.
Phase locked oscillator comprising a a which is. 2. The frequency divider according to claim 1 , wherein said frequency divider is divided by M or (M + 1).
2. A frequency divider comprising a switchable frequency divider.
The placement of the phase-locked oscillator. 3. The phase comparison timing generating means according to claim 1, further comprising: phase comparison timing generation means for generating phase comparison timing for phase comparison by said phase comparator based on cycle end information of each counter of said control signal generator. Phase locked oscillator. 4. A phase comparison timing generating means according to claim 3 Symbol placement of the phase-locked oscillator in synchronism with the phase comparison timing is configured to reset the non-like cycle divider. Wherein the control means, the Initial value data may be held in advance obtain correction initial value data corrected according to the phase error, the correction initial depending on the phase comparison result information from the phase comparator The phase-locked oscillator according to any one of claims 1 to 4, wherein a value is provided to the non-equi-periodic frequency dividing circuit. 6. A non-equi-periodic frequency divider having a hold-over function by retaining a previous non-equi-periodic frequency division ratio when a normal input signal is lost. Item 6. The phase-locked oscillator according to any one of Items 1 to 5 .