JP2777368B2 - Frequency synthesizer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly, to a frequency synthesizer that outputs a signal whose frequency is not limited to an integer but is an arbitrary fraction of a reference frequency. 2. Description of the Related Art A conventional frequency synthesizer that outputs a signal that is a fractional multiple of the frequency of a reference signal is disclosed in Japanese Patent Application Laid-Open No. 61-109324. This conventional frequency synthesizer will be described with reference to FIG. In FIG. 5, 1 is a reference signal source, 2 is a voltage controlled oscillator (VCO), 3 is a frequency divider, 4 is a phase comparator, 5 is a loop filter amplifier, 9 and 10 are registers, and 11 is an adder. is there. This conventional frequency synthesizer has two registers
The adder 11 uses the output of the frequency divider 3 as a clock, adds the output values of the two registers 9, 10 and outputs the result to the register 10, and when an overflow occurs during the addition. Changes the frequency division ratio of the frequency divider 3 from N to N + 1. The operating principle of the conventional frequency synthesizer shown in FIG. 5 is as follows. For example, the output frequency is , The value of the decimal part A is entered in the register 9.
Then, each time there is an output from the frequency divider 3, the value of the register 9 and the value of the register 10 are added, and the decimal part of the added value is input to the register 10. Also, when there is a carry to the integer part, the adder 11 overflows and changes the frequency division ratio of the frequency divider 3 from N to N + 1. This is repeated each time there is an output from the frequency divider 3. By doing so, of the 10 pulses output from the frequency divider 3, A pulses are obtained by dividing the output of the VCO2 by N + 1, and 10-A pulses are obtained by dividing N. Therefore, assuming that the output frequency of VCO2 is f _VCO and the frequency of one reference signal is f _ref , the number of output waves N _{VCO of} VCO 2 included in the ten pulses output from frequency divider 3 is N _VCO = A · (N + 1) + (10 −A) · N = 10 · N + A Here, the time required for the frequency divider 3 to output 10 pulses is
Assuming T ₀ , From this, the ratio of f _ref to f _VCO is Thus, an output of a frequency multiple including a fraction such as A / 10 can be obtained for the reference signal as well as an integer. [Problems to be solved by the invention] However, in the above-mentioned conventional frequency synthesizer,
Even if a frequency that is a fraction multiple of the reference signal is obtained, the denominator value of the fraction is fixed at 10 and cannot be changed. Only the numerator value can be changed. In this conventional frequency synthesizer, the denominator value is determined by an adder
The decimal number of 11, that is, the value until an overflow occurs.If the decimal adder 11 is used as in the above-described conventional example, the denominator value is 10, the number of digits of the adder 11 is increased to 10 ⁿ , and If a binary adder is used, the value of 2 ⁿ can be used as the denominator. Therefore, for example, if the denominator is 3, a ternary adder may be provided, and if the denominator is 7, a ternary adder may be provided. However, in general, adders other than binary and decimal have a complicated structure, and changing a decimal number requires a large change in hardware. For this reason, in order to use an arbitrary value as a denominator and to be able to change it, there is a problem that a large-scale hardware configuration is required, cost is increased, and a large mounting area is required. Moreover, there is a problem that the operating speed, that is, the frequency of the reference signal which is a clock cannot be increased. An object of the present invention is to eliminate the limitation of the denominator of the fractional frequency dividing ratio by the base value of the adder in the conventional frequency synthesizer, to set an arbitrary denominator, and to easily change the denominator. A frequency divider control circuit which can be realized with a simple hardware configuration, and which can adopt a high reference signal frequency, thereby providing a frequency synthesizer having a wider frequency setting range. . [Means for Solving the Problems] The object of the present invention is to provide a reference signal source, a voltage controlled oscillator as an output signal source, and one of the integers N or M connected to the output of the voltage controlled oscillator and controlled by an external device. A frequency divider that can select a frequency ratio; and a phase comparator that compares a phase difference between an output of the frequency divider and a reference signal from the reference signal source. By limiting and amplifying the frequency as a frequency control signal of the voltage-controlled oscillator.
In the frequency synthesizer performing the L operation, the output of the frequency divider or the reference signal is used as a clock, the number of clocks is counted, the count is output, and when a reset signal is input, the count is reset and the count is reset from the initial value. A counter to start, a memory in which first data for causing the frequency divider to select the integer N and second data for selecting the integer M are written in correspondence with addresses, and are sequentially output from the counter for each count. The count value is taken as an address, the first data or the second data specified by the address is output to the frequency divider, and a reset signal is sent to the counter when the count value of the counter reaches a set value. This is achieved by providing a memory in which data to be output is written. [Operation] A frequency synthesizer that outputs a signal that is a fractional multiple of the reference signal frequency does not divide the VCO output uniformly, but changes the frequency division ratio and outputs a frequency divider output pulse A The number of VCO output pulses included in B out of N
By changing the reference signal The output of fractional frequency is obtained. In the conventional frequency synthesizer, an adder and a register are used as a means for removing the B outputs from the A frequency dividers and changing the frequency division ratio. , With a counter and memory. For example, when the denominator value is K, the counter is a K-ary counter, and two of K are divided by an integer N (K-2).
In order for the frequency divider to repeat the operation of dividing the number of times by the integer M, when the count value of the counter has counted the set value (for example, '3' and 'K'), the predetermined signal for selecting the integer N is divided. Write the data to the memory so that it is output to the container. As a result, the frequency divider performs frequency division while switching between the two frequencies, and the frequency as an average value becomes the target frequency. As described above, it is possible to obtain an arbitrary frequency by setting in the memory how many digits the counter is to be, and writing in the memory how many of them are to be divided by the integer N and the remainder is to be divided by the integer M. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a frequency synthesizer according to a first embodiment of the present invention using a counter as a counting unit and a ROM as a memory unit, and FIG. 2 is a block diagram of the contents of the ROM. In FIG. 1, 1 is a reference signal source, 2 is a voltage controlled oscillator (VCO), 3 is a frequency divider, 4 is a phase comparator, 5
Is a loop filter amplifier, 6 is a counter, and 7 is a ROM. The counter 6 uses the output of the frequency divider 3 as a clock and outputs
M7 output Q _A of the counter 6, Q _B, Q _C, address _{Q D A 0, A 1,} A 2,
D ₁ and D ₀ are output as A ₃ , and the output D ₁ is used as a reset signal of the counter 6, and the output D ₀ is used for frequency division ratio selection control of the frequency divider 6. With such a configuration, the counter 6 counts up using the output of the frequency divider 3 as a clock, and proceeds with the frequency division program stored in the ROM 7. Of the outputs D ₀ and D ₁ of ROM7, D
₀ is used for controlling the frequency division ratio of the frequency divider 3. When a value "1" appears in the output, the frequency divider 3 selects the frequency division ratio N + 1, and when the value is "0", the frequency division ratio N is selected. . Also, D ₁ is used to reset the counter 6, the counter 6 is the address counted up to ROM7 outputs a "7" proceed to the the value "1", the initial value at the next clock input "0" Into the counter 6
The counter 6 is reset. Therefore, in the embodiment shown in FIG. 2, of the seven pulses output from the frequency divider 3 during the circulation of the counter 6, two are N + 1 and five are N. . Accordingly, the relationship between the reference signal f _ref from the reference signal source 1 and the output f _VCO of the _{VCO 2} is Becomes In this case, what determines the denominator value is an address that contains the reset signal of the counter 6, if the setting "11" as the denominator value, the address of the ROM 7 "11" to D ₁ of the " Write 1 ". The numerator value is ROM
Among the data D ₀ of 7 of the address "1" from to address that contains the reset signal, determined by the number of whether "1" is written to. To change the output frequency in this way,
Either rewrite the contents of the ROM 7 or, as shown in FIG. 3, use a ROM 7 'having a large number of address inputs, and give the lower address from the counter 6 and the upper address from the external control circuit. It is also possible to store the frequency division pattern and select the higher frequency address. still,
It goes without saying that RAM can be used instead of ROM. FIG. 4 is a configuration diagram of a frequency synthesizer according to an example in which a shift register is used instead of a count and a wire matrix is used instead of a memory. The In Figure 4, the shift register 8, the frequency divider 3 outputs a clock 1 clock pulse from the output Q _A are sequentially shifted Q _G, and Q _G again Q _A when the pulse comes to a
It returns to "7" clock cycle. When the output of the AND circuit 13 which takes the logical product of two of the outputs of the shift register 8 is used for frequency division ratio control of the frequency divider 3, and one clock pulse appears in the output used for this frequency division ratio control, The frequency division ratio of the frequency divider 3 is set to N + 1, and otherwise the frequency division ratio is set to N. As a result, the ratio between the reference signal 1 and the output of the VCO 2 is the same as in the above-described embodiment, and two of the seven pulses output from the frequency divider 3 during one cycle of the shift register 8 are N + 1 minutes. The lap and the five laps are divided by N, Becomes In this case, it is the cycle of the cyclic operation of the shift register 8 that determines the denominator value, and the cycle can be changed by changing the number of stages of the shift register. For example, when “11” is set as the denominator value, it is necessary to add four more stages of the shift register and to input the outputs of the four shift registers to the NOR (NOR) circuit 12. Conversely, when "3" is used as the denominator value, the number of outputs of the shift register 8 input to the NOR circuit 12 may be reduced from six to two.
Is reduced from “7” to “3”, and the cycle of the circulation operation is “3”. The numerator value is determined based on how many of the outputs of the shift register 8 are used for controlling the frequency divider 3. If the denominator value is changed from “2” to “4”, 2 is added. What is necessary is just to input the output of the shift register 8 to the AND circuit 13. To change the output frequency in this way,
AND circuit 13 and NOR circuit 12 of the output of shift register 8
It is sufficient to change the way of connection to, and if this connection can be arbitrarily made using a switch or a gate, it can be easily changed. [Effects of the Invention] According to the present invention, a denominator value and a numerator value of an arbitrary value can be selected in a frequency synthesizer that outputs a signal that is a fractional multiple of the reference signal frequency, so that a finer output frequency can be set. Therefore, the number of reference signal sources such as crystal oscillations can be reduced, which is effective for cost recommendation of the frequency synthesizer. In addition, since the hardware is simple and suitable for high-speed operation, the reference frequency can be increased, which is also effective in reducing noise spurious of the output of the frequency synthesizer.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a frequency synthesizer according to a first embodiment of the present invention, FIG. 2 is a block diagram of the contents of a ROM shown in FIG. 1, and FIG. 3 is a block diagram of FIG. FIG. 4 is a configuration diagram of a frequency synthesizer according to an example using a shift register and a wire matrix, and FIG. 5 is a configuration diagram of a conventional frequency synthesizer when a large-capacity ROM is used instead of a ROM. . 1. Reference signal source, 2. VCO, 3. Divider, 4.
Phase comparator, 5: loop filter / amplifier, 6: counter, 7: ROM, 8: shift register, 12: NOR (NOR) circuit, 13: AND circuit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03L 1/00-7/26

Claims (1)

(57) [Claims] A reference signal source, a voltage-controlled oscillator that is an output signal source, a frequency divider connected to an output of the voltage-controlled oscillator and capable of selecting one of an integer N or M by an external control, A phase comparator for comparing the phase difference between the output of the frequency divider and the reference signal from the reference signal source. The output of the phase comparator is band-limited and amplified to control the frequency of the voltage-controlled oscillator. In a frequency synthesizer that performs a PLL operation by using a signal, the output of the frequency divider or the reference signal is used as a clock, the number of clocks is counted, the count value is output, and when a reset signal is input, reset and reset again. A memory in which a counter that starts counting from an initial value, and first data that causes the frequency divider to select the integer N and second data that causes the frequency divider to select the integer M are written in correspondence with addresses. The count value sequentially output from the counter for each count is taken as an address, the first data or the second data specified by the address is output to the frequency divider, and the count value of the counter is set to a set value. And a memory in which data for outputting a reset signal to the counter when the number reaches a predetermined value is stored.