SU1483632A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering and m. used to obtain a discrete grid of stable frequencies from a single source of reference oscillations. The purpose of the invention is to reduce power consumption from a power source. The digital frequency synthesizer contains tunable rr 1, frequency divider 2 with variable division factor (DDC), phase detector 3, amplifier 4, direct current, analog adder 5, low pass filter 6, block 7 of reference frequencies, two DACs 12 and 13 To achieve the goal, a code change block 8 is entered, the adder 9 codes and two accumulators 10 and 11. Since the division factors of the DPDK 2 by a value of ± 1 are changed using the adder 9 via the set input of the PDKD 2 at a frequency N ₁ times lower -pa 1, then reduced power consumption from n sources Itani. Connecting the clock inputs of the accumulators 10, 11 and block 8 with the output of block 7 also makes it possible to reduce the fine tuning time to the desired frequency. 1 il.

Description

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The invention relates to radio engineering and can be used to obtain a discrete grid of stable frequencies from a single source of reference oscillations.

The aim of the invention is to reduce power consumption from a power source.

The drawing shows an electrical structural diagram of a digital frequency synthesizer.

The digital frequency synthesizer contains a tunable oscillator 1, a divider 2 frequencies with a variable division factor (DCD), a phase detector 3, an amplifier 4 constant

current, analog adder 5, filter

de reference frequency at the second output of the code change block 8 appears O, which leads to a decrease in the output code of the adder 9 and the division ratio of the DPCD 2 to the value N n, + 1,

As a result, the average division ratio of the PDCD 2 for the period remains equal to n, + 2.

In the next period of the reference frequency, the lower frequencies, the reference frequency block 7 (BOC), the code change block 8, 20 adder 9 codes, the first drive 10, the second drive 11, the first digital-analog converter (DAC) 12, the second DAC 13.

A digital frequency synthesizer of operation — the code change block 8 returns as follows: in its initial state, the coefficient is

Tunable oscillator 1, DPKD 2, phase detector 3, amplifier 4, analog summator 5 and filter 6 rev.

thirty

Phase self-tuning ring is expanded. With the integer division ratio of the DPCD 2 (n,), the code input of the first accumulator 10 receives the code zero (n, 0). The transfer signal in the first drive 10 is missing, and the amount code 35 on the code output of the first drive 10 can be any, quasi-random. If the code inputs n 2 of the first accumulator 10 give the code of some number and then turn off 40 of it, then the code output of the first accumulator 10 can also have a quasi-random code. The code of the sum of the second accumulator 11 is changed after the passage of the DPCD 2 before the arrival of the next transfer pulse is equal to n, + 2.

If in the first accumulator 10 the code at the output of the sum is zero, then at the output of the transfer of the second accumulator 11 there are no transfer pulses and the division ratio of DPDD 2 in each division period is equal to n (+ 2.

When fractional bits are turned on, the code input of the first accumulator 10 carries the transfer pulses from the transfer output of the first accumulator 10 to the adder 9, summed in it with the integer part code and in some periods of the PDKD 2 increases its division ratio by one.

The code inputs of the second accumulator 11 each period of the reference frequency pulse with the DRC 7. Transmit pulses receive a different code, and the input from the second accumulator 11 is fed to the input of the code change unit 8, which changes the code by + 1 In the initial state, from the first output of block 8, which JQ ry changes the code by +1, to the input of the first digit of the adder 9 it enters O, and from the second output, which changes the code by -1, to the input of the second bit 55 of the adder 9 enters 1. As a result, the code arriving at the Marketing input of the adder 9 (n), its output / increased by two units and the code transfer of the second accumulator 11 are pulses with a variable law sequencers. By the same law, the modulation of DPKD 2 division coefficients occurs.

For additional analog compensation, the first and second outputs of the code change unit 8 are connected to the inputs of the second D / A converter 13 with corresponding weights, the output of which is in the form of a mirror image of the function of changing the division factors. This signal compensates for changes in the DPKD 2 division ratio becomes N 2.

When a transfer pulse arrives, level 1 appears at the input of block 8 of the code change at its first output for a time equal to two periods of the reference frequency from the output of the DRF 7 or two periods of oscillations from the output of the PDDK 2, which is typical of synchronization mode. The occurrence of a unit by two periods leads to an increase by one of the output code of the adder 9. The division coefficient of the DPCD 2 is equal to j. In the next period

de reference frequency at the second output of the code change block 8 appears O, which leads to a decrease in the output code of the adder 9 and the division ratio of the DPCD 2 to the value N n, + 1,

As a result, the average division ratio of the PDCD 2 for the period remains equal to n, + 2.

In the next period of the reference frequency DPKD 2 before the arrival of the next transfer pulse is equal to n, + 2.

If in the first accumulator 10 the code at the output of the sum is zero, then at the output of the transfer of the second accumulator 11 there are no transfer pulses and the division ratio of DPDD 2 in each division period is equal to n (+ 2.

When fractional bits are turned on, the code input of the first accumulator 10 carries the transfer pulses from the transfer output of the first accumulator 10 to the adder 9, summed in it with the integer part code and in some periods of the PDKD 2 increases its division ratio by one.

At the code inputs of the second accumulator 11, each period of the reference frequency receives a different code, and

The transfer of the second accumulator 11 p are pulses with a variable law of succession. By the same law, the modulation of DPKD 2 division coefficients occurs.

For additional analog compensation, the first and second outputs of the code change unit 8 are connected to the inputs of the second D / A converter 13 with corresponding weights, the output of which is in the form of a mirror image of the function of changing the division factors. This signal compensates for changes in the fission coefficients associated with the formation of transfer pulses of the second accumulator 11, i.e. the modulation of the division factors, and the changes associated with the change in the sum at the code output of the second accumulator 11, are compensated for using the first DAC 12.

The signals of the first and second D / A converters 12 and 13 are fed to an analog adder 5 with their own weighting factors, which depend on the parameters of the phase locked loop.

Since the change in the division ratio of the PDDK 2 by the value of fl is made using the adder 9 by the installation input of the PDKD 2 at a frequency n times lower than the frequency of the tunable generator 1, this reduces the power consumption from the power sources. Connecting the clock inputs of the first and second accumulators 10, 11 and block 8 of the code change with the output of the DRC 7 also allows you to reduce the fine tuning time to the desired frequency, since the program for controlling the division coefficients in PDCD 2 does not depend on its input frequency.

Claims (1)

Invention Formula A digital frequency synthesizer containing a tunable tunable oscillator, a variable divider frequency divider, a phase detector, an amplifier ten 15 836326 a direct current, an analog adder and a low-pass filter, a block of reference frequencies whose output is connected to another input of a phase detector, the first and second digital-to-analog converters, whose outputs are connected to the second and third inputs of an analog adder, respectively, that, in order to reduce power consumption from the power source, the first drive, the second drive, the code change unit and the code adder, the output and transfer input of which are connected respectively, are entered into it Respectively to the installation input of the frequency divider with a variable division factor, and to the transfer output of the first accumulator, the information output. The second accumulator is connected to the input of the first digital-to-analog converter, the clock inputs of the first accumulator, the second accumulator and the code change block are combined and connected to the output of the reference frequency block, the second output of the code change block is connected to the second input of the code accumulator 30, and the first and second outputs The code change unit is connected respectively to the first and second inputs of the second digital-to-analog converter, the code inputs of the first accumulator and the code adder are respectively the fractional input and the input of the integer part of the division coefficients. 20 25 35