SU1677871A1 - Digital frequency synthesizer - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase the spectral frequency of the output oscillations. The digital frequency synthesizer contains a reference oscillator 1, a frequency-phase detector (PFD) 2, the first oscillator 3 of a stable current (GTS). second 4 and third 5 GTS, low pass filter 6, controlled oscillator 7, frequency divider 8 with variable division factor, synchronizer 9, AC amplifier 10, voltage comparator 11, reversible counter 12, digital analogue converter (DAC) 13 In synchronization mode, pulses are formed at the first output of the FPD 2, the duration of which is proportional to the phase shift of the signals at the inputs of the PFD 2 and is equal to the duration of the gating pulses at the second output of the synchronizer 9. When the currents of the first and second GTS are not equal to 3.4, e amplifier 10 produces a pulse signal, depending on the form of which, at one of the two outputs of the comparator 11, a signal is generated by which the code of the number in the reversible counter 12 is changed, the output signal of the DAC 13 changes the value of the current of the second GTS 4 to the side reducing the absolute value of the difference between the currents of the first and second GTS 3.4. 3 il. w Ё

Description

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The invention relates to radio engineering and can be used in transceiver radio measuring devices. The aim of the invention is to increase the spectral purity of the output oscillations.

Figure 1 shows a structural electrical circuit of a digital frequency synthesizer; figure 2 - timing charts of his work; Fig. 3 shows an embodiment of a synchronizer.

The digital frequency synthesizer contains a reference oscillator 1, a frequency-phase detector (FFD) 2, the first stable current generator 3 (GTS), the second GST4, a third GTS 5 filter, 6 low-pass filter 6, a controlled oscillator 7, a frequency divider 8 with a variable division factor (DPKD), synchronizer 9, AC amplifier 10, voltage comparator 11, reversible counter 12 and digital-to-analog converter (DAC) 13.

Digital frequency synthesizer works as follows.

In synchronism mode, the output signal of the controlled generator 7 through DPCD 8 is fed to the first input of FPD 2, the second input of which receives the signal of the reference generator 1. At the first exit of FFD 2, pulses are formed, the duration of which is proportional to the phase shift of the signals at the inputs of PFD 2 and is equal to the duration of the gating pulses at the second output of the synchronizer 9, which is fed to the input of the second GTS 4, the signal from the first output of the FFD 2, passed through the synchronizer 9, is fed to the input of the gating of the first GTS 3. When the absolute values are equal the values of the currents of the first and second GTS 3,4 current pulses acting on the input of the filter 6, are mutually compensated, which leads to a decrease in the level of side components in the spectrum of the output signal.

To maintain the equality of the absolute values of the currents of the first and second GTS 3.4, amplifier 10, comparator 11, reversible counter 12, and DAC 13 are used throughout the entire temperature range. In synchronization mode, the pulse of the second output of the synchronizer 9 ( Fig. 2a), to the input of the first GTS 3 - regulating pulses from the first output of the synchronizer (Fig. 26). At the input of the amplifier 10, because of the inequality of the absolute values of the currents of the first and second GTS 3.4, a pulse signal is formed (Fig. 2c), form of which depends on the ratio of these currents (in the left part there are voltage diagrams at Igst 12gst, in the middle part - with hrcT

l2K, r, and on the right, with Ngst 12gst. After the amplifiers 10 a pulse signal (FIG. 2 g) is fed to the input of the comparator 11, which is designed as a two-level comparator and, depending on the waveform at the output of the amplifier 10, generates at one of the two outputs pulses (FIG. 2d, 2e), which the inputs of the reversible counter 12, change the code recorded in

its number, the output signal from the output of the DAC 13 (Fig. 2g), affecting the current input of the second GTS 4, changed the absolute value of the current of the second GTS 4 in the direction of decreasing the absolute value

current difference (Igst-2gst).

By choosing a specific gain of the amplifier 10 and the levels of the reference voltages of the comparator 11, any predetermined level can be achieved

suppressing side components in the output spectrum. The third GTS 5 is designed to compensate for all possible leakage currents of elements.

The synchronizer 9 forms a constant (in synchronism mode) in duration the pulse at the second output and ensures the synchronism of the leading edges of the gating pulses at the first and second outputs. The duration of the pulse generated by the first pulse shaper 14 (FIG. 3) is chosen slightly longer than the delay value of the formation of the FPS pulse 2. The pulse duration generated by the second pulse shaper 15 is chosen larger than the value of the FPS 2 dead band. The pulses generated by the synchronizer through the first and second elements OR 16,17

arrive at the corresponding outputs of the synchronizer,

Thus, in the digital frequency synthesizer, there are no circuit limitations on the magnitude of the level suppression

5 components in the spectrum of the output signal, while maintaining a high short-term frequency stability, constant phase shift between the output and reference signals without losing fast response frequency setting.

Claims (1)

The invention includes a digital frequency synthesizer containing a series-connected controlled oscillator, a variable division divider frequency divider, a frequency-phase detector, a synchronizer, a first stable current generator, a low-pass filter whose output is connected to the input of the uvravlivaemy oscillator, a reference generator, the output of which is connected to the second input of the frequency-phase detector and to the clock input of the synchronizer, the second input and the second output of which are connected respectively to the second output of the frequency-phase detector and to the input of the second stable current generator, the third stable current generator, the output of which is connected to the output of the second stable current generator and the input of the low-pass filter, which is characterized by the fact that, in order to increase the spectral purity of the output oscillations, between the output of the third stable generator current and current supply input of the second stable current generator are introduced in series AC amplifier, voltage comparator, reversible counter and digital-analog converter, while the second voltage comparator output connected to the second input of the reversible counter. 2