JP3210512B2 - Numerically controlled oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a numerically controlled oscillator (NCO: NuCo) used for a frequency synthesizer or the like of communication equipment.
It is related to improvement of merical Controlled Oscillator).

[0002]

2. Description of the Related Art FIG. 5 is a configuration diagram of a conventionally used numerically controlled oscillator circuit. In the figure, reference numeral 101 denotes a phase increase step value Δθ set from the outside as one input,
An adder 102 performs addition with the other input and outputs the result. The adder 102 temporarily stores the output of the adder 101, and uses the reference clock signal _fCLK as an integrated clock to calculate the phase integrated value θ (0 ≦ 0).
θ ≦ 2π) and outputs the calculated value.
1 is a register that feeds back as the other input. In the above configuration, if 2π = 2 ^N , the period T _NCO of the output value θ of the register 102 is expressed by the following equation.

[0003]

(Equation 1)

[0004]

Here, the register 10
In order to improve the accuracy of the output value θ of 2, the method of increasing the word length of data, that is, increasing 2 ^N in the equation (1) is adopted. At this time, the carry operation time of the adder 101 is reduced. To secure the integrated clock signal f _CLK
Will be slow. Therefore, in the conventional configuration, it was difficult to increase the speed of integration and to increase the accuracy of the integrated phase value.

According to the present invention, there is provided a numerically controlled oscillation circuit capable of performing high-speed integration by solving the low-speed operation of the integrated clock signal due to the carry-in operation time of the adder accompanying the increase in the accuracy of the output signal. The purpose is to do.

[0006]

Means for Solving the Problems] numerically controlled oscillator of the present invention, counter divides the reference clock signal f _CLK supplied from the outside, and outputs the _{f CLK / 2, f CLK /} 4, f CLK / 8 And the phase increase step value Δθ set from the outside
Is multiplied by 2 ⁿ (n = 0, 1, 2, 3) to obtain phase information Δθ, 2
A ｛× 2 ⁿ ｝ circuit that outputs Δθ, 4 ・ Δθ, and 8 ・ Δθ, and a first circuit that takes the output value of 8 ｛Δn of the ｛× 2 ⁿ ｝ circuit as one input and adds the other input The adder and the output value of the first adder are temporarily stored, and the phase integrated value {8 · Δθ is calculated according to the timing of the clock signal f _CLK / 8.
A first register which outputs as the other input and feeds back as the other input of the first adder, and an output value of the first register which is set to the output value of the ｛× 2 ⁿ ４4 · Δθ as one input. A second adder for performing subtraction processing with Δθ as the other input, and an output value of the second adder temporarily stored, and according to the timing of the clock signal f _CLK / 8, Δ8 · Δθ−4. The second register for outputting Δθ, the output value of the first register Σ8 · Δθ, and the output value of the second register ΣΔ8 · Δθ−4 · Δθ are used as the timing of the clock signal f _CLK / 8. And a first switching circuit which outputs the integrated value as a phase integrated value Σ4 ・ Δθ, and output values θθ and 2２Δθ of the ｛× 2 ⁿ ｝ circuit.
And the output value of the first switching circuit Σ4 · Δθ is used as an input value to calculate in parallel to obtain phase information Σ4 · Δθ-Δθ,
Σ4 · Δθ, Σ4 · Δθ + Δθ, Σ4 · Δθ + 2 · Δθ
, And phase information か ら 4 · Δθ-Δθ, Σ4 · Δθ, output from the four-phase parallel operation circuit,
A second switching circuit for sequentially switching θ4ΣΔθ + Δθ and Σ4θΔθ + 2 ・ Δθ in accordance with the timing of the clock signals f _CLK / 2 and f _CLK / 4 from the counter, and outputting as a phase integrated value ΣΔθ; A third register for outputting an output value of the switching circuit as a phase integrated value θ in accordance with the timing of the reference clock signal _fCLK .

[0007]

【Example】

[Configuration] FIG. 1 is a configuration diagram showing an embodiment of the present invention. In the figure, reference numeral 1 denotes a counter, which _{divides a} frequency of a reference clock signal f _CLK supplied from the outside to generate a clock signal f _CLK / 2,
f _CLK / 4 and f _CLK / 8 are output. 2 is a ｛× 2 ⁿ ｝ circuit, and a phase increase step value Δθ set from outside
Is multiplied by 2 ⁿ (n = 0, 1, 2, 3) to obtain phase information Δθ, 2
• Outputs Δθ, 4 · Δθ, and 8 · Δθ. The circuit comprises n
It can be easily configured by shift wiring to the upper bit side. An adder 3 receives the output value 8 · Δθ of the {× 2 ⁿ } circuit 2 as one input, performs addition with the other input, and outputs the result. 4
Is a register for temporarily storing the output value of the adder 3 and using the clock signal f _CLK / 8 as an integrated clock signal to output a phase integrated value Σ8 · Δθ according to the timing and to output the other of the adder 3 Return as input.
Reference numeral 5 denotes an adder, which takes the output value {8 · Δθ of the register 4 as one input (added value), and outputs the output value 4 of the {× 2 ⁿ } circuit 2.
Perform an addition operation using Δθ as the other input (subtraction value),
Output. Reference numeral 6 denotes a register which temporarily stores the output value of the adder 5 and outputs Σ8 ・ Δθ-4 ・ Δ according to the timing of the clock signal f _CLK / 8.

Reference numeral 7 denotes a switching circuit, and the clock signal f
In accordance with the timing of _CLK / 8, the output value Σ8 · Δθ-4 · Δθ the register 6 at _{f CLK / 8 = "0"} ,
When f _CLK / 8 = "1", the output value of register 4４8
.DELTA..theta. Is alternately switched and output as a phase integrated value .SIGMA.4.DELTA..theta .. Numeral 8 denotes a four-phase parallel operation circuit, which outputs the output value Δθ, 2 · Δθ of the｝ × 2 ⁿ ｝ circuit 2 and the output value Σ4
Addition operation is performed in parallel with Δθ as an input, and phase information Σ4 is calculated according to the timing of the clock signal f _CLK / 4.
・ Δθ-Δθ, θ4 ・ Δθ, Σ4 ・ Δθ + Δθ, Σ4 ・
Δθ + 2 · Δθ is output. The circuit can be easily constituted by an adder and a register. Reference numeral 9 denotes a switching circuit, which outputs the phase information {4 · 4} supplied from the four-phase parallel operation circuit 8 in accordance with the timing of the clock signals f _CLK / 2 and f _CLK / 4.
Δθ−Δθ, Σ4 · Δθ, Σ4 · Δθ + Δθ, Σ4 · Δ
θ + 2 · Δθ is sequentially switched and output as the phase integrated value ΣΔθ. Reference numeral 10 denotes a register, which is an output value of the switching circuit 9.
Δθ is temporarily stored, and the reference clock signal f _CLK
Is output as the phase integrated value θ in accordance with the timing.

FIG. 2 is a structural example showing the details of the four-phase parallel operation circuit 8 of FIG. In the figure, reference numerals 81, 82 and 83 denote adders, each of which takes the output value Σ4 · Δθ of the switching circuit 7 as one input. The adder 81 subtracts the output value Δθ of the ｛× 2 ⁿ ｝ circuit 2 as the other input, and obtains the phase information {4 · Δ
θ−Δθ is output. The adder 82 adds the output value Δθ of the ｛× 2 ⁿ ２ circuit 2 as the other input and adds the phase information {4 ·
Δθ + Δθ is output. The adder 83 is a {× 2 ⁿ } circuit 2
Is added as the other input to output phase information Σ4 · Δθ + 2 · Δθ. 84 is a register, the output value of the adder 81 Σ4 · Δθ−Δθ, the switching circuit 7
Σ4 · Δθ, output value of adder 82 Σ4 · Δθ +
Δθ and the output value 出力 4 · Δθ + 2 · Δθ of the adder 83 are temporarily stored and output in accordance with the timing of the clock signal f _CLK / 4.

[0010]

The operation of the configuration example shown in FIGS. 1 and 2 will be described with reference to FIGS. FIG. 3 shows the output value of the register 4 {8 · Δθ (broken line) and the output value of the register 6} in FIG.
8 is a waveform diagram showing an example of a time change of 8.Δθ-4 · Δθ (dotted line) and the output value Σ4 · Δθ (solid line) of the switching circuit 7. FIG. 4 shows the output value of the switching circuit 7 in FIG.
FIG. 9 is a waveform diagram showing an example of a change over time of a (dashed line) and an output value 及 び Δθ (solid line) of the switching circuit 9;

First, the output waveforms of the switching circuit 7 with respect to the inputs of the adder 3 and the adder 5 will be described with reference to FIG. Now, at time T ₀ , the output value of register 4 Σ
8. Set Δθ = 0. Since the adder 3 and the register 4 form an integrating circuit, the clock signal _fCLK / 8
The integration of the input value 8 · Δθ of the adder 3 is continued for each cycle (8 / f _CLK ), and the output value of the register 4 rises stepwise in steps of 8 · Δθ as shown by the broken line in FIG. Next, reaches the time T _1, when the value of Σ8 · Δθ reaches more than 2 ^M, the value of Σ8 · Δθ by integrating action of modulo2 ^M, 2
It falls to a value obtained by subtracting ^M , rises again in steps of 8 · Δθ, and repeats the same operation as after time T ₀ . From the above operation, it is understood that the output value Σ8 · Δθ of the register 4 exhibits a sawtooth waveform value.

Here, the phase step value is defined as Δφ (Δφ = 8
.DELTA..theta.),

[0013]

[Outside 1] Is given by the following equation.

[0014]

(Equation 2)

The output value of the register 6 Σ8 · Δθ-4
The value of Δθ is the output value of the register 4 by the adder 5 Σ8 · Δ
Since the value is obtained by subtracting 4 · Δθ from θ, it is apparent that the waveform becomes a sawtooth waveform as shown by the dashed line in FIG. Therefore, according to the timing of the clock signal f _CLK / 8, the switching circuit 7 outputs the output value Σ8 · Δθ−4 · Δθ of the register 6 when f _CLK / 8 = “0” and f _CLK / 8 =
"1" the output to switch alternately output value Σ8 · Δθ the register 4 when the output waveform of the switching circuit 7 as shown in solid line in FIG. 4, the phase increment step value 4 · [Delta] [theta], integration clock signal f _CLK An output waveform is obtained by the integration operation of / 4. Waveform, along with {× 2 ^n} Output value 2 · [Delta] [theta] and [Delta] [theta] of the circuit 2, the input of the next stage four-phase parallel operation circuit 8.

Next, the output of the switching circuit 9 with respect to the input of the four-phase parallel operation circuit 8 will be described with reference to FIG. 4
The phase-parallel operation circuit 8 outputs the output values {4 · Δθ, ｛× 2 ⁿ } of the switching circuit 7 indicated by the broken lines in FIG.
The · [Delta] [theta], the adder 81, the adder 82 adds operations in parallel by the adder 83, the result by the register 84 in accordance with the timing of the clock signal f _CLK / 4 Σ4 · Δθ-
Δθ, Σ4 · Δθ, Σ4 · Δθ + Δθ, Σ4 · Δθ + 2
-Output as Δθ. The output value is the clock signal f
_The signals are sequentially switched and output by the switching circuit 9 in accordance with the timings of _CLK / 2 and _fCLK / 4, have a sawtooth waveform as shown by the solid line in FIG. 4, are temporarily stored in the register 10, and are integrated in accordance with the timing of the reference clock signal _fCLK. Information θ
Is output to the outside. Here, equations (1) and (2)
In the above, if N = M, the following equation is established.

[0017]

(Equation 3)

[0018] than this, the output value θ of the register 10, a waveform equivalent obtained by integrating the phase increment step value Δθ in the reference clock signal f _CLK, i.e. the same as the output value of the numerical control oscillation circuit of the conventional method shown in FIG. 5 It turns out that it is a waveform.
Equation (2) can be expressed as the following equation.

[0019]

(Equation 4)

As described above, the numerically controlled oscillation circuit according to the present invention integrates the phase step information of Δφ (= Σ8 · Δθ) in the integrating operation, so that the integrated clock signal is reduced to 1/8 the speed of the conventional system. It is possible to do. That is, this is equivalent to accelerating the integration operation eight times.

[0021]

As described in detail above, in the configuration of the numerically controlled oscillation circuit of the present invention, since the speed of the integrated clock signal in the integrating circuit operates with a clock signal whose speed is 1/8 that of the conventional system, the addition is performed. The carry operation time of the device has a margin, and the speed of the integration clock can be increased. Further, the word length of the integrating circuit can be increased, and the accuracy of the integrated output value can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration example diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a four-phase parallel operation circuit of FIG. 1;

FIG. 3 is a time chart of the integration operation and the output value of the switching circuit 7 of FIG. 1;

FIG. 4 is a time chart of an output value of the switching circuit 9 of FIG. 1;

FIG. 5 is a configuration example diagram of a conventional numerically controlled oscillation circuit.

[Explanation of symbols]

Reference Signs List 1 counter 2 {× 2 ⁿ } circuit 3 adder 4 register 5 adder 6 register 7 switching circuit 8 four-phase parallel operation circuit 9 switching circuit 10 register 81, 82, 83 adder 84 register 101 adder 102 register

Claims (1)

(57) [Claims] An externally supplied reference clock signal f
A counter that divides _CLK and outputs f _CLK / 2, f _CLK / 4, and f _CLK / 8, and a phase increase step value Δθ set from the outside by 2 ⁿ times (n = 0, 1, 2, 3 ) To obtain phase information Δθ, 2 · Δθ,
A ｛× 2 ^{n n} circuit that outputs 4 ・ Δθ and 8 ・ Δθ, a first adder that takes the output value of 8 ｛Δn of the ｛× 2 ⁿ ｝ circuit as one input and adds the other input The output value of the first adder is temporarily stored, and the phase integrated value Σ is calculated according to the timing of the clock signal f _CLK / 8.
A first register that outputs as 8 · Δθ and feeds back as the other input of the first adder; and an output value of 4 · Δθ of the ｛× 2 ⁿ ｝ circuit as one input and outputs the first register. A second adder for performing a subtraction process using the output value Σ8 · Δθ as the other input; temporarily storing the output value of the second adder; Σ8 · Δθ in accordance with the timing of the clock signal f _CLK / 8 −
A second register for outputting 4 · Δθ, an output value of the first register Σ8 · Δθ, and an output value of the second register ΣΔ8 · Δθ−4 · Δθ, the clock signal f _CLK / 8 A first switching circuit that switches in accordance with the timing of and outputs as a phase integrated value Σ4 · Δθ; output values Δθ and 2 · Δθ of the ｛× 2 ⁿ ｝ circuit; and an output value Σ4 · Δθ of the first switching circuit. Is calculated in parallel with the input values, and the phase information Σ4 · Δθ−Δθ, Σ4 · Δ
a four-phase parallel operation circuit that outputs θ, Σ4 · Δθ + Δθ, θ4 · Δθ + 2 · Δθ, and phase information Σ4 · Δθ output from the four-phase parallel operation circuit
−Δθ, Σ4 · Δθ, Σ4 · Δθ + Δθ, Σ4 · Δθ +
2. · Δθ is calculated using the clock signal f _CLK /
2, a second switching circuit for sequentially switching in accordance with the timing of f _CLK / 4 and outputting as a phase integrated value ΣΔθ, and an output value of the second switching circuit,
_A third register that outputs a phase integrated value θ according to the timing of _CLK .