JPS6093855A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To eliminate the need for a transmission line for a data read command by sampling a received data, loading it to a buffer register and comparing the content of the buffer register with the content of the received data. CONSTITUTION:When a pulse of logical ''1'' is incoming to a terminal L of a data register 8, a signal of a parallel input terminal is loaded to the buffer register 7. The content of the received data and the content of the buffer register 7 are compared by a comparator 6. When the content of the received data is coincident with the content of the buffer register 7, a data coincidence detecting flag 12 is transmitted from the comparator circuit 6 and the flag 12 is transmitted to a transmission side 1 as a data read end signal 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data transmission device that transmits data in parallel bits using a plurality of signal lines.

[Prior art]

A conventional device of this type is shown in FIG. In the figure, (1) is the transmitting side of the transmission device, (2) is the receiving side of the transmission device, (3a), (3b), (3c), ...
3m) and (3n) are data signal lines, (4) is a data read command (data load command) issued by the transmitting side (1) to the receiving side 121, and (51 is a signal line from the receiving side (2) to the transmitting side (1).
) data read completion signal (data load completion signal)
It is.

Figure 2 is an operation time diagram showing the signals of each part in Figure 1, and Figure 2 (a) is the data signal line (3a) - (3b),
(3J...(3n) In the above data, α, β, r...
It shall change as follows. Figure 2(b), (C
) respectively indicate a data reading command (41) and a data reading completion signal (5).

During the transition period when the data changes from α to β, there is a slight difference in the timing of data change on each data signal line (3a), (3b)..., so the bi-soto logic on all signal lines is The data read command (41) is issued after waiting until the data definitely represents new data.
A predetermined delay time T from the point in time when the transmission data of l changes from α to β. After that, the data read command (4) is set to logic "1". In the reception 111u 121, the command (41 is the logic "1"
”, the transmission data β is read, and after the reading is completed, the signal (5) is set to logic “1” and sent.

The sending side (1) sees that the signal (5) has become logic "1" and sets the command (4) to logic "0", and the receiving side confirms that the command (41) has become logic "0". and the signal (51 is logic ``
0".

This completes the transmission of one piece of data (data β in the above case).

Since the conventional data transmission device is configured as described above, it is necessary to provide a signal line for transmitting the data read command (41), and the data read command (4) is transmitted for a predetermined period of time from the point of switching of the data signal. It must be sent with a delay of TD, confirmation of the logic change of the read command (4) on the receiving side (2), and completion signal (51) on the transmitting side (1).
Since transmission/reception procedures are required even after the read command (41) is sent, such as confirmation of logical changes in the data, there is a drawback that a large amount of time and money is expended in transmitting one data.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above.In this invention, a comparator and a buffer register are provided on the receiving side, and all received data is sampled at a predetermined clock and loaded into the buffer register. Then, a comparator compares whether the contents of the buffer register and the received data match, and if they match, each data signal line (3a), (3b), (3o), ... (3n)
) is assumed to have been completed and this data is loaded into the data register, so the read command (4) is not required, and therefore the transmission line for the read command can be omitted. And the time required to transfer one data, that is, one data signal line (3
It was possible to shorten the time it takes to send signals to a), (3b)-(3c), . . . (3n).

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figures indicate the same or corresponding parts, and the difference from FIG. 1 is that FIG. 3 lacks a signal line for transmitting a data reading command. FIG. 4 is a block diagram showing the internal configuration of the receiving side (21) in FIG.
b), (3c), ... (3n) eAll are represented by the code (31), (5) indicates the same signal as the same code in Fig. 3, (61 is the comparator, (7) is the buffer register,
(81 is a data register, and the letters in these registers indicate load signal input terminals. In other words, when a logic "1" pulse arrives at the terminal, the signals at the parallel input terminals of these registers are loaded into these registers. (9
) is the clock generator, +101.

1I11 are gate circuits, 0 flag is a data coincidence detection flag, and flag 0 is a data read completion signal (51).

FIG. 5 is an operation time chart showing the signal progress in the circuit of FIG. 4.

r, ..., one input of the comparator (61), the parallel input terminal of the buffer register (7), and the data register (
81 parallel input terminals, respectively.

FIG. 5(b) shows the data matching detection flag (6).

Next, the operation of the apparatus of this invention will be explained.

For example, when the transmitted data is stable at α in FIG. 5 (al), both inputs of the comparator (6) match,
The data match detection flag 10 is set to logic "1",
The clock of the clock generator (9) is the gate circuit ttnv.
The data α on the data signal line (3) is then loaded into the data register (8), but the data already existing in the data register +81 is also the same data. Since α, the contents of the data register (8) do not change.

Also, while the logic of the six flags is "1", the gate circuit stops passing the clock (i = 1514).Next, when the transmitted data changes from α to β, both inputs of the comparator (6) are inconsistent, and the logic around the flag 0 becomes "0", so the clock that has passed through the gate circuit +101'e is loaded into the data signal line (all signal buffer registers 17 on 31) at that time.Transmission signal switching In the transient state of time, both inputs of the comparator +61 become inconsistent at the next clock point, and the clock passed to the gate circuit fl (1=) transfers the signal on the data signal line (31) at that point to the buffer register ( 7). When this process is repeated and the signal on the data signal line (3) reaches β, both comparators (6) match and the logic of flag a becomes "1". Then, all the clocks of the gate circuit 11v pass through, and the signal on the data signal line +31 at that time, that is, the signal β, is loaded into the take register (8).

Data match detection flag (data read completion signal (51)
is sent to the sending side (1) as 11111.
txt, the receiving side (2) knows that reading of data β has been completed and may change to data γ.

〔Effect of the invention〕

As described above, according to the present invention, the receiving side (2) is provided with the buffer register (7) and the comparator (6), and the data loaded into the buffer register (71) at the previous clock and the data received at the next clock are When the received data matches the data, the received data is considered stable and is loaded into the data memory. This eliminates the need for data read commands (41 transmission lines), and allows It was possible to shorten the time required for transmission.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional device, FIG. 2 is an operation time diagram showing signals of each part in FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. FIG. 5 is a block diagram showing the internal configuration of the receiving side shown in FIG. 5, and FIG. 5 is an operation time diagram showing signals of each part in FIG. (1)...Transmission device sending side, (21...Transmission device receiving side, (3J...data signal line, (51...data read completion signal, 161...1+1 device, (7 )...
Buffer register, (81... data register, 02
...Data match detection flag. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 4 Figure 5

Claims (1)

[Claims] In a data transmission device that transmits data in parallel bits through a plurality of signal lines, the data transmission device is provided on the data receiving side, and the signals on the plurality of signal lines are transferred to one input of a comparator and a buffer. means for connecting the contents of the buffer register as an input to the parallel input terminal of the register and to the parallel input terminal of the data register, respectively; means for connecting the contents of the buffer register as the other input of the comparator; When the bit patterns match, a data match detection flag of logic “1” is output,
When the bit patterns of both inputs do not match, a logic "0" signal is output, and when the logic "0" signal is output, the signal from the parallel input terminal of the buffer register is loaded into the buffer register. , means for loading the signal of the parallel input terminal of the data register into the data register when the data match detection flag is being output; and transmitting the data match detection flag from the receiving side to the sending side as a data read completion signal. A data transmission device characterized by comprising: means.