JPH01236823A - Analog/digital signal converter - Google Patents

Abstract

PURPOSE:To eliminate the action of a register due to hazard without changing the constitution of a flip flop by obtaining an output signal simultaneously when the output signal of a comparator is set into a successive approximate register. CONSTITUTION:When a register starting signal C.CMD is inputted from an input terminal 31, a successive approximate register 3 is synchronized to a clock EX.CK inputted from an input terminal 32, operated, the data set to parallel outputs B1-BN with the successive approximate register 3 are outputted and sent to a digital analog signal converter 1. Simultaneously, a signal outputted from a comparator 2 is shaped and outputted from an output terminal 36. At this time, an EOC signal 'H' is set from an output signal 34 and the EX.CK and an in-phase clock are outputted from an output terminal 35 of an output clock signal CK.Out during the action only. When the action of the successive approximate register 3 is interrupted at an (i)-th bit, a register output terminal Bi and the SC input terminal of an input terminal 33 are shorted. Thus, the generation of the hazard can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a successive approximation type analog-to-digital signal converter.

BACKGROUND ART In a conventional analog-to-digital signal converter, the successive approximation register consists of a flip-flop that sets data using a clock that is in phase with the external clock, and a flip-flop that sets data using an anti-phase clock as shown in the block diagram of Figure 3.・The flop and all pairs are composed of n-)-1 pairs.

In addition, in FIG. 3, 1 is a digital-to-analog signal converter, 2 is a comparator, 3 is a successive approximation register, 30
1.302 is a D flip-flop circuit, 311-31
5 is a gate circuit, 316 is a flip-flop circuit network,
11 is an output terminal of a signal converted from a digital to analog signal, 21.23 is an input terminal of comparator 2, 22 is an output terminal of comparator 2, 31 is an input terminal of a register start signal (C, CMD), and 32 is an input terminal. Input terminal for clock signal (EX, GK), 33 is input terminal for register reset signal (SC), 34 is output terminal for register operation confirmation signal (EOC), 36 is for register output clock signal (OK, 0ut) Output terminals 36 are data input terminals, 37 are data output terminals, and B1 to BN are register/parallel output signal terminals as input terminals of the digital/analog signal converter 1. FIG. 4 shows a timing chart. First, when the drive signals C and CMD to the register go to IIL" level, the register starts to move in synchronization with the clock, and then becomes 1 (H" level.
The flip-flop output of the final stage of the flop circuit network 316 and the SC signal (usually 11 HI
+ level) in a gate circuit 311, and then the AND of the output signal and external clock signals XX and GK is used as a drive clock for the register and as an output clock to the outside.

Problems to be Solved by the Invention In such a conventional successive approximation register circuit, as shown in the timing chart of FIG. becomes IT)I”, T
ll," level is output or input. Therefore, a buzzer occurs when a register operation ends or when a reset is applied in the middle of an operation, and this buzzard is used to drive the register. Therefore, this buzz occurs in the final external output clock, making it difficult to communicate with external peripheral circuits using this clock.

The present invention solves these problems and aims to eliminate register operations caused by buzzards without changing the configuration of flip-flops.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides an N-stage flip-flop circuit network that operates in synchronization with a human-powered clock from the outside when a start signal is input, and the circuit network. It is connected to the output terminal of the final stage flip 70 tube.
RS connected to the input terminal for resetting all flip-flops when the R8-7 lip-flop circuit and the first stage 7 lip-flops of the circuit network operate.
- a successive approximation register having a clip/70 tube circuit, a digital-to-analog signal converter that receives the N-bit digital signal output of this successive approximation register circuit, and a reference potential between the output of this digital-to-analog signal converter and a reference potential. and a comparator for comparing, and at the same time setting the output signal of the comparator in the successive approximation register,
This is the output signal. That is, by using a clock with the opposite phase of the external input clock and passing the SC signal to the R8-flip-flop circuit or the final stage flip-flop output signal of the 7-lip-flop circuit network in the register, the buzzard will not occur. It was made in a similar manner.

Operation This configuration allows the SC signal, the final flip-flop output signal of the flip-flop network in the register, to be
By not generating a buzzer in the clock output from the register through the 3-flip-flop, digital signal processing between the analog-to-digital signal converter and the peripheral circuits can be performed accurately and easily.

Embodiment FIG. 1 shows an analog system using the successive approximation register of the present invention.
FIG. 2 is a block diagram showing one embodiment of a digital signal converter. In FIG. 1, 1 is a digital-to-analog signal converter, and output terminals 11. It has input terminals 81 to BN. 2 is a comparator, and input terminal 21. Output terminal 2
2. It has an input terminal 23 for reference potential, and the input terminal 23 is grounded. Further, the output signal is obtained from the output terminal 22. 3 is a successive approximation register, and when register start signals C and CMD are input from an input terminal 31, the successive approximation register 3 operates in synchronization with clocks IEX and OK input from an input terminal 32. When the successive approximation register 3 operates, the data set in the successive approximation register 3 is outputted to the parallel outputs B1 to BN and sent to the digital/analog signal converter 1.

At the same time, the signal output from the comparator 2 is shaped and output from the output terminal 36. At this time, the output signal 34 f)E
The OC signal "'H" is set, and the output clock signal GK,
Out (7) Output terminal a ts Yot) EX, OK
A clock with the same phase as that is output only during operation. Also, when interrupting the operation of successive approximation register 3 at the i-th bit,
The register output terminal Bi and the SC input terminal of the input terminal 33 are short-circuited.

FIG. 2 shows a timing chart of the SC input signal or the output signal of the final flip-flop and the clocks EX and GK according to the present invention. The flop circuit network 316 is set and the RS successive approximation register 3 operates.At this time, the EOC signal is set to 11H11.When the successive approximation register 3 operates, the output signal is
X, GK "L" is set in synchronization with "H". At this time, since the Bi times signal SC signal line is short-circuited, C
, CMD is +1 L 11 to "H"K'i tte, i-th EX, OK "I ("SC signal becomes °゛L'' at C1. Next, gate circuit 306゜307.
When the clock of φ becomes "H" in the R3-flip-flop circuit composed of AND of 309, the input terminal of the gate circuit 311 becomes "L". Also, the SC signal remains at "H". When , the flip 70-tube circuit network 316
operate in order, and the output of the final stage flip-flop is EX
, when GK is "H", it is set from 11 H+1 to +1 L It. Similarly to the above, φ,
When becomes 11 H11, the input terminal of the gate circuit 311 is set from 'H' to 11 L It. Therefore,
The register continues to operate without any buzz. In addition, 308 is a gate circuit, gate circuit 306゜3
07.309 - connected to the input stage of the flip-flop circuit.

Effects of the Invention As described above, according to the present invention, the generation of buzzards can be eliminated by adding AND circuits to peripheral input/output lines without changing the configuration of the flip-flop circuit network in the register. data processing between the analog/digital signal converter and peripheral circuits.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a successive approximation type analog-to-digital signal converter in an embodiment of the present invention, Figure 2 is a timing chart of a successive approximation register circuit, and Figure 3 is a conventional successive approximation type analog-to-digital signal converter. Block diagram of the device,
FIG. 4 is a timing chart of a conventional successive approximation register circuit. 1...Digital/analog signal converter, 2...
...Comparator, 3...Successive approximation)
Star, 301° 302...D flip-flop circuit, 304-316...Gate circuit, 31
6. River...Flip-flop circuit network ○ Name of agent Patent attorney Toshio Nakao and 1 other person 1st
Figure 2 Figure 3

Claims (1)

[Claims] An N-stage flip-flop circuit network that operates in synchronization with an externally input clock when a start signal is input, and an RS-flip-flop circuit connected to the output terminal of the final stage flip-flop in the circuit network. and a successive approximation register having an RS-flip-flop circuit connected to an input terminal for resetting all the flip-flops when the i-th flip-flop of the circuit network operates; It is equipped with a digital-to-analog signal converter that inputs an N-bit digital signal output, and a comparator for comparing the output of this digital-to-analog signal converter with a reference potential, and the output signal of the comparator is stored in the successive approximation register. At the same time, set the output signal to an analog-to-digital signal converter.