JPH0425247A - Clock thinning circuit - Google Patents

Abstract

PURPOSE:To prevent production of undesired pulse in the case of thinning processing by processing a mask signal and synchronizing the mask signal at the rising of the clock. CONSTITUTION:A thinned number is loaded to a down-counter, in which the number is counted down as a count 21 and a carry is outputted from the down- counter 12. Since the carry outputted from the down-counter 12 includes undesired high frequency pulses being so-called gabbage from the standpoint of bit pattern, a flip-flop 9 uses to latch the carry signal once and the output of the flip-flop 9 is used to a clear flip-flops 1, 2. In this case, the mask start position is delayed by one clock thereby matching the start and end of thinning of the clock and the start and end position of the mask with the clock rising. Thus, production of undesired pulse is prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a clock diversion circuit, and in particular to a clock diversion circuit for controlling the phase of a local code generator clock of a code generator used in a coded digital communication system. Regarding the blind circuit.

[Conventional technology]

In coded communication systems, it is necessary to match the phases of the code of the received signal and the code of the local code generator during demodulation. For this reason, it is necessary to first set the code phase of the local code generator in an arbitrary state and then search sequentially until a synchronized phase is secured. At this time, one possible method for shifting the code phase of one local code is to vary the control clock of the local code generator.

Conventionally, in order to realize this control clock variation, it has been considered to count the number of phase shifts with a town counter 25 and control the clock variation with a selector 27, as shown in FIG.

[Problem to be solved by the invention]

Due to the characteristic of the counter that the carry of the counter is output at °゛O°', the conventional clock diversion circuit described above tends to dilute by one more than the specified diversion number, and also masks the clock. Since a selector is used for this purpose, there is a drawback that unnecessary pulses may be generated if handled carelessly.

[Means to solve the problem]

The clock adjustment circuit of the present invention includes a register that holds the adjustment number, a down counter that counts down the adjustment number, a flip-flop that synchronizes the mask control signal with the clock so as not to generate unnecessary pulses, and a clock that masks the clock. It is configured with a logic gate for.

Further, the clock adjustment circuit of the present invention has a configuration in which the mask start position is delayed by one clock.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1(A) is a circuit diagram of an embodiment of the present invention. In FIG. 1 (A>), 1 is a flip-flop as a register that holds the number of J subtractions, 12 is a down counter that counts down the number of multiplications, 2 is a flip-flop as a register that instructs the start of multiplication, and 9 is a down counter 12 3, 4, 5.10 are flip-flops for timing correction to suppress the number of deflections to a specified number, B, 6, 7.11 and Reference numerals 13 denote an OR gate and a NAND gate, each serving as a logic gate for generating a clock mask signal.

They are an OR gate, an AND gate, and an OR gate.

Next, the operation of this embodiment will be explained using the time chart of FIG. 1(B).

Now, set the n-bit bits of winding data to the register that holds the winding number of flip-flop 1.

Fri-n-fu is a register that instructs the start of winding.

Clock and 4. as a write signal to flop 2. tll
When the E-synchronization logic “H” is set, (
The output 15 shown in c) is obtained from the flip-flop circuits 3, 4 and 5 (the second one and the first one, respectively).
Output 16 shown in (d), (e), and (f) of Figure (B).
17 and 18 are obtained. The output 18 is input to the load terminal (L) of the down counter 12, and the clock terminal of the down counter 12 is supplied with the output 20 of the OR gate 7 shown in FIG. 2(h). The OR gate 7 is shown in Figure 1 (
The output 19 of the NAN gate 6 shown in (g) of B) and the clock shown in (a) of FIG. 1(B) are input to obtain an output 20.

The down counter 12 is loaded with the number of blinds up to the point ■ in FIG. 1(B), and after the point ■, the down counter 12 counts down as shown in the count value 21 in (i) of FIG. 1(B). , when the count value reaches "0°', a carry is output from the down counter 12. Since the carry output from the down counter 12 includes thin unnecessary pulses called garbage due to its structure, these unnecessary pulses are To remove the clock, the carry signal is latched once in the flip-flop 9 to obtain the original carry, and the flip-flop 1.2 is cleared by its output 22 shown in FIG. If the mask signal is set from the count start point to the point where it is cleared, the mask signal will have a length of clocks (n+1> minutes), and the clock will be repeated one more time than the set number. This problem is solved in this embodiment. However, this problem is solved by delaying the mask start position by one clock.6 Also, the clock mismatching start and end prevents the generation of unnecessary pulses by synchronizing the mask start and end positions with the rising edge of the clock. The thing is.

As shown in the output 23 of (k) and the output 24 of (JL") in FIG. output 15 of flip-flop 2 as another input of the AND gate.
This is ensured by supplying an output 24 whose rise is synchronized with that of the output 23, and logically ORing this and the clock with the OR gate 13 to obtain the parallel clock shown in (m> in FIG. 1B). Ru.

〔Effect of the invention〕

As explained above, the present invention allows the number of clocks set in the register to be correctly set by modifying the mask signal, and by synchronizing the mask signal with the rising edge of the clock, the number of clocks set in the register can be set correctly. This has the effect of not generating unnecessary pulses.

[Brief explanation of the drawing]

FIG. 1(A) is a circuit diagram of one embodiment of the present invention, and FIG. 1(B) is a circuit diagram of an embodiment of the present invention.
) is a timing chart of the main signals in FIG. 1(A), and FIG. 2 is a circuit diagram of a conventional clock adjustment circuit. 1.2, 3, 4.5, 9.10...Flip-flop, 6...NAND gate, 7.8.13...OR gate, 11...AND gate, 12.25... downtown data, 14...NOT gate, 26...state holding block, 27...selector.

Claims (1)

[Claims] 1. A register that holds the number of steps, a down counter that counts down the number of steps, a flip-flop that synchronizes the mask control signal with the clock so as not to generate unnecessary pulses, and masks the clock. 1. A clock diversion circuit comprising a logic gate for. 2. The clock adjustment circuit according to claim 1, wherein the mask start position is delayed by one clock.