JPH06318932A - Clock change circuit - Google Patents

Abstract

PURPOSE:To prevent the latch error of data caused by the clock of a following step by replacing input data held by a first clock with data held by the inverted clock of a second clock when the latch error is generated. CONSTITUTION:The data latched by a first clock CLK 1 at a flip-flop(FF) 1 are latched by a second clock CLK 2 at an FF 3. Further, these data are latched by the inverse of the CLK 2 at an FF 7. When the latch error is generated at the FF 3 and outputs are made instable at FF 3 and 4, the output of a comparator 11 is turned to H. The output of the comparator 11 are latched by FF 12 and 13, and these outputs are ANDed by an AND gate 14. The output of the AND gate 14 is latched by an FF 15, and this is defined as the select signal of a selector 16. When the select signal is L, the selector 16 selects the output of a delay means 100 but when it is H, the output of a delay circuit 200 is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock transfer circuit, and more particularly, to the transfer of information between non-synchronized circuits or devices, from the operation clock of the device that is the source of the information to the operation of the device that is the destination of the information. The present invention relates to a clock transfer circuit when synchronizing information with a clock.

[0002]

2. Description of the Related Art FIG. 19 is a block diagram of a conventional clock transfer circuit using a flip-flop. In the figure, reference numeral 89 is a first flip-flop 1 for holding input data by a first clock, and 90 is a second flip-flop for holding an output of the first flip-flop by a second clock.

The operation of a conventional clock transfer circuit is shown in FIG.
Will be explained. Input data is latched by the first clock in the first flip-flop. Then, it is latched by the second clock in the second flip-flop (FIG. 20B). Since the first clock and the second clock are asynchronous with each other, as shown in FIG.
If the second flip-flop tries to latch with the second clock during the period in which the output data of the second flip-flop changes, a latch miss occurs because the setup time or the hold time is insufficient, and the output of the second flip-flop is undefined. However, there is a problem in that (FIG. 20 (d)).

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and prevents a data latch miss due to a clock in the subsequent stage.
The purpose is to obtain a clock transfer circuit with a simple circuit configuration.

[0005]

According to a first aspect of the present invention, there is provided a clock transfer circuit which comprises a first holding section for holding and outputting input data by a first clock, and a first holding section by a second clock. A second holding unit for holding and outputting the output of the unit, a third holding unit for holding and outputting the output of the second holding unit by a second clock, and a third holding unit by an inverted clock of the second clock. A fourth holding unit that holds and outputs the output of the first holding unit; a comparing unit that compares the output of the second holding unit and the output of the third holding unit; and a second output of the comparing unit.
A fifth holding unit that holds and outputs the output of the fifth holding unit by the second clock, a sixth holding unit that holds and outputs the output of the fifth holding unit, and an output of the fifth holding unit and the fifth holding unit. 6
AND gate for taking the logical product of the outputs of the holding units of
A seventh holding unit that holds and outputs the output of the D gate by the second clock, a first delay unit that time-adjusts the third holding unit and the seventh holding unit, and the fourth holding unit. Second delay means for adjusting the time of the holding part and the seventh holding part;
A selection unit that selects and outputs the output of the third holding unit and the output of the fourth holding unit according to the output of the holding unit of And a holding part.

A clock transfer circuit according to a second aspect of the present invention holds a first holding unit for holding and outputting input data by a first clock and a second holding unit for holding an output of the first holding unit. A second holding unit that outputs, a third holding unit that holds and outputs the output of the second holding unit by a second clock, and an output of the first holding unit by an inverted clock of the second clock Of the second holding unit, a fourth holding unit that holds and outputs the second holding unit, a comparing unit that compares the output of the second holding unit and the output of the third holding unit, and the output of the comparing unit. An output unit and a selection unit that selects and outputs the output of the fourth holding unit, and a fifth holding unit that holds and outputs the output of the selection unit according to the second clock.

According to a third aspect of the present invention, there is provided a clock transfer circuit which holds a first holding unit for holding and outputting input data by a first clock and a second holding unit for holding an output of the first holding unit. A second holding unit for outputting, a third holding unit for holding and outputting the output of the second holding unit by a second clock, and a third holding unit for holding the output of the third holding unit by a second clock A fourth holding unit for outputting, a fifth holding unit for holding and outputting the output of the fourth holding unit by the second clock, an output of the second holding unit and a third holding unit. A comparing unit that compares outputs, a sixth holding unit that holds and outputs the output of the comparing unit by a second clock, and a seventh holding unit that holds and outputs the output of the sixth holding unit by the second clock. Holding unit, and the logic of the output of the sixth holding unit and the output of the seventh holding unit An AND gate for taking the eighth to the output of the AND gate is held by the second clock output
Holding unit, a selecting unit for selecting and outputting the output of the fourth holding unit and the output of the fifth holding unit by the output of the eighth holding unit, and the output of the selecting unit for the second clock. And a ninth holding unit that holds and outputs the data.

A clock transfer circuit according to a fourth aspect of the present invention holds a first holding unit that holds and outputs input data by a first clock, and holds an output of the first holding unit by a second clock. A second holding unit for outputting, a third holding unit for holding and outputting the output of the second holding unit by a second clock, and a third holding unit for holding the output of the third holding unit by a second clock A fourth holding unit for outputting, a comparison unit for comparing the output of the third holding unit and the output of the fourth holding unit, and the output of the second holding unit and the output of the second holding unit by the output of the comparing unit. The third holding unit includes a selecting unit that selects and outputs the output of the third holding unit, and a fifth holding unit that holds and outputs the output of the selecting unit according to the second clock.

A clock transfer circuit according to a fifth aspect of the present invention holds a first holding unit that holds and outputs input data by a first clock, and holds an output of the first holding unit by a second clock. A second holding unit for outputting, a third holding unit for holding and outputting the output of the second holding unit by a second clock, and a third holding unit for holding the output of the third holding unit by a second clock A fourth holding unit for outputting, a comparing unit for comparing the output of the third holding unit and the output of the fourth holding unit, and a frequency dividing unit for dividing the output of the comparing unit by half. An AND of the output of the frequency divider and the second clock
A D gate, a selection unit that selects and outputs the output of the third holding unit and the output of the fourth holding unit by the output of the AND gate, and the output of the selection unit is held and output by the second clock. It has a fifth holding portion that does.

A clock transfer circuit according to a sixth aspect of the present invention holds a first holding unit that holds and outputs input data by a first clock, and holds an output of the first holding unit by a second clock. A second holding unit for outputting, a third holding unit for holding and outputting the output of the second holding unit by a second clock, and a third holding unit for holding the output of the third holding unit by a second clock A fourth holding unit for outputting, a first comparing unit for comparing the output of the second holding unit and the output of the third holding unit, the output of the third holding unit, and the fourth holding unit A second comparing section for comparing the outputs of the sections, and an AND gate for taking the logical product of the output of the first comparing section and the output of the second comparing section,
A fifth holding unit that holds and outputs the output of the AND gate by the second clock, and an output of the fifth holding unit,
And a selection unit that selects and outputs the output of the third holding unit and the output of the fourth holding unit, and a sixth holding unit that holds and outputs the output of the selection unit according to a second clock. is there.

In the clock transfer circuit according to the seventh aspect of the present invention, the input data is held in the first holding unit by the first clock. Then, the logical product of the output of the second holding unit that holds the first clock with the second clock and the output of the third holding unit that holds the first clock with the inverted clock of the second clock is obtained. This is used as a clock of the fourth holding unit to hold and output the output of the first holding unit.

According to another aspect of the clock transfer circuit of the present invention, there is provided a first holding section for holding and outputting the input data by the first clock, a delay section for delaying the second clock by a fixed time, and A second holding unit that holds and outputs the output of the delay unit according to a second clock; and a third holding unit that holds and outputs the output of the first holding unit by the output of the second holding unit, A fourth holding unit that holds and outputs the output of the third holding unit by the output of the second holding unit, and holds and outputs the output of the fourth holding unit by the output of the second holding unit A fifth holding unit for holding, a sixth holding unit for holding and outputting the first clock with the second clock, and a seventh holding unit for holding and outputting the output of the sixth holding unit with the second clock. The exclusive OR of the holding unit and the output of the sixth holding unit and the output of the seventh holding unit is calculated. An EXOR gate, an eighth holding unit that holds and outputs the output of the EXOR gate by a second clock, and a ninth holding unit that holds and outputs the output of the eighth holding unit by a second clock. , An AND gate that takes the logical product of the output of the eighth holding unit and the output of the ninth holding unit, and a tenth holding that holds and outputs the output of the AND gate by the inverted clock of the second clock Part and the first
The AND gate that takes the logical product of the output of the holding unit of 0 and the second clock, and the output of the AND gate
And an twelfth holding unit that holds and outputs the output of the eleventh holding unit according to the second clock.

[0013]

According to the first aspect of the invention, the input data held by the first clock is held by the second clock, and is held once again by the second clock.
The outputs of the two holding units are compared by the comparing unit, and if they do not match for two clocks, it is determined that a latch miss has occurred. Configure the control signal of the selector from the output of the comparison unit,
When a latch miss occurs, the input data held by the first clock is replaced with the data held by the inverted clock of the second clock.

According to the second aspect of the invention, the input data held by the first clock is held by the second clock, and is held again by the second clock. The outputs of the two holding units are compared by the comparing unit, and if they do not match, it is determined that a latch miss has occurred. The output of the comparator is used as the control signal of the selector, and when a latch miss occurs, the input data held by the first clock is replaced with the data held by the inverted clock of the second clock.

According to the third aspect of the invention, the input data held in the first holding section by the first clock is held in the second holding section by the second clock. Further, the output of the second holding unit is held by the third holding unit by the second clock. In addition, the second clock
The output of the holding unit is held by the fourth holding unit. Further, the output of the fourth holding unit is held by the fifth holding unit by the second clock. The outputs of the second and third holding units are compared by the comparing unit. If they do not match for two clocks, it means that a latch miss has occurred. The control signal of the selector is constructed from the output of the comparison unit, and when a latch error occurs, the output of the holding unit of the fourth output is selected instead of the output of the fifth holding unit.

According to another aspect of the invention, the input data held in the first holding unit by the first clock is held in the second holding unit by the second clock. Further, the output of the second holding unit is held by the third holding unit by the second clock. In addition, the second clock
The output of the holding unit is held by the fourth holding unit. The outputs of the third and fourth holding units are compared by the comparison unit, and if they do not match, it is determined that a latch miss has occurred. The output of the comparison unit is used as the control signal of the selector, and when it is determined that a latch error has occurred, the output of the holding unit of the second output is selected instead of the output of the third holding unit.

In the fifth aspect of the invention, the input data held in the first holding unit by the first clock is held in the second holding unit by the second clock. Further, the output of the second holding unit is held by the third holding unit by the second clock. In addition, the second clock
The output of the holding unit is held by the fourth holding unit. The outputs of the second and third holding units are compared by the comparing unit. If they do not match for two clocks, it means that a latch miss has occurred. The control signal of the selector is constructed from the output of the comparison unit, and when a latch error occurs, the output of the holding unit of the fourth output is selected instead of the output of the third holding unit.

In the invention of claim 6, the input data held in the first holding unit by the first clock is held in the second holding unit by the second clock. Further, the output of the second holding unit is held by the third holding unit by the second clock. In addition, the second clock
The output of the holding unit is held by the fourth holding unit. The outputs of the second and third holding units are compared by the comparing unit. If they do not match for two clocks, it means that a latch miss has occurred. Furthermore, the output of the third holding unit and the output of the fourth holding unit are also compared, the control signal of the selector is constructed from the outputs of the two comparing units, and when a latch miss occurs,
Instead of the output of the third holding unit, the output of the holding unit of the fourth output is selected.

According to the invention of claim 7, even when the rising edges of the second clock and the first clock are overlapped,
Even if the inverted clock of the second clock and the rising edge of the first clock overlap, the first clock is
Of the first clock and the inverted clock of the second clock are used as a clock, and the first clock is held at the timing delayed from the time when the rising edges of the clocks overlap. The data held by the clock of 1 is held.

According to another aspect of the present invention, when the rising edges of the first clock and the second clock coincide with each other, the data in which the input data is held by the second clock is converted by the clock whose rising coincidence is masked. By holding it, latch miss is avoided.

[0021]

【Example】

Example 1. FIG. 1 is a block diagram showing a clock transfer circuit according to an embodiment of the present invention. In the figure, 1 is a flip-flop that holds input data by a first clock, 2 is an inverter that inverts the phase of a second clock, 3 is a flip-flop that holds the output of the flip-flop 2 by a second clock, 4 Is a flip-flop that holds the output of the flip-flop 3 by the second clock, that is, delays it by one clock, 7 is a flip-flop that holds the output of the flip-flop 1 by the inverted clock of the second clock, and 11 is the flip-flop 3
Is compared with the output of the flip-flop 4, and when they are equal, L,
When they are different, a comparator that outputs H, 12 is a flip-flop that holds the output of the comparator 11 by the second clock, 13 is a flip-flop that holds the output of the flip-flop 12 by the second clock, that is, a 1-clock delay 14 is a flip-flop 12,
AND gate that takes the logical product of the flip-flops 13, 1
Reference numeral 5 is a flip-flop for holding the output of the AND gate 14 by the second clock, 100 is a delay means for timing the output of the flip-flop 4 and the output of the flip-flop 15, and 200 is the output of the flip-flop 7 and the flip-flop. A delay means for adjusting the time with the output of 15; a selector for switching the output of the delay means 100 and the delay means 200 according to the output of the flip-flop 15; and 17 for holding the output of the selector 16 by the second clock. It is a flip-flop.

Next, the clock transfer operation of the above embodiment will be described with reference to FIG. First, the case where the flip-flop 3 causes a latch miss will be described. The data latched by the first clock (hereinafter, referred to as CLK1) in the flip-flop 1 (FIG. 2D) is the second clock (hereinafter, referred to as CLK2) in the flip-flop 3.
(FIG. 2 (e)), and the flip-flop 7 is latched by the inverted clock of the second clock (hereinafter referred to as inverted CLK2) (FIG. 2 (g)). At this time, it is assumed that a latch miss has occurred in the flip-flop 3, that is, the output of the flip-flop 3 is indefinite (FIG. 2 (e)). Next, the comparator 11 compares the outputs of the flip-flops 3 and 4 and outputs L if the values of the two flip-flop outputs match, and outputs H otherwise. In this case, the output of the comparator 11 becomes H for 2 clocks in which the outputs of the flip-flops 3 and 4 are indefinite (FIG. 2 (j)). The output of the comparator 11 is the flip-flop 12 and the flip-flop 1
When latched by 3 and ANDed by AND gate 14, these outputs are as shown in FIG.
Becomes AND gate 14 output is latched by CLK2,
This is used as a select signal for the selector 16 (see FIG. 2).
(N)). A delay means is used to time the period when the input signal of the selector 16 is indefinite and the period when the select signal is H. For example, flip-flop 4
Output signal of flip-flop 5, flip-flop 6
By CLK2, the output signal of the flip-flop 7 is latched by the flip-flop 8 and the flip-flop 9 by the inverted CLK2, and the flip-flop 10 is latched once by CLK2. Then, when the select signal is L, the output of the flip-flop 6 is selected, and when it is H, the output of the flip-flop 10 is selected (FIG. 2 (q)). Finally, the output of the selector 16 is C
It is latched by LK2 and output (FIG. 2 (r)).

In the above embodiment, in order to match the output times of the flip-flop 4, the flip-flop 7, and the flip-flop 15, the flip-flop 5, the flip-flop 6, the flip-flop 8, the flip-flop 9, and the ff
Although 10 is used, it goes without saying that other delay means may be used as long as the time can be adjusted.

Example 2. FIG. 3 is a block diagram showing a second embodiment of the present invention. In the figure, reference numeral 18 denotes a flip-flop that holds input data by the first clock,
19 is an inverter for inverting the phase of the second clock, 2
0 is a flip-flop that holds the output of the flip-flop 18 by the second clock, 21 is a flip-flop that holds the output of the flip-flop 18 by the inverted clock of the second clock, and 22 is the flip-flop 18
A flip-flop for holding the output of the flip-flop with the inverted clock of the second clock, 23 for comparing the outputs of the flip-flop 20 and the flip-flop 22, and a comparator for outputting L when they are equal and an H when they are different, and 24 for the comparator 23 2 which is a selector for switching the outputs of the flip-flop 20 and the flip-flop 21 according to the output
Reference numeral 5 is a flip-flop that holds the output of the selector 24 by the second clock.

Next, the clock transfer operation of the above embodiment will be described with reference to FIG. The data (FIG. 4B) latched by the first clock (hereinafter, referred to as CLK1) in the flip-flop 18 is changed by the second clock (hereinafter, referred to as CLK2) in the flip-flop 20 (see FIG. 4).
(E)), and is latched by the flip-flop 21 by the inverted clock of the second clock (hereinafter referred to as inverted CLK2) (FIG. 4 (g)). At this time, a latch miss occurs in the flip-flop 20, that is, the flip-flop 2
It is assumed that the output of 0 is indefinite (FIG. 4 (e)). The latch output of the flip-flop 20 is C in the flip-flop 22.
It is latched by LK2, that is, delayed by one clock (FIG. 4 (f)). Next, the comparator 23 compares the outputs of the flip-flops 20 and 22 and
If the values of the two flip-flop outputs match, L,
Otherwise, H is output. In this case, the output of the comparator 23 is H during two clocks when the outputs of the flip-flop 20 and the flip-flop 22 are indefinite (FIG. 4 (h)). The output of the comparator 23 is used as the select signal of the selector 24. When the signal of the selector 24 is H, the output of the flip-flop 20 is selected, and when the signal of the selector 24 is L, the output signal of the flip-flop 21 is selected, and the output of the selector 24 is as shown in FIG. Therefore, when the relationship such as t6 <t1− (t2 + t3 + t5) t7 <t2 + t4 is satisfied, the flip-flop 25 operates correctly without causing a latch miss (FIG. 4 (j)). However, t1: time when H becomes 1 clock period in CLK2 t2: propagation delay of flip-flop t3: propagation delay of comparator t4: propagation delay of selector 24 (input → output) t5: propagation delay of selector 24 (select signal → Output) t6: Flip-flop setup time t7: Flip-flop hold time

Example 3. FIG. 5 is a block diagram showing a clock transfer circuit according to an embodiment of the present invention. In the figure, 26 is a flip-flop that holds the input data by the first clock, 27 is a flip-flop that holds the output of the flip-flop 26 by the second clock, and 28 is an output that holds the output of the flip-flop 27 by the second clock. A flip-flop for delaying by 1 clock, 29 is a flip-flop for holding the output of the flip-flop 28 by the second clock, that is, for delaying by 1 clock, 30 is a flip-flop for holding the output of the flip-flop 29 by the second clock, that is, 1 clock Flip-flop 31 for delay, 31 compares the outputs of flip-flop 27 and flip-flop 28, and when they are equal, L,
When they are different, a comparator that outputs H, 32 is a flip-flop that holds the output of the comparator 31 by the second clock, 33 is a flip-flop that holds the output of the flip-flop 32 by the second clock, that is, that delays by one clock, 34 is a flip-flop 32,
AND gate which takes the logical product of the flip-flops 33, 3
Reference numeral 5 is a flip-flop for holding the output of the AND gate 34 by the second clock, and 36 is a flip-flop 3.
A selector that switches the outputs of the flip-flop 29 and the flip-flop 30 according to the output of 5 and a flip-flop 37 that holds the output of the selector 36 by the second clock.

Next, the clock transfer operation of the above embodiment will be described with reference to FIG. The data latched by the first clock (hereinafter, referred to as CLK1) in the flip-flop 26 (FIG. 6C) is latched by the second clock (hereinafter, referred to as CLK2) in the flip-flop 27. At this time, it is assumed that a latch miss has occurred, that is, the output of the flip-flop 27 is indefinite (FIG. 6).
(D)). The latch output of the flip-flop 27 is latched by the CLK2 in the flip-flop 28, that is, 1
The clock is delayed (FIG. 6 (e)). Further, the latch output of the flip-flop 28 is the flip-flop 29 (FIG. 6 (l)), and the latch output of the flip-flop 29 is the flip-flop 30 (FIG. 6 (k)).
It is latched by K2, ie delayed by one clock each. Next, the comparator 31 compares the outputs of the flip-flops 27 and 28, and outputs L if the values of the two flip-flop outputs match, and outputs H otherwise. In this case, the output of the comparator 31 becomes H for two clocks when the outputs of the flip-flop 27 and the flip-flop 28 are indefinite (FIG. 6).
(F)). The output of the comparator 31 is the flip-flop 3
2, latched by flip-flop 33, AND gate 3
The logical product of these outputs at 4 is as shown in FIG. 6 (i), which becomes H for one clock. The output of the AND gate 34 is latched by CLK2, and this is used as the select signal of the selector 36 (FIG. 6 (j)). Select signal is L
When the flip-flop 30 is selected in the case of and the flip-flop 29 is selected in the case of H, the result is as shown in FIG. Then, the output of the selector 36 is latched by CLK2 and output (FIG. 6 (n)).

Example 4. FIG. 7 is a block diagram showing a clock transfer circuit according to a fourth embodiment of the present invention. In the figure, 38 is a flip-flop that holds input data by the first clock, and 39 is a flip-flop 38.
Of the output of the flip-flop 39 is held by the second clock, 40 is a flip-flop that holds the output of the flip-flop 39 by the second clock, 41 is a flip-flop that holds the output of the flip-flop 40 by the second clock, 42 Compares the outputs of the flip-flop 40 and the flip-flop 41, and outputs L when they are equal and outputs H when they are different, and 43 is a comparator 42
Is a selector that switches the outputs of the flip-flop 39 and the flip-flop 40 in accordance with the output of the flip-flop 39. The flip-flop 44 holds the output of the selector 43 by the second clock.

Next, the clock transfer operation of the above embodiment will be described with reference to FIG. First, a case where the flip-flop 39 causes a latch miss will be described. The data latched by the first clock (denoted by CLK1) in the flip-flop 38 (FIG. 8B) is latched by the first clock (denoted by CLK2) in the flip-flop 39. At this time, it is assumed that a latch miss occurs in the flip-flop 39, that is, the output of the flip-flop 39 is indefinite (FIG. 8 (d)). The latch output of the flip-flop 39 is latched by CLK2 in the flip-flop 40, that is, delayed by one clock (FIG. 8 (e)).
Further, the latch output of the flip-flop 40 is latched by CLK2 in the flip-flop 41, that is, delayed by another clock (FIG. 8 (f)). Next, the comparator 42 flips the flip-flop 40 and the flip-flop 4.
The outputs of 1 are compared, and L is output if the values of the two flip-flop outputs match, and H is output otherwise.
In this case, the flip-flop 40 and the flip-flop 4
Comparator 4 during 2 clocks when the output is undefined at 1
The output of 2 becomes H (FIG. 8 (g)). The output of the comparator 42 is used as the select signal of the selector 43. When the signal of the selector 43 is H, the output of the flip-flop 39 is selected, and when the signal of the selector 43 is L, the output signal of the flip-flop 40 is selected, and the output of the selector 43 is as shown in FIG. Finally, the output of the selector 43 is latched by the clock 2 and output (FIG. 8 (i)).

Example 5. FIG. 9 is a block diagram showing a clock transfer circuit according to a fifth embodiment of the present invention. In the figure, 45 is a flip-flop that holds input data according to the first clock, and 46 is a flip-flop 45.
A flip-flop for holding the output of the flip-flop 46 by the second clock, 47 is a flip-flop for holding the output of the flip-flop 46 by the second clock, that is, delaying by 1 clock, 48 is a comparison of the outputs of the flip-flops 46 and 47 However, a comparator that outputs L when they are equal and outputs H when they are different, 49 is a T flip-flop that divides CLK2 in half, and 50 is the logical product of the output of the comparator 48 and the output of the T flip-flop 49. AND gate, 51 is a flip-flop for holding the output of the AND gate 50 by the second clock, 52
Is a selector that switches the outputs of the flip-flops 46 and 47 according to the output of the flip-flop 51, and 48 is a flip-flop that holds the output of the selector 47 by the second clock.

Next, the clock transfer operation of the above embodiment will be described with reference to FIG. First in flip-flop 45
The data latched by the clock (hereinafter, referred to as CLK1) of FIG.
And is latched by the second clock (hereinafter referred to as CLK2). At this time, it is assumed that a latch miss has occurred, that is, the output of the flip-flop 46 is indefinite (FIG. 10).
(D)). The latch output of the flip-flop 46 is latched by CLK2 in the flip-flop 47, that is, 1
The clock is delayed (FIG. 10 (e)). Next, the flip-flop 46 and the flip-flop 4 are compared by the comparator 48.
The outputs of 7 are compared, and L is output if the values of the two flip-flop outputs match, and H is output otherwise.
In this case, the flip-flop 46 and the flip-flop 4
During 2 clocks when the output becomes undefined at 7, the comparator 4
The output of 8 becomes H (FIG. 10 (f)). CLK2 is divided in half by the T flip-flop 49 (see FIG.
(G)), AND gate 50 obtains the logical product of the comparator 48 and the output of the T flip-flop, as shown in FIG. The output of the AND gate 50 is latched by CLK2, and this is used as the select signal of the selector 52 (FIG. 10 (i)). When the select signal is L, the flip-flop 46 is selected, and when the select signal is H, the flip-flop 47 is selected, as shown in FIG. And the selector 52
Output is latched by CLK2 and output (see FIG. 10).
(K)).

Example 6. FIG. 11 is a block diagram showing a clock transfer circuit according to a sixth embodiment of the present invention. In the figure, 54 is a flip-flop that holds input data by the first clock, and 55 is a flip-flop 5.
4 is a flip-flop for holding the output of 4 by the second clock, 56 is a flip-flop for holding the output of the flip-flop 55 by the second clock, that is, delaying by 1 clock, 57 is an output of the flip-flop 56 by the second clock A flip-flop which holds, that is, delays by one clock, 58 compares the outputs of the flip-flops 55 and 56, and when they are equal, L,
When they are different, a comparator that outputs H, 59 compares the outputs of the flip-flop 56 and the flip-flop 57,
A comparator that outputs L when they are equal and outputs H when they are different,
Reference numeral 60 is an AND gate that obtains the logical product of the comparators 58 and 59, 61 is a flip-flop that holds the output of the AND gate 60 by the second clock, and 62
Is a selector that switches the outputs of the flip-flop 56 and the flip-flop 57 according to the output of the flip-flop 61, and 63 is a flip-flop that holds the output of the selector 62 by the second clock.

Next, the clock transfer operation of the above embodiment will be described with reference to FIG. First in flip-flop 54
The data latched by the clock (hereinafter, referred to as CLK1) of FIG.
And is latched by the second clock (hereinafter referred to as CLK2). At this time, it is assumed that a latch miss has occurred, that is, the output of the flip-flop 55 is indefinite (FIG. 12).
(D)). The latch output of the flip-flop 55 is latched by CLK2 in the flip-flop 56, that is, 1
The clock is delayed (FIG. 12 (e)). Further, the latch output of the flip-flop 56 is latched by the CLK2 in the flip-flop 57, that is, delayed by one clock (FIG. 12 (f)). Next, the comparator 58 compares the outputs of the flip-flops 55 and 56, and outputs L if the two flip-flop outputs have the same value, and outputs H otherwise. Similarly, in the comparator 59, the flip-flop 56, the flip-flop 57
Are compared, and if the values of the two flip-flop outputs match, L is output, otherwise H is output. In this case, the flip-flop 56 and the flip-flop 57
During 2 clocks when the output is undefined at
Output becomes H (FIG. 12 (g)), and the output of the comparator 58 becomes H during two clocks when the outputs of the flip-flop 56 and the flip-flop 57 are indefinite (FIG. 12).
(H)). When the logical product of the outputs of the comparator 58 and the comparator 59 is calculated by the AND gate 60, it becomes as shown in FIG. 12 (i), which becomes H for one clock. AND gate 60
The output of is latched by CLK2 and this is used as a select signal of the selector 62 (FIG. 12 (j)). If the flip-flop 56 is selected when the select signal is L and the flip-flop 57 is selected when the select signal is H, the result is as shown in FIG. Then, the output of the selector 62 is latched by CLK2 and output (FIG. 12 (m)).

Example 7. FIG. 13 is a block diagram showing a clock transfer circuit according to the seventh embodiment of the present invention. In the figure, 64 is a flip-flop that holds the input data by the first clock, 65 is an inverter that inverts the phase of the second clock, 67 is a flip-flop that holds the first clock by the second clock, 66
Is a flip-flop that holds the first clock by the inverted clock of the second clock, 68 is an AND gate 68 and 69 that takes the logical product of the flip-flop 67 and the flip-flop 66, and the output of the flip-flop 64 is the output of the AND gate A holding flip-flop 70 is a flip-flop that holds the output of the flip-flop 69 by the second clock.

Next, the clock transfer operation of the above embodiment will be described with reference to FIG. First clock (hereinafter CLK
1) is held by the flip-flop 67 at the rising timing of the second clock (hereinafter referred to as CLK2) (FIG. 14 (e)). Further, the flip-flop 66 causes the inverted clock of the second clock (hereinafter, inverted CL
It is held at the rising timing of K2) (FIG. 14 (f)). At this time, FIGS. 14 (a) and 14 (c)
As described above, it is assumed that the rising edges of CLK1 and CLK2 overlap. Then, it is assumed that the output of the flip-flop 67 becomes H (FIG. 14 (e)). In this case, assuming that the output of the flip-flop 64 is held by the flip-flop 69 using the output of the flip-flop 67 as a clock, the clock rises at the change point of the output of the flip-flop 64, which may cause a latch miss. The clock applied to the flip-flop 69 in order to prevent the latch miss is applied to the flip-flop 6 by using the AND gate 68.
7 and the data held in the flip-flop 66 are logically ANDed (FIG. 14 (g)). When the clock configured by the above method is used, the rise of the clock applied to the flip-flop 69 is delayed by half a clock, so that the flip-flop 69 can prevent a latch miss (FIG. 14).
(H)). Finally, output the flip-flop 69 to CLK
It is latched by 2 and output (FIG. 14 (i)).

Further, when the output of the flip-flop 67 becomes L, the output of the AND gate 68 becomes as shown in FIG. 15 (g), and in this case also, the rising edge of the clock applied to the flip-flop 69 and the flip-flop. The change points of the outputs of 64 do not coincide with each other, and no latch miss occurs.

Example 8. FIG. 16 is a block diagram showing a clock transfer circuit according to the eighth embodiment of the present invention. In the figure, reference numeral 52 designates input data as a first clock (hereinafter,
A flip-flop held by CLK1),
Reference numeral 53 is a delay element that delays the second clock (hereinafter, referred to as CLK2) for a predetermined time, 54 is a flip-flop that latches the output of the delay element by CLK2 (the output of the flip-flop 54 is hereinafter referred to as CLK2 ′), 5
Reference numeral 5 is a flip-flop that holds the output of the flip-flop 52 by CLK2 ', that is, delays one clock, 56 is a flip-flop that holds the output of the flip-flop 52 by CLK2', that is, that is delayed by one clock, and 57 is a flip-flop 56. CLK output
2'holds, that is, a flip-flop that delays by 1 clock, 58 is a flip-flop that holds the first clock by the second clock, 59 is a flip-flop that holds the output of the flip-flop 58 by the second clock, 60 Is an EXOR gate that takes the exclusive OR of the flip-flops 58 and 59,
Reference numeral 61 is a flip-flop that holds the output of the EXOR gate 60 by the second clock, 62 is a flip-flop that holds the output of the flip-flop 61 by the second clock, and 63 is the logical product of the flip-flop 61 and the flip-flop 62. AND gate, 64 is an inverter that inverts the phase of the second clock, 65 is a flip-flop that holds the output of the AND gate 63 by the inverted clock of the second clock, and 66 is the logical product of the flip-flop 65 and CLK2. An AND gate 67 is a flip-flop that latches the output of the flip-flop 57 by the output of the AND gate 66, and 68 is a flip-flop that latches the output of the flip-flop 67 by CLK2.

Next, the clock transfer operation of the above embodiment will be described with reference to FIG. The second clock (hereinafter referred to as CLK2) delayed by the delay element 53 for a fixed time is latched by the CLK2 in the flip-flop 54, that is, a time equal to the propagation delay from the rising edge of the clock of the flip-flop to the output ( = Tpd)
Is delayed (FIG. 17 (d)). The output of the flip-flop 54 is CLK2 '. The input data is first input to the flip-flop 52 in the first clock (hereinafter,
CLK1) (FIG. 17 (b)),
Its output is latched by CLK2 'in the flip-flop 55, that is, delayed by one clock (FIG. 17).
(M)). Further, the output of the flip-flop 55 is a flip-flop 56 (FIG. 17 (n)), and the output of the flip-flop 56 is a flip-flop 57 (FIG. 17 (n)).
(O)), both are latched by CLK2 '. Further, CLK1 is CLK in the flip-flop 58.
Latched at the rising edge of 2 (see FIG. 17).
(E)). At this time, since the rising edges of CLK1 and CLK2 are overlapped with each other, if the output of the flip-flop 52 delayed by tpd from CLK1 is attempted to be latched by CLK2 ′ delayed by tpd from CLK2, a latch miss may occur. Flip-flop 58 at this time
It is assumed that the output of the signal H becomes H after a delay of tpd from the rise of CLK2 as shown in FIG. Flip flop 58
The output of is latched by CLK2 in the flip-flop 59, that is, delayed by one clock (FIG. 17 (f)).
Therefore, the EXOR gate 60 causes the flip-flop 58
17 (g) is obtained by taking the exclusive OR of the output of the above and the output of the flip-flop 59. EXOR gate 6
The output of 0 is output to the flip-flop 61 (see FIG.
(H)), the output of the flip-flop 61 is both latched by the CLK2 in the flip-flop 62 (FIG. 17 (i)), and the logical product of these outputs is taken in the AND gate 63, as shown in FIG. 17
(J)). By latching the output of the AND gate 63 with the inverted clock of CLK2 and taking the logical product of the output and CLK2, a signal that masks the rising edges of the rising edges of CLK1 and CLK2 is obtained (FIG. 17).
(L)). Using this signal as a clock, the output of the flip-flop 57 is latched (Fig. 17 (o)), and finally, this latched output is latched by CLK2 and output, as shown in Fig. 17 (p).
become that way.

Next, as shown in FIGS. 18A, 18C and 18D, it is assumed that the flip-flop 58 causes the rising edges of CLK1 and CLK2 to overlap with each other and the output thereof becomes L. The output of the flip-flop 58 is latched by CLK2 in the flip-flop 59, that is, delayed by one clock (FIG. 18).
(A)). Therefore, the exclusive OR of the output of the flip-flop 58 and the output of the flip-flop 59 is obtained by the EXOR gate 60 as shown in FIG. EXO
The output of the R gate 60 is C in the flip-flop 61 (FIG. 18H) and the output of the flip-flop 61 is C in the flip-flop 62 (FIG. 18I).
When latched by LK2 and the logical product of these outputs is taken in the AND gate 63, it becomes as shown in FIG.
When the output of the AND gate 63 is latched by the inverted clock of CLK2 (FIG. 18 (k)) and the logical product of the output and CLK2 is taken, a signal that masks the rising edges of the rising edges of CLK1 and CLK2 is obtained. It is obtained (FIG. 18 (l)). When the output of the flip-flop 57 is latched by using this signal as a clock (FIG. 18 (o)), and finally this latched output is latched by CLK2 and output,
It becomes like (p).

[0040]

According to the first to sixth aspects of the present invention,
Even if the rising edge of the clock of the data transmission source and the rising edge of the clock of the data receiving destination overlap, by replacing the undefined data with another data, the data received at the receiving side will not become unstable, and the clock The transfer can be performed well, and the clock transfer can be performed with a simple circuit configuration.

Further, according to the seventh and eighth aspects of the present invention, even if the clock of the data transmission source and the clock of the data reception destination overlap with each other, there is no rise at the time when the clocks overlap. By holding the data with the clock, the data received on the receiving side does not become unstable, and the clock transfer is favorably performed, and the clock transfer can be performed with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a clock transfer circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart of each part of the first embodiment of the present invention.

FIG. 3 is a block diagram showing a clock transfer circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart of each part of the second embodiment of the present invention.

FIG. 5 is a block diagram showing a clock transfer circuit according to a third embodiment of the present invention.

FIG. 6 is a time chart of each part of the third embodiment of the present invention.

FIG. 7 is a block diagram showing a clock transfer circuit according to a fourth embodiment of the present invention.

FIG. 8 is a time chart of each part of the fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a clock transfer circuit according to a fifth embodiment of the present invention.

FIG. 10 is a time chart of each part of the fifth embodiment of the present invention.

FIG. 11 is a block diagram showing a clock transfer circuit according to a sixth embodiment of the present invention.

FIG. 12 is a time chart of each part of the sixth embodiment of the present invention.

FIG. 13 is a block diagram showing a clock transfer circuit according to a seventh embodiment of the present invention.

FIG. 14 is a diagram showing the components of the seventh embodiment of the present invention when the rising edges of the first clock and the second clock overlap and the output becomes H when the first clock is latched by the second clock. It is a time chart.

FIG. 15 is a diagram showing the components of the seventh embodiment of the present invention when the rising edges of the first clock and the second clock overlap each other and the output becomes L when the first clock is latched by the second clock. It is a time chart.

FIG. 16 is a block diagram showing a clock transfer circuit according to an eighth embodiment of the present invention.

FIG. 17 is a diagram showing the components of the eighth embodiment of the present invention when the rising edges of the first clock and the second clock overlap and the output becomes H when the first clock is latched by the second clock. It is a time chart.

FIG. 18 is a diagram showing the components when the rising edges of the first clock and the second clock are overlapped with each other and the output is L when the first clock is latched by the second clock in the eighth embodiment of the present invention. It is a time chart.

FIG. 19 is a block diagram of a clock transfer circuit using a conventional flip-flop.

FIG. 20 is a time chart of each part of a clock transfer circuit using a conventional flip-flop.

[Explanation of symbols]

1,3 to 10,12,13,15,17,18,20
Through 22, 25, 26 through 30, 32, 33, 35, 3
7 to 41, 44 to 47, 51, 53 to 57, 6
1, 63, 64, 66, 67, 69 to 71, 73 to 78, 80, 81, 84, 86, 87, 89, 90 Flip-flop 49 T flip-flop 2, 19, 65, 83 Inverter 16, 24, 36 , 43, 52, 62 selectors 11, 23, 31, 42, 48, 58, 59 comparators 14, 34, 49, 63, 66 AND gates 79 EXOR gates 72 delay elements 100, 200 delay means

Claims (8)

[Claims] 1. A clock transfer circuit for exchanging data between circuits or devices which are not synchronized with each other, wherein first input data is held and output by a first clock.
Holding unit, a second holding unit that holds and outputs the output of the first holding unit by a second clock, and a third holding unit that holds and outputs the output of the second holding unit by a second clock. Of the first clock by the clock holding unit and the inverted clock of the second clock.
A fourth holding unit that holds and outputs the output of the second holding unit, a comparison unit that compares the output of the second holding unit and the output of the third holding unit, and the output of the comparison unit to the second holding unit. A fifth holding unit that holds and outputs the clock, and a sixth holding unit that holds and outputs the output of the fifth holding unit by the second clock;
An AND gate that takes the logical product of the output of the fifth holding unit and the output of the sixth holding unit, a seventh holding unit that holds and outputs the output of the AND gate by a second clock, and Three
Delay unit for adjusting the time between the holding unit and the seventh holding unit, second delay unit for adjusting the time between the fourth holding unit and the seventh holding unit, and the seventh delay unit. A selection unit that selects and outputs the output of the third holding unit and the output of the fourth holding unit according to the output of the holding unit of A clock transfer circuit having a holding unit. 2. A clock transfer circuit for exchanging data between circuits or devices which are not synchronized with each other, wherein first input data is held and output by a first clock.
Holding unit, a second holding unit that holds and outputs the output of the first holding unit by a second clock, and a third holding unit that holds and outputs the output of the second holding unit by a second clock. Of the first clock by the clock holding unit and the inverted clock of the second clock.
A fourth holding unit that holds and outputs the output of the second holding unit, a comparison unit that compares the output of the second holding unit and the output of the third holding unit, and the output of the comparison unit A second holding unit for selecting and outputting the output of the second holding unit and the output of the third holding unit; and a fifth holding unit for holding and outputting the output of the selecting unit by the second clock. Clock transfer circuit to do. 3. A clock transfer circuit for exchanging data between circuits or devices which are not synchronized with each other, wherein first input data is held and output by a first clock.
Holding unit, a second holding unit that holds and outputs the output of the first holding unit by a second clock, and a third holding unit that holds and outputs the output of the second holding unit by a second clock. Holding unit, a fourth holding unit that holds and outputs the output of the third holding unit by the second clock, and a fifth holding unit that holds and outputs the output of the fourth holding unit by the second clock. Holding unit, a comparing unit that compares the output of the second holding unit and the output of the third holding unit, and a sixth holding unit that holds and outputs the output of the comparing unit according to a second clock. , A seventh clock which holds and outputs the output of the sixth holding unit by the second clock
Holding unit, an AND gate that takes the logical product of the output of the sixth holding unit and the output of the seventh holding unit, and an eighth holding unit that holds and outputs the output of the AND gate by the second clock. Section, a selection section that selects and outputs the output of the fourth holding section and the output of the fifth holding section by the output of the eighth holding section, and the output of the selecting section is held by the second clock. And a ninth holding unit that outputs the clock transfer circuit. 4. A clock transfer circuit for exchanging data between circuits or devices which are not synchronized with each other, wherein first input data is held and output by a first clock.
Holding unit, a second holding unit that holds and outputs the output of the first holding unit by a second clock, and a third holding unit that holds and outputs the output of the second holding unit by a second clock. And a fourth holding unit that holds and outputs the output of the third holding unit by the second clock, and compares the output of the third holding unit and the output of the fourth holding unit. A comparing unit, a selecting unit that selects and outputs the output of the second holding unit and the output of the third holding unit by the output of the comparing unit, and the output of the selecting unit is held and output by the second clock. A clock transfer circuit having a fifth holding unit for 5. A clock transfer circuit for exchanging data between circuits or devices which are not synchronized with each other, wherein first input data is held and output by a first clock.
Holding unit, a second holding unit that holds and outputs the output of the first holding unit by a second clock, and a third holding unit that holds and outputs the output of the second holding unit by a second clock. And a fourth holding unit that holds and outputs the output of the third holding unit by the second clock, and compares the output of the third holding unit and the output of the fourth holding unit. A comparison unit, a frequency division unit that divides the output of the comparison unit into halves, an AND gate that performs a logical product of the output of the frequency division unit and a second clock, and the output of the AND gate A selection unit that selects and outputs the output of the third holding unit and the output of the fourth holding unit, and a fifth holding unit that holds and outputs the output of the selection unit according to a second clock. A clock transfer circuit characterized by: 6. A clock transfer circuit for exchanging data between circuits or devices which are not synchronized with each other, wherein first input data is held and output by a first clock.
Holding unit, a second holding unit that holds and outputs the output of the first holding unit by a second clock, and a third holding unit that holds and outputs the output of the second holding unit by a second clock. Comparing the output of the second holding unit and the output of the third holding unit with the fourth holding unit that holds and outputs the output of the third holding unit by the second clock. A first comparing unit, a second comparing unit that compares the output of the third holding unit and the output of the fourth holding unit, the output of the first comparing unit, and the second comparing unit.
AND gate for taking the logical product with the output of the comparator of
A fifth holding unit that holds and outputs the output of the ND gate by the second clock, and an output of the fifth holding unit selects the output of the third holding unit and the output of the fourth holding unit. And a sixth holding unit that holds and outputs the output of the selecting unit according to the second clock. 7. A clock transfer circuit for exchanging data between circuits or devices which are not synchronized with each other, wherein first input data is held and output by a first clock.
Holding unit, a second holding unit that holds and outputs the first clock by a second clock, and a third holding unit that holds and outputs the first clock by an inverted clock of the second clock. Section, a fourth holding section that holds and outputs the output of the first holding section at a timing when the output levels of the second holding section and the third holding section match, and the fourth holding section And a fifth holding unit that holds and outputs the output of the holding unit according to the second clock. 8. A clock transfer circuit for exchanging data between circuits or devices which are not synchronized with each other, wherein first input data is held and output by a first clock.
Holding unit, a delay unit that delays the second clock for a fixed time, a second holding unit that holds and outputs the output of the delay unit according to the second clock, and an output of the second holding unit. A third holding unit that holds and outputs the output of the first holding unit, and a fourth holding unit that holds and outputs the output of the third holding unit by the output of the second holding unit, A fifth holding unit that holds and outputs the output of the fourth holding unit by the output of the second holding unit; and a sixth holding unit that holds and outputs the first clock by the second clock. The seventh holding unit that holds and outputs the output of the sixth holding unit by the second clock, and the exclusive OR of the output of the sixth holding unit and the output of the seventh holding unit An EXOR gate, an eighth holding unit that holds and outputs the output of the EXOR gate according to a second clock, and a second clock. An AND gate for taking the ninth holding portion for holding outputs an output of the holding portion of said 8, a logical product of the output of the holding section and the output of the said 9 of the holding portion of said 8 by,
A tenth holding unit that holds and outputs the output of the AND gate by an inverted clock of the second clock, and an AND that takes the logical product of the output of the tenth holding unit and the second clock
An eleventh holding unit that holds and outputs the output of the fifth holding unit by the output of the gate and the AND gate, and a twelfth holding unit that holds and outputs the output of the eleventh holding unit by the second clock. And a holding unit for the clock transfer circuit.