JPS61179621A - Serial/parallel converting circuit - Google Patents

Abstract

PURPOSE:To simplify further the circuit constitution of a serial/parallel converting circuit converting a serial data sent continuously in terms of the hardware by providing a register inputting only a part of a bit data and saving it. CONSTITUTION:A serial data sent one by one bit in the order of a bit data Do of the least significant digit to the high-order digit bit data D1, D2,...D15 is inputted to a serial data input Din. Then a word data Wo is inputted sequentially from the head bit to a shift register 12. On the other hand, the input of the head bit data Do is finished and the succeeding bit data D1- is started to be inputted, the content Do of a 1-bit register 12c is transferred to a buffer register 12d synchronously with the timing signal cp3 at the 2nd bit and stored. Thus, the serial data Din transmitted continuously is converted sequentially into the parallel data Dout and outputted by repeating the operation that the data Do and D1-D15 stored respectively in the two registers 12d, 12 are extracted and latched when the head bit data Do is inputted and read in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a serial/parallel conversion technology and a technology that is particularly effective when applied to a serial/parallel conversion circuit with a complicated hardware configuration. This relates to a technology that is effective for use in serial/parallel conversion circuits on the digital input side of A (digital/analog) converters.

[Background technology]

Generally, serial data (serial data) is converted to parallel data (
As a means of converting to parallel data), micro-
There are software means using a computer and hardware means using a shift register.

The former software method has the flexibility to respond to changes in communication specifications, such as baud rate and protocol, by simply changing the program, but on the other hand, it has the flexibility to respond to changes in communication specifications such as baud rate and protocol by simply changing the program.
Since a computer system is required, the hardware configuration tends to be large-scale. Furthermore, since at least several hundred processing steps must be executed for the conversion process, it is not suitable for high-speed conversion operations.

In the latter hardware means, communication specifications such as baud rate and protocol are fixed in terms of hardware, but it can be configured with only a few types of circuit functions such as a shift register, a latch circuit, and a timing generation circuit. With this button, the hardware configuration is greatly simplified compared to the one using software means described above. Furthermore, since the conversion process is performed in the busy hardware time, there is an advantage that the conversion operation can be made extremely fast.

Therefore, the latter hardware means is suitable for applications where communication specifications are fixed, such as serial/parallel conversion of data read from a digital audio disc.

For example, Nikkei Electronics No. 282, published on January 18, 1982. Pages 186 to 216 show that serial data is converted to parallel data and used as digital input to the D/A converter. In this case, if the serial data is, for example, data read from a digital audio disc, the above-mentioned hardware means is suitable as means for converting the serial data into parallel data.

Therefore, the present inventors particularly focused on digital audio.
Prior to the present invention, a circuit as shown in FIG. 1 was studied as a serial/parallel conversion circuit for converting serial data from a disk into parallel data.

The serial/parallel conversion circuit 1o shown in FIG. 1 is configured in terms of hardware, and converts the serial data input Din sent together with the synchronized clock CK into parallel data Do-D 15 word by word. This is what is output. This serial/parallel conversion circuit 10 includes the first. It is comprised of second two shift registers 12a and 12b, a parallel data switching circuit 14, a parallel data latch circuit 16, a synchronous clock switching circuit 18, a timing generation circuit 20, and the like.

Here, the first. Second two shift registers 12a, 1
2b are the same, each having the number of pits for one word, that is, 16 7-limp flops F.
15 to Fo are connected in series.

The parallel data switching circuit 14 is for selecting the contents of either one of the two shift registers 12a, 12b and introducing it into the parallel latch circuit 16. It is designed to be switched each time it is input.

The parallel data latch circuit 16 is connected to the shift register 12a or 1 selected by the parallel data switching circuit 14.
The bit data at each shift stage of 2b, that is, the set output of each of the 7 lip-flops Fo=F15 is taken in in parallel and latched. Then, this latched state is input as a parallel data output Dout to the digital side of, for example, a D/A converter (not shown).

The synchronous clock switching circuit 18 switches and sends the synchronous clock signal CK input together with the serial data (Din) to either one of the two shift registers 12a and 12b. Only the shift register 12a or 12b receiving this synchronization clock CK performs a shift operation.

The timing generation circuit 2o generates a switching control signal apl for the parallel data switching circuit 14 and the synchronous clock switching circuit 18, and a latch timing signal (sampling signal) cp2 for the latch circuit 16, based on the synchronous clock and the like. Occurs every word period.

FIG. 2 shows part of the operation of the series/parallel circuit described above.

1 and 2, the serial data input (Din
) includes bit data (LSB) Do of the least significant digit to bit data DI of the upper digit, D2 . ....

Serial data sent bit by bit in the order of D15 is input. At the same time, a synchronous clock CK having a falling portion for each bit period is input.

For example, assume that when the word data w1 is input in series, the synchronization clock CK is applied to the second shift register 12b.

Then, the second shift register 12b receives the 16-pit filtered data (Do to D1) that composes the word data W1.
5) are input sequentially. At this point, since the other first shift register 12a is not given the rm1 period clock CK, the word data W that was input last time is
The shift operation is stopped while holding o. The first word data holding this previous word data Wo
Each shift stage (Fo-F15) of the shift register 12a of
is connected to the latch input side of the latch circuit 16 by the parallel data switching circuit 14. At the same time, the latch timing signal cp2 is generated while data is being input to the second shift register 12b. As a result, the previous word data WO held by the first shift register 12a is transferred in parallel to the latch circuit 16 and latched. Then, this latched word data IWo becomes the parallel data output Dout (Do-D1
5).

When the word data W1 has been input to the second shift register 12b, the states of the switching control signal cpl of the parallel data switching circuit 14 and the synchronous clock switching circuit 18 are switched, so that the first shift register 1
2a starts the shift operation and transfers the next word data W2.
Now you can shift input. At this point, the second shift register 12b receives the previously input word data W.
Stop the shift operation while holding the value 1. Then, word data W2 is transferred to the first shift register 12a.
is input in series, the second shift register 12
The word data W1 inputted to b is transferred to the latch circuit 16 in parallel.

As a result, the word data appearing on the parallel data output Dout is switched from WO to Wl.

In the above manner, two identical shift registers 1
2a and 12b are operated alternately, and while inputting serial data to one, parallel data is taken out from the other and latched. By repeating this operation, serial data (Din) that is continuously sent is obtained. is sequentially parallel data (Dou
t) and output.

By the way, in the above-described serial/parallel conversion circuit 10, in order to transfer parallel data while inputting serial data, the shift registers 12a and 12b have the same number of stages.
Two shift registers are required, and accordingly, a data switching circuit 14 is also required for switching the young column data from the two shift registers. Therefore, it was found necessary to further simplify this.

[Purpose of the invention]

An object of the present invention is to provide a technique for further simplifying the circuit configuration of a serial/parallel conversion circuit that performs hardware conversion of serial data that is continuously sent.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, by providing a register that inputs and saves only part of the bit data, it is possible to further simplify the circuit configuration of the serial/parallel conversion circuit that converts serial data that is continuously sent using hardware. It is intended to achieve the purpose of

[Example 1] Hereinafter, a typical example of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

The serial/parallel conversion circuit 10 shown in FIG. 3 is configured in terms of hardware, and converts serial data input (n) sent together with a synchronized clock CK into parallel data (Do-D) word by word. It is converted and output. This serial/parallel conversion circuit 10 distributes the serial data input Din (Do to D15) for each word into lower digit data Do and upper digit data D1 to D15 and inputs them into two registers 12 and 12c, respectively. do.

Along with this, the contents of one of the registers 12c (Do
) for temporarily saving the buffer register 12d.
will be established. When this one register 12cJm data Do is being input, the contents of the other register 12 (DI to D15) and the contents (Do) of the buffer register 12c are respectively latched and output in parallel. has been done.

Here, the one register 12c and the buffer register 12d each need to hold only the first bit (LSB) of data Do, and therefore each is constituted by only one stage of 7-lip 70-tube Fo and FF. The other register 12 is a multi-stage shift register, and includes 15 7-lip 70-tube F1s connected in series.
5 to FIK. This shift register 12
need only have a sufficient number of stages to shift and input 15 bits of data D1 to D15 excluding the first bit data Do.

To explain in more detail about FIG. 3, the series/
In the parallel conversion circuit 10, the registers 12.12c, 1
Other than 2d, there are only a parallel data 2-bit circuit 16, a timing generation circuit 20, etc., and the above-mentioned parallel data switching circuit 14 etc. are omitted.

The parallel data latch circuit 16 is connected to the shift register 12.
The bit data at each shift stage, that is, the set output of each of the seven lip-flops F1 to F15, and the 1-bit data held in the buffer register 12dK are taken in and latched in parallel. The latched states of both registers 12 and 12d are then input in parallel to the digital side of, for example, a D/A converter (not shown) as parallel data output Dout (Do=D15). At this time, the upper 15 digit data D1 to D15 from the shift register 12 and the least significant digit data D from the buffer register 12d.

are combined together and output as 16-pit parallel data.

The timing generation circuit 20 is constituted by, for example, a ring counter, and generates the latte timing signal (
sampling signal), cp2 and buffer register 1
A save write timing signal cp3 to 2d is generated every one word cycle.

FIG. 4 shows part of the operation of the series/parallel circuit described above.

3 and 4, the serial data input (Din
) includes bit data (LSB) Do of the least significant digit to bit data DI, D2, . . . of the upper digits.

Serial data sent one pit at a time in the order of D15 is input. At the same time, a synchronous clock CK having a falling portion for each bit period is input.

For example, when word data Wo is input in series, first the first bit (LSB) of the word data Wo is input.
) is written into the 1-bit register 12c in synchronization with the timing signal cp2.

Next, the word data Wo is stored in the shift register 12.
are input in order from the first pit. On the other hand, after the input of the first bit data Do is completed, the subsequent bit data D1
When ~ starts to be input, the contents (DO) of the 1-bit register 12c are changed to the timing signal cp3 at the 2nd bit.
The data is transferred to the buffer register 12d and held in synchronization with the above.

Thereafter, when the input of the 16-pit data Do-D15 forming the word data Wo is completed, the next word data W1 is input again in order starting from the first bit data Do.

Then, the first bit data Do of the word data W1
is being input to the 1-bit register 12c, the contents of each shift stage of the shift register 12, that is, the data D1 to D15 held in the seven lip-flops F1 to F15 of each stage, are saved to the buffer register 12d. Together with the first bit data Do, it is transferred in parallel to the latch circuit 16 in synchronization with the timing signal cp2, and is doubled. In other words, the word data Wo that was serially input last time is the first peer of the next word data W1)
When data Do is read, it is transferred in parallel to the latch circuit 16 and latched. This latched word data Wo becomes the parallel data output Dout (Do=D15).

As described above, when the first bit data Do is input and read, the two registers 12d.

12, the data Do and D1~
By repeating the operation of extracting and latching D15, the serial data (Din) that is continuously sent can be sequentially converted into parallel data (Dout) and output. At this time, seven lip-flops Fo-F15 . In the embodiment described above, it is sufficient to have 15+1+1=17 FFs. Moreover, here, the parallel data switching circuit 14 (FIG. 1) and the like described above are unnecessary. Therefore, compared to the one shown in FIG. 1, the circuit configuration is significantly simplified while having the same functions.

[Embodiment 2] A more specific circuit of the above-mentioned serial/parallel conversion circuit of the present invention is shown in FIG. Further, each signal waveform in FIG. 5 is shown in FIG. 6.

The serial/parallel conversion circuit shown in Fig. 5 is a semiconductor integrated circuit (I
C). Next, the circuit operation will be explained. Data W
When o is input in series, the first bit (LS
B) is held in the D-type flip-flop Fo in synchronization with the fall of the timing signal apl generated by the timing generation circuit 20. Next, bit data Di of data WO
.about.D15 are deposited into the shift register 12 composed of D-type flip-flop circuits F1 to F15, and are transferred one after another in synchronization with the timing signal cp2. On the other hand, the first bit data Do of the data Wo held in the flip-flop Fo is transferred to the D-type flip 70 block F16 in synchronization with the falling edge of the timing signal cp3.

In this way, the D-type 7 lip-flop circuit Fo-F16
After the 16-bit data Do-D15 is held, the held data is input in parallel to the D/A converter input latch circuit 16 in synchronization with the fall of the timing signal cp4. The data Do-D15 output from the input latch circuit is further input to the digital comparator 17, and the output of this digital comparator causes the switch SWI OO~
5W226 controlled and weighted electrician 0-126
A current of the sum of Io flows through line 10 to capacitor C1
is stored in As a result, the integrated D
/A conversion output appears and is outputted via the sample and hold circuit 19. Thereafter, the npn transistor Q1 is turned on by the timing signal cp5, the charge stored in the capacitor C1 is discharged, and the D/A converter is reset.

After that, the first bit data Do of the data W2 is held in the D-type flip-flop Fo, and the D-type flip-flop 7
Each bit data of the data W1 stored in the zero tubes F1 to F16 is input in parallel to the input latch circuit 16, and the same operation is repeated thereafter.

According to the present invention, the input interval Ti of data Wo, Wl, W2
can be shortened. In addition, only 17 flip-flop circuits are required, reducing the number of elements and reducing the chip area when integrated into an IC.

〔effect〕

111 A buffer register is provided to input and hold only a part of bit data, and when that part of bit data is being input, the contents of the register to which other bit data has been input are saved to the buffer register. By transferring the serial data in parallel along with the transmitted data, it is possible to further simplify the circuit configuration of the serial/parallel conversion circuit that converts serial data that is continuously sent using hardware.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the register 12c and the buffer register 12d may each be configured to hold serial input data of 2 bits or more. Although the application has been explained to the serial/parallel conversion technology used with D/A converters, which is a field of application that has become a new field of application, it is not limited to this (for example, input/output interface technology in microcomputer systems) It can be applied to at least conditions where serial data that is sent continuously is converted to parallel data.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a serial/parallel conversion circuit studied prior to this invention, Fig. 2 is a timing chart showing the operation of the serial/parallel conversion circuit shown in Fig. 1, and Fig. 3 is based on this invention. FIG. 4 is a timing chart showing the operation of the serial/parallel converter shown in FIG. 3. FIG. FIG. 5 is a circuit diagram showing a second embodiment of the serial/parallel conversion circuit of the present invention, and FIG. 6 is a timing chart showing the operation of the serial/parallel conversion circuit shown in FIG. 10...Serial/parallel conversion circuit, 12, 12a. 12b...shift register, 12C...register,
12d... Back 7 register, 14... Data switching circuit, 16... Latch circuit, 17... Digital comparator, 18... Clock switching circuit, 19... Counter, 20... Timing generation Circuit, 22...Crystal oscillator, Din...Series data input, Dout
...Parallel data output, CK...Clock, DO~D
15...Data, CI, C2...Capacitor, Ql
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Claims (1)

[Claims] 1. Serial data converter that converts serial data into parallel data and outputs it.
A parallel conversion circuit that divides serial data input for each word into lower digit data and upper digit data and inputs them into two registers, respectively, and temporarily saves the contents of one of the registers. A serial system characterized in that a buffer register is provided for this purpose, and when data is input to one of the registers, the contents of the other register and the contents of the buffer register are respectively latched and output in parallel. /Parallel conversion circuit. 2. The serial/parallel conversion circuit according to claim 1, wherein the one register and the buffer register are circuits that each hold a first bit of data.