JP2008193516A - Random error signal generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To materialize a random error signal which has specified error rate and error distribution approximated to Poisson distribution. <P>SOLUTION: This random error signal generator is provided with: a PN signal generation circuit 6 of M series which outputs a plurality of pieces of bit data stored in each register 7 in parallel whenever clocks are input; a data position replacement circuit 21 which replaces data positions of the plurality of pieces of bit data output in parallel by being synchronized with the clocks from the PN signal generation circuit 6; and a comparator 26 which receives, at one end, the plurality of pieces of bit data with data positions replaced by the data position replacement circuit, and which captures the plurality of pieces of input data as one numeric value and outputs the random error signal to be an error bit when the numeric value is equal to or below a reference value corresponding to the specified error rate input to the other end. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a random error signal generator for generating a random error signal having a specified error rate and having an error distribution of a Poisson distribution.

  In a test apparatus that performs various tests on various communication devices incorporated in a digital communication network using a general electric signal cable or an optical communication network using an optical fiber cable, this communication is performed on the communication device to be tested. A test signal that matches the actual usage status of the device is input to evaluate the response operation of the communication device. As one type of evaluation test for such a communication device, a test signal that intentionally includes an error is employed as a test signal that matches the actual usage situation transmitted to the communication device to be measured. Then, the communication device evaluates to what extent the error occurrence rate (error rate) E included in the test signal operates normally.

Normally included for some reason including external noise in various digital signals transmitted and received in communication networks connecting between stations, not between general user terminals and base stations or between subscriber terminals and telephone stations. The occurrence rate (error rate) E of an error (error bit) is on the order of E = 10 ⁻² to 10 ⁻⁸ . Moreover, errors occur randomly.

Therefore, as shown in FIG. 26, in addition to the test signal generation circuit 2 that generates the original digital test signal a, the test apparatus 1 has a specified error occurrence rate (error rate) E and randomly, for example, “1 A random error signal generator 3 for generating a random error signal b in which a bit error occurs is incorporated. Then, an exclusive OR operation is performed on the digital test signal a output from the test signal generation circuit 2 and the random error signal b output from the random error signal generator 3 by the exclusive OR gate 4, and the operation result is obtained. by inverted by the inverter 5 to generate a test signal a ₁ which contain errors for the specified error occurrence rate E.

  It has been demonstrated that the frequency of events that occur spontaneously in nature follows a Poisson distribution. Therefore, the distribution on the time axis of errors included in various digital signals transmitted and received between the stations of the communication network described above also follows the Poisson distribution. For this reason, it is preferable that the error distribution of the random error signal b generated by the random error signal generator 3 incorporated in the test apparatus 1 also follows the Poisson distribution.

  An example of a random error signal generator that generates a random error signal having an error distribution of the Poisson distribution is proposed in Patent Document 1. Although the detailed configuration of this random error signal generator is not clearly described in Patent Document 1, it can be estimated from the specification and drawings that the random error signal generator 3 has the configuration shown in FIGS. .

As is well known, a PN (Pseudo Noise pseudo-random) signal generation circuit 6 includes m stages of registers 7 and one or a plurality of exclusive OR gates 8 connected in series as shown in FIG. When the clock signal CLK is applied from the external clock circuit 9 to each register 7, a PN signal that is a digital serial signal having a cycle of (2 ^m −1) is output from the output terminal 10.

  Each time the clock signal CLK is input, the bit data (pseudo-random binary sequence) stored in the m registers 7 are output in parallel. Each bit data output in parallel from the PN signal generation circuit 6 is applied to one input terminal (X terminal) of the comparator 11. The other input terminal (Y terminal) of the comparator 11 receives a parallel m-bit reference value input by the operator through the reference value setting circuit 12.

  The comparator 11 takes in m pieces of bit data applied to one input terminal (X terminal) as one numerical value A. Similarly, the parallel m-bit reference value B applied to the other input terminal (Y terminal) is also taken as one numerical value. When the numerical value A taken in from one input terminal (X terminal) is less than or equal to the reference value B taken in from the other input terminal (Y terminal), the comparator 11 has a ramdam error signal b that becomes an error bit. Is output.

The reference value B is set corresponding to the error occurrence rate (error rate) E of the random error signal b output from the random error signal generator 3. For example, when the error rate E is 0.004 (0.4%) and the value A that the X terminal can take is 1 to 1000, the reference value B is set to “4”. Since the probability that the numerical value A is 4 or less is 4/1000, a ramdam error signal b having an error rate E of 0.004 is obtained.
JP 2002-330192 A

  However, the random error signal generator 3 shown in FIG. 27 still has the following problems to be solved.

  That is, the error occurrence rate (error rate) E of the random error signal b output from the random error signal generator 3 can be made to coincide with the specified error occurrence rate (error rate) E. The distribution does not necessarily match the Poisson distribution that exists in nature. The reason for this will be described with reference to FIG.

FIG. 29 is a time chart showing the operation of the random error signal generator 3 of FIG. One of the clock signal CLK in the cycle T _C of the clock signal CLK at the time of the input, a portion of the PN signal of the period of the PN signal generating circuit 6 (2 ^m -1) is the case of [... 0110000000000 ...] For example, when m is 10, for example, when m pieces (bits) of parallel data output from the m registers 7 are [0000000], the numerical value A of the m pieces (bits) of data is [0]. It is. When the reference value B is [4], since the numerical value A ≦ reference value B, the output of the comparator 11 is the error bit [1].

  When the next clock signal CLK is input, the data in each register 7 is shifted one by one, so the m (bit) data in parallel becomes [1000000000], and the numerical value A of the m (bit) data is [ 1]. Since the reference value B does not change with [4], the output of the comparator 11 remains the error bit of [1].

  Further, when the next clock signal CLK is input, the data in each register 7 is shifted one by one, so that m (bit) data in parallel becomes [11000000], and the numerical value A of the m (bit) data is A. Is [3]. Since the reference value B is [4], the output of the comparator 11 remains the error bit of [1].

  Further, when the next clock signal CLK is input, the data in each register 7 shifts by one, so that m (bit) data in parallel becomes [0110000000], and the numerical value (m) of the m (bit) data ( Data numerical value) A is [6]. Since the reference value B is [4], the output of the comparison committee 11 changes to a normal bit of [0].

  As described above, since the data only shifts between the registers 7 in synchronization with the clock signal CLK, once the error bit [1] is generated, the error bit [1] is continuously generated. Probability is high. Then, the normal bit of [0] continues for a long time.

  This means that the error distribution of the random error signal b output from the random error signal generating device 3 is concentrated at a specific time position, and greatly deviates from the Poisson distribution existing in nature.

  The present invention has been made in view of such circumstances, and with a simple configuration, the error rate of the output random error signal can be matched with the specified error rate, and the error of the generated error can be matched. An object of the present invention is to provide a random error signal generator that further approximates the distribution to a Poisson distribution existing in nature.

  In order to solve the above problems, a random error signal generator of the present invention has a plurality of registers connected in series, and outputs a plurality of bit data stored in each register in parallel each time a clock is input. An M-sequence PN signal generation circuit, a data position replacement circuit that replaces the data positions of a plurality of bit data output in parallel from the PN signal generation circuit in synchronization with the clock, and the data position replacement by the data position replacement circuit A plurality of bit data is input at one end, the input bit data is taken as one numerical value, and when this numerical value is equal to or less than a reference value corresponding to the specified error rate input at the other end, an error bit is obtained. And a comparator for outputting a random error signal.

  In the random error signal generator configured as described above, a data position exchanging circuit is interposed between the PN signal generating circuit and the comparator. The data position replacement circuit replaces the data positions of a plurality of bit data output in parallel from the PN signal generation circuit in synchronization with the clock. As a result, the data position (digit position when regarded as a numerical value) of the parallel bit data output from the serially connected registers of the PN signal generation circuit changes greatly when input to the comparator.

  Therefore, since the arrangement of other bit data that has shifted the register at the same time when it is input to the comparator changes, the value determined by the data position at the input end of the comparator varies greatly each time a clock is input. The value on the PN signal generation circuit side is continuously set to the reference value that is set to an order of magnitude smaller than the value on the PN signal generation circuit side. It can be suppressed as much as possible below the value. Therefore, the error distribution of the random error signal can be further approximated by a Poisson distribution existing in nature.

  According to another aspect of the present invention, a random error signal generator includes a plurality of serially connected registers, and outputs a plurality of bit data stored in each register in parallel each time a clock is input. A signal generation circuit; a plurality of serially connected data position replacement circuits for switching data positions of a plurality of bit data output in parallel in synchronization with a clock from the PN signal generation circuit; and the plurality of serially connected data positions A plurality of bit data whose data positions have been switched by the replacement circuit is input to one end, the plurality of input bit data is taken as one numerical value, and this numerical value corresponds to the specified error rate input to the other end. And a comparator that outputs a random error signal that becomes an error bit when the value is less than or equal to the value.

  In the random error signal generator having such a configuration, since a plurality of eta position switching circuits connected in series are used, the data positions of the plurality of bit data output in parallel from the PN signal generating circuit are switched more randomly. . As a result, the numerical value composed of a plurality of bit data applied to the data position input to one end of the comparator changes more greatly than the previous numerical value. Therefore, the probability that error bits are continuously output from the comparator is reduced.

  A random error signal generator according to still another invention has a plurality of registers connected in series, and each time a clock is input, one M-sequence of outputs a plurality of bit data stored in each register in parallel. A plurality of PN signal generation circuits and a plurality of bit data outputted in parallel in synchronization with the clock from the one PN signal generation circuit, respectively, and a plurality of bit positions of the inputted bit data are switched in different patterns. Data position replacement circuit and a plurality of bit data whose data positions have been switched by each data position replacement circuit are input to one end, and the input bit data are taken as one numerical value, and this numerical value is input to the other end. Multiple comparators that output bit data that becomes error bits when the value is below the reference value corresponding to the specified error rate, and each A data buffer that temporarily stores the bit data output from the comparator as parallel bit data, and the parallel bit data stored in the data buffer is converted into one random error signal having a serially specified error rate and output. And a parallel-serial conversion circuit.

  In the random error signal generation device having such a configuration, the parallel bit data output from one PN signal generation circuit is input to a plurality of data position replacement circuits each having a different replacement pattern. Each parallel bit data output from each data position replacement circuit is compared with a reference value by a comparator and converted into one random error signal having a specified error rate by a parallel-serial conversion circuit.

  According to another aspect of the present invention, there is provided a random error signal generator having a plurality of serially connected registers, and each time a clock is input, a plurality of M-sequences for outputting a plurality of bit data stored in each register in parallel. A plurality of bit data output in parallel in synchronization with the clock from the PN signal generation circuit and the PN signal generation circuits in the plurality of PN signal generation circuits are respectively input, and the data positions of the input bit data are respectively determined. A plurality of data position replacement circuits that are replaced in different patterns, and a plurality of bit data whose data positions are replaced in each data position replacement circuit are input to one end, and the input plurality of bit data is taken as one numerical value, Bit data that becomes an error bit when this value is below the reference value corresponding to the specified error rate input to the other end A plurality of comparators that output data, a data buffer that temporarily stores bit data output from each comparator as parallel bit data, and the parallel bit data stored in the data buffer has a serially specified error rate. A parallel-serial conversion circuit that converts the signal into one random error signal and outputs the signal.

  In the random error signal generator configured as described above, the parallel bit data respectively output from the plurality of PN signal generation circuits is input to the plurality of data position replacement circuits having different replacement patterns. Therefore, it is possible to achieve the same effect as the previous invention.

  The random error signal generator according to another aspect of the invention has a plurality of registers connected in series, and outputs a plurality of bit data stored in each register in parallel each time a clock is input, and a different pattern from each other. A plurality of M-sequence PN signal generation circuits for generating the PN signal, and a plurality of bit data output in parallel in synchronization with the clock from each of the PN signal generation circuits in the plurality of PN signal generation circuits, respectively, A plurality of data position exchanging circuits for exchanging data positions of a plurality of input bit data, and a plurality of bit data in which the data positions are interchanged in each data position exchanging circuit are input to one end, and the plurality of input bit data As a single value, and this value is below the reference value corresponding to the specified error rate entered at the other end. Multiple comparators that output bit data that becomes error bits, a data buffer that temporarily stores the bit data output from each comparator as parallel bit data, and the parallel bit data stored in this data buffer are specified in series And a parallel-serial conversion circuit that converts and outputs one random error signal having an error rate.

  In the random error signal generator having such a configuration, the plurality of PN signal generators incorporated in the random error signal generator includes, for example, a means for changing a signal extraction register position with respect to the exclusive OR gate. By taking the above, the patterns of the output PN signals are different. Therefore, a numerical value formed from a plurality of bit data applied to one end of each comparator can be made even more random.

  According to another aspect of the present invention, the random error signal generator has a plurality of serially connected registers, and outputs a plurality of bit data stored in each register in parallel each time a clock is input. A plurality of M-sequence PN signal generation circuits whose initial data patterns are set to different data patterns, and a plurality of bits output in parallel from each PN signal generation circuit in the plurality of PN signal generation circuits in synchronization with the clock Each of the data is input, a plurality of data position replacement circuits for switching the data positions of the plurality of input bit data, and a plurality of bit data whose data positions are replaced by each data position replacement circuit are input to one end. Takes multiple input bit data as a single numerical value and inputs this numerical value to the other end A plurality of comparators that output bit data that becomes an error bit when it is equal to or less than a reference value corresponding to the specified error rate, a data buffer that temporarily stores bit data output from each comparator as parallel bit data, and A parallel-serial conversion circuit for converting the parallel bit data stored in the data buffer into one random error signal having a serially specified error rate and outputting the random error signal.

  In the random error signal generator configured as described above, a plurality of PN signal generator circuits incorporated in the random error signal generator are set in each of the serially connected registers at the time of activation of the random error signal generator. Different initial values are used. Therefore, a numerical value formed from a plurality of bit data applied to one end of each comparator can be made even more random.

  According to another aspect of the present invention, there is provided a random error signal generator having a plurality of serially connected registers, and each time a clock is input, a plurality of M-sequences for outputting a plurality of bit data stored in each register in parallel. A plurality of bit data output in parallel in synchronization with the clock from the PN signal generation circuit and the PN signal generation circuits in the plurality of PN signal generation circuits are respectively input, and the data positions of the input bit data are respectively determined. A plurality of data position replacement circuits that are replaced with different patterns as time elapses, and a plurality of bit data in which the data positions are replaced in each data position replacement circuit are input to one end. When this value is less than the reference value corresponding to the specified error rate input at the other end, A plurality of comparators that output bit data, a data buffer that temporarily stores the bit data output from each comparator as parallel bit data, and a serially specified error rate for the parallel bit data stored in the data buffer. And a parallel-to-serial conversion circuit that converts the random error signal into a single random error signal.

  In the random error signal generator configured as described above, all the PN signal generator circuits have the same configuration, but the replacement pattern of the data position change circuit changes with time. Even under such conditions, a numerical value formed from a plurality of bit data applied to one end of each comparator can be made even more random.

  The random error signal generator according to another invention has a plurality of registers connected in series, and outputs a plurality of bit data stored in each register in parallel each time a clock is input, and also connects the registers. A plurality of M-sequence PN signal generation circuits whose numbers are set to different values, and a plurality of bit data output in parallel from each PN signal generation circuit in the plurality of PN signal generation circuits in synchronization with the clock are input. A plurality of data position exchange circuits for exchanging data positions of a plurality of input bit data, and a plurality of bit data whose data positions are exchanged by each data position exchange circuit are input to one end, Bit data is taken as one numerical value, and this numerical value is below the reference value corresponding to the specified error rate input at the other end A plurality of comparators that output bit data that becomes error bits, a data buffer that temporarily stores the bit data output from each comparator as parallel bit data, and the parallel bit data stored in the data buffer in series A parallel-to-serial conversion circuit that converts the signal into one random error signal having a specified error rate and outputs the random error signal.

  In the random error signal generator configured as described above, the plurality of PN signal generator circuits incorporated in the random error signal generator have different register stages. When the number of register stages is different, the period of the PN signal is different, so that a numerical value formed from a plurality of bit data applied to one end of each comparator can be made even more random.

  In the present invention, a data position replacement circuit is provided for replacing the data positions of a plurality of parallel bit data output from the PN signal generation circuit. Therefore, the error rate of the output random error signal can be matched with the specified error rate, and the error distribution of the generated error can be further approximated by the Poisson distribution existing in nature.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of a random error signal generator 20 according to the first embodiment of the present invention. The same parts as those of the conventional random error signal generator shown in FIG.

As shown in FIG. 2, an M (longest) series PN signal generation circuit 6 incorporated in the random error signal generation apparatus 20 according to the first embodiment includes an m-stage register 7 and one or a plurality of exclusive It consists of an OR gate 8. When the clock signal CLK is applied from the external clock circuit 9 to each register 7, the PN signal generation circuit 6 outputs a PN signal having a cycle of (2 ^m −1) from the output terminal 10. Each time the clock signal CLK is input, the bit data stored in the m registers 7 are output in parallel.

In addition to the configuration shown in FIG. 2, the PN signal generation circuit 6 changes the register 7 that supplies the bit data d ₁ and d ₂ supplied to the exclusive OR gate 8 to another register 7. Is possible. The m pieces of bit data output in parallel from the PN signal generation circuit 6 are input to the data position replacement circuit 21.

  FIG. 3 is a circuit diagram of the data position replacement circuit 21. The m pieces of bit data output from each register 7 of the PN signal generation circuit 6 are input to m input terminals 22 of P1, P2,. The input terminals 22 of P1, P2,..., Pm and the output terminals 23 of Q1, Q2,..., Qm are connected by a printed wiring board 25 wired so as to have a predetermined connection pattern 24. Has been.

  For example, the input terminal 22 of P1 is connected to the output terminal 23 of Qm-1. The input terminal 22 of P2 is connected to the output terminal 23 of Q5. Therefore, the data positional relationship between P1 and P2 on the input side changes to the data positional relationship between Qm-1 and Q5 on the output side. In this manner, the data position replacement circuit 21 replaces the data positions of the m pieces of bit data input in parallel.

  The m pieces of parallel bit data whose data positions have been replaced by the data position replacement circuit 21 are applied to one input terminal (X terminal) of the comparator 26. The other input terminal (Y terminal) of the comparator 26 is supplied with a parallel m-bit reference value B that is input by the operator through the reference value setting circuit 27.

The comparator 26 takes in m pieces of parallel bit data applied to one input terminal (X terminal) as one numerical value C. Similarly, the parallel m-bit reference value B applied to the other input terminal (Y terminal) is also taken in as a numerical value. When the numerical value C taken from one input terminal (X terminal) is equal to or smaller than the reference value B taken from the other input terminal (Y terminal), the comparator 26 is a random bit that becomes an error bit of “1”. An error signal e ₁ is output.

Since the PN signal generation circuit 6 outputs m pieces of bit data in synchronization with the clock signal CLK, the bit rate of the random error signal e ₁ output from the comparator 26 is the bit rate (transmission of the clock signal CLK). Speed).

As described above, the reference value B is set corresponding to the error occurrence rate (error rate) E of the random error signal e ₁ output from the random error signal generator 20. For example, as shown in FIG. 4, when the error rate E is 0.004 (0.4%) and the value C that the X terminal can take is 1-1000, the reference value B is set to “4”. . Since the probability that the numerical value C is 4 or less is 4/1000, a random error signal e ₁ with an error rate E of 0.004 is obtained.

  The overall operation of the random error signal generator 20 of the first embodiment configured as described above will be described with reference to the time chart of FIG.

Similarly to the conventional random error signal generator 3 shown in FIG. 29, when a part of the PN signal of the period (2 ^m −1) of the PN signal generation circuit 6 is [... 0110000000000000 ...], and m is, for example, 10 (Cycle = 2 ^m −1 = 11023), when the m bit data in parallel output from each of the m registers 7 is [0000000], the numerical value A of the m (bit) data is [0]. In this case, even if the data position is replaced by the data position replacement circuit 21, the data does not change and maintains [0000000], so the numerical value C of the data applied to the X terminal of the comparator 26 remains “1”. It is. When the reference value B is [4], since the numerical value C ≦ reference value B, the output of the comparator 26 is the error bit [1].

  When the next clock signal CLK is input, the data in each register 7 is shifted one by one, so the m (bit) data in parallel becomes [1000000000], and the numerical value A of the m (bit) data is [ 1]. In this case, if the data position is switched by the data position replacement circuit 21, the data becomes “0000000010”, and the numerical value C of the data applied to the X terminal of the comparator 26 becomes “256”. Since the reference value B does not change with [4], the numerical value C> the reference value B, and the output of the comparator 26 is a normal bit of [0].

  Further, when the next clock signal CLK is input, the data in each register 7 is shifted one by one, so that m (= 10) bit data in parallel becomes [1100000000]. The numerical value A is [3]. When the data position is replaced by the data position replacement circuit 21, the data becomes [0000100010], and the numerical value C of the data applied to the X terminal of the comparator 26 is “272”. Since the reference value B does not change at [4], the numerical value C> the reference value B, and the output of the comparator 26 is a normal bit of [0].

  Further, when the next clock signal CLK is input, the data in each register 7 shifts one by one, so that the data of m bits in parallel becomes [011000000], and the data position replacement circuit 21 replaces the data position. Since the data is [1001000000], the numerical value C of the data applied to the X terminal of the comparator 26 is “9”. Since the reference value B does not change with [4], the numerical value C> the reference value B, and the output of the comparator 26 is a normal bit of [0].

  As described above, the data position in the plurality of parallel bit data output from each register 7 of the PN signal generation circuit 6 is replaced by the data position replacement circuit 21, so that the register 7 is simultaneously shifted when input to the comparator 26. Since the arrangement with the other bit data changes, the numerical value C determined by the data position of the input terminal (X terminal) of the comparator 26 varies greatly every time the clock CLK is input.

Therefore, since the signal is input to the other input terminal (Y terminal) of the comparator 26, the reference value B which is set to an order of magnitude smaller than the numerical value A on the PN signal generation circuit 6 side is continuously obtained. The numerical value C on the PN signal generation circuit 6 side can be suppressed as much as possible below the reference value B. Therefore, the error distribution of the random error signal e ₁ can be further approximated by a Poisson distribution existing in nature.

(Second Embodiment)
FIG. 5 is a block diagram showing a schematic configuration of a random error signal generator 20a according to the second embodiment of the present invention. The same parts as those of the random error signal generator 20 of the first embodiment shown in FIG.

  In the random error signal generating device 20a of the second embodiment, as shown in FIG. 6, 2 of the same configuration is provided between the PN signal generating circuit 6 and one input terminal (X terminal) of the comparator 26. The data position replacement circuits 21a and 21b are inserted in series.

  Therefore, the parallel m pieces of bit data (having the numerical value A) output from the respective registers 7 of the PN signal generating circuit 6 are changed in data position by the data position replacing circuit 21a in the previous stage, and the parallel data having the numerical value C It is changed to m bit data. Furthermore, the m bit data in parallel output from the data position replacement circuit 21b in the previous stage is changed in the data position in the data position replacement circuit 21b in the subsequent stage and changed to m bit data in parallel having the numerical value C ′. Is done. Then, m pieces of parallel bit data having the numerical value C ′ are applied to one input terminal (X terminal) of the comparator 26.

Accordingly, since the data positions of the plurality of bit data output in parallel from the PN signal generation circuit 6 are more randomly switched, a numerical value composed of a plurality of bit data input to one input terminal (X terminal) of the comparator 26. C ′ changes more greatly than the value in the previous clock CLK. Therefore, the probability that error bits “1” are continuously output from the comparator 26 is reduced. Therefore, the error distribution of the random error signal e ₂ output from the comparator 26 can be further approximated to a Poisson distribution.

(Third embodiment)
FIG. 7 is a block diagram showing a schematic configuration of a random error signal generator 20b according to the third embodiment of the present invention. The same parts as those of the random error signal generator 20 of the first embodiment shown in FIG.

  In the random error signal generation device 20b of the third embodiment, m bit data output from each register 7 of one PN signal generation circuit 6 is the data position of each input m bit data. Are input to the input terminals of k data position replacement circuits 21c that replace them in different patterns.

As shown in FIG. 8, the k data position replacement circuits 21 c have different connection patterns 24 of the printed wiring board 25 that connects the m input terminals 22 and the m output terminals 23. Therefore, the data arrangement (numerical value) of m bit data output from the output terminal 23 of the k data position replacement circuits 21c to which m bit data having the same data arrangement (numerical value A) is input is: Each of the k data position replacement circuits 21 changes to a different data array (numerical values Ca ₁ , Ca ₂ ,..., Ca _k ).

Each of m pieces of bit data (numerical values Ca ₁ , Ca ₂ ,..., Ca _k ) output from each of the k pieces of data position replacement circuits 21c is a comparator in the random error signal generator 20 of the first embodiment. 26 is input to one input terminal (X terminal) of the comparator 26 having the same configuration as that of the comparator 26. A parallel m-bit reference value B input by the operator through the reference value setting circuit 27 is input to the other input terminal (Y terminal) of each of the k comparators 26.

Each comparator 26 takes in m pieces of parallel bit data applied to one input terminal (X terminal) as one numerical value Ca. Similarly, the parallel m-bit reference value B applied to the other input terminal (Y terminal) is also taken in as a numerical value. Each comparator 26 has an error bit of “1” when the numerical value Ca taken from one input terminal (X terminal) is equal to or less than the reference value B taken from the other input terminal (Y terminal). Bit data g ₁ , g ₂ ,..., A _k are output. In this case, since different data arrays (numerical values Ca) are applied to one input terminal (X terminal) of each comparator 26 as a result, the output bit data g ₁ , g ₂ ,. _k becomes “1” error bits at different timings.

Bit data g ₁ , g ₂ ,..., G output from each comparator 26 in synchronization with the clock signal CLK
_k is temporarily stored in the data buffer 28 and then input to the parallel-serial conversion circuit 29 as parallel k-bit parallel data [g ₁ , g ₂ ,..., a _k ]. The parallel / serial conversion circuit 29 receives a clock signal CLK ₂ obtained by multiplying the frequency f _C (period T _C ) output from the clock circuit 9 by k times by the multiplication circuit 9.

The parallel-serial conversion circuit 29 converts parallel k-bit parallel data [g ₁ , g ₂ ,..., G _k ] into serial data having a frequency (k · f _C ) (period T _{C / k} ), thereby generating a random error. Output as signal e ₃ .

FIG. 9 is a time chart showing the overall operation of the random error signal generator 20b of the third embodiment configured as described above. The parallel m pieces of bit data output within one cycle T _C of the clock signal CLK are subjected to data position replacement and comparison with a reference value in parallel by the k data position replacement circuits 21c and the comparator 26. To be implemented. Individually, bit data g ₁ , g ₂ ,..., G _{k that} are error bits of “1” when the reference value B or less is generated are finally transmitted by the parallel-serial conversion circuit 29. speed is k times the basic clock signal CLK, the random error signal e ₃ of the high frequency of 30~40GHz for example optical communication frequency obtained.

Further, as described with reference to FIG. 26, an exclusive logical sum operation is performed on the random error signal e ₃ and the digital test signal a output from the test signal generation circuit 2 by the exclusive OR gate 4, and the signal is output. Becomes the test signal a ₁ .

Here, the exclusive OR operation is performed on the random error signal e ₃ output from the parallel-serial conversion circuit 29. The bit data g ₁ before being input to the parallel-serial conversion circuit 29, The output may be performed for each of g ₂ ,..., g _k .

Of course, in parallel, since replacement pattern 24 of the data array employs a different k data position replacement circuit 21c, to the specified value the error rate E in the random error signal e ₃ to be finally output In addition, the error distribution can be further approximated by a Poisson distribution existing in nature.

(Fourth embodiment)
FIG. 10 is a block diagram showing a schematic configuration of a random error signal generator 20c according to the fourth embodiment of the present invention. The same parts as those of the random error signal generator 20b of the third embodiment shown in FIG. 7 are denoted by the same reference numerals, and detailed description of the overlapping parts is omitted.

  In the random error signal generator 20c of the fourth embodiment, m registers 7 connected in series having the same configuration as the PN signal generator circuit 6 of the random error signal generator 20b of the third embodiment shown in FIG. In addition, k PN signal generation circuits 6 incorporating the exclusive OR gate 9 are provided. A common clock signal CLK from the clock circuit 9 is applied to the k PN signal generation circuits 6.

  Similarly to the random error signal generator 20b of the third embodiment of FIG. 7, the m pieces of parallel bit data output from each of the k pieces of PN signal generation circuits 6 are input m pieces of bit data data. The data is input to each input terminal (X terminal) of the k data position replacement circuits 21c whose positions are replaced with different connection patterns.

Each data position replacement circuit 21c individually replaces the data positions of the input parallel m pieces of bit data, and each comparator as each m pieces of bit data (numerical values Ca ₁ , Ca ₂ ,..., Ca _k ). 26 is applied to one input terminal (X terminal). A reference value B is applied from the reference value generating circuit 27 to the other input terminal (Y terminal) of each comparator 26.

Each comparator 26, numeric Ca _1, Ca ₂ of the taken from one input terminal (X terminal), ..., when Ca _k is less than or equal to the other input terminal (Y terminal) taken-from the reference value B, " Bit data g ₁ , g ₂ ,..., G _k that are error bits of “1” are output. Each bit data g ₁ , g ₂ ,..., G _k outputted from each comparator 26 passes through the data data buffer 28 and is converted into a frequency (k · f _C ) (period T _{C / k} ) by the parallel-serial conversion circuit 29. Are converted into serial data and output as a random error signal e ₄ .

  Therefore, the random error signal generator 20c of the fourth embodiment configured as described above can achieve substantially the same operational effects as the random error signal generator 20b of the third embodiment described above. .

  FIG. 11 shows the error distribution characteristics of the random error signal e3 obtained by the random error signal generator 20c of the fourth embodiment. The implementation conditions are as follows: the number of stages m = 16 of the register 7 of each PN signal generation circuit 6, the number of each PN signal generation circuit 6 and the data position replacement circuit 21, the number of comparators 26 (the number of parallels) k = 16, the specified error rate E = A sample size n = 1024 indicating the number of data of one measurement unit when measuring (counting) an error is 0.001. The horizontal axis indicates the number of errors existing in one measurement unit, and the vertical axis indicates the frequency of occurrence (occurrence frequency) of each error number. The experimental results shown by the bar graph were proved to approximate the Poisson distribution shown by the solid line.

  FIG. 12 shows the error distribution characteristics of the random error signal when the data position replacement circuit 21c is removed and the output of each PN signal generation circuit 6 is applied directly to each comparator 26 under the same conditions as in FIG. Compared to the error distribution in FIG. 11, it was confirmed that the error distribution was significantly different from the Poisson distribution. On the contrary, the present application can further approximate the error distribution to the Poisson distribution as compared with the prior art.

(Fifth embodiment)
FIG. 13 is a block diagram showing a schematic configuration of a random error signal generator 20d according to the fifth embodiment of the present invention. The same parts as those of the random error signal generator 20c of the fourth embodiment shown in FIG. 10 are denoted by the same reference numerals, and detailed description of the overlapping parts is omitted.

  In the random error signal generation device 20d of the fifth embodiment, the k data position replacement circuits 21 all have the same configuration as the data position replacement circuit 21 shown in FIG. However, each of the k PN signal generation circuits 6a that individually send m data bits in parallel to the k data position replacement circuits 21 has a different configuration. Specifically, PN signals having different patterns are generated.

FIG. 14 is a circuit diagram of each PN signal generation circuit 6a. The same parts as those in FIG. 2 are denoted by the same reference numerals. In the PN signal generation circuit 6a, a gate 32 is interposed between the output terminals of the m registers 7 and the exclusive OR gate 8. Each gate 32 is controlled to be opened and closed by a gate signal G = [j ₁ , j ₂ ,..., J _k ]. By specifying the contents of the gate signal G, it is possible to specify which register 7 bit data is input to the exclusive OR gate 8. For example, the connection configuration in FIG. 15A or the connection configuration in FIG. 15B can be arbitrarily set. In this way, by changing the connection configuration, the signal pattern of the (2 ^m −1) period of the PN signal output from the output terminal 10 of the PN signal generation circuit 6a can be arbitrarily changed.

In FIG. 13, the signal patterns of the PN signals of the k PN signal generation circuits 6 a are set to patterns different from each other by the gate signals G ₁ , G ₂ ,..., G _k from the PN pattern control unit 31. . As a result, the m pieces of bit data (numerical value A) output in parallel with the clock signal CLk from the m registers 7 of each of the k PN signal generation circuits 6a do not coincide with each other and have different values. (Numerical values A ₁ , A ₂ ,..., A _k ).

The data position changing circuit 21 having the same configuration to which m pieces of parallel bit data having different values (numerical values A ₁ , A ₂ ,..., A _k ) output from the respective PN signal generation circuits 6a are input. The data position of the bit data is switched and applied to one input terminal (X terminal) of the corresponding comparator 26 as new parallel m pieces of bit data (numerical values Cb ₁ , Cb ₂ ,..., Cb _k ). A reference value B is applied from the reference value generating circuit 27 to the other input terminal (Y terminal) of each comparator 26.

Each of the comparators 26, when the numerical values Cb ₁ , Cb ₂ ,..., Cb _{k taken} from one input terminal (X terminal) are less than or equal to the reference value B taken from the other input terminal (Y terminal), Bit data g ₁ , g ₂ ,..., G _k that are error bits of “1” are output. Each bit data g ₁ , g ₂ ,..., G _k outputted from each comparator 26 passes through the data data buffer 28 and is converted into a frequency (k · f _C ) (period T _{C / k} ) by the parallel-serial conversion circuit 29. Are converted into serial data and output as a random error signal e ₅ .

  Therefore, the random error signal generation device 20d of the fifth embodiment configured as described above can achieve substantially the same operational effects as the random error signal generation device 20c of the fourth embodiment described above. .

FIG. 16 is a time chart showing the overall operation of the random error signal generator 20d of the fifth embodiment configured as described above. m pieces of parallel bit data having different numerical values (A ₁ , A ₂ ,..., A _k ) output from each of the k PN signal generation circuits 6 a within one cycle T _C of the clock signal CLK. In parallel, data positions are replaced by k data position replacement circuits 21 and comparators 26 of the same configuration and compared with a reference value. Individually, bit data g ₁ , g ₂ ,..., G _{k that} are error bits of “1” when the reference value B or less is generated are finally transmitted by the parallel-serial conversion circuit 29. A high-frequency random error signal e ₅ whose speed is k times that of the basic clock signal is obtained.

Further, as described with reference to FIG. 26, an exclusive logical sum operation is performed on the random error signal e ₅ and the digital test signal a output from the test signal generation circuit 2 by the exclusive OR gate 4, and the signal is output. Becomes the test signal a ₁ .

Here, the exclusive OR operation is performed on the random error signal e ₅ output from the parallel-serial conversion circuit 29. The bit data g ₁ before being input to the parallel-serial conversion circuit 29, The output may be performed for each of g ₂ ,..., g _k .

(Sixth embodiment)
FIG. 17 is a block diagram showing a schematic configuration of a random error signal generator 20e according to the sixth embodiment of the present invention. The same parts as those of the random error signal generator 20d of the fifth embodiment shown in FIG. 13 are denoted by the same reference numerals, and detailed description of the overlapping parts is omitted.

  In the random error signal generation device 20e of the sixth embodiment, k PN signal generation circuits 6b having different configurations for individually transmitting m data bits in parallel are configured as shown in FIG. 18, for example. ing. In FIG. 18, the same parts as those of the PN signal generation circuit 6a of the fifth embodiment shown in FIG.

In the PN signal generation circuit 6b, a gate 32 is interposed between the output terminals of the m registers 7 and the exclusive OR gate 8. Each gate 32 is controlled to be opened and closed by a gate signal G = [j ₁ , j ₂ ,..., J _k ].

Further, in the PN signal generation circuit 6b, an input terminal 34 is provided in the first register 7 in the first register 7 of the m registers 7 connected in series. The input terminal 34 is supplied with initial values (m pieces of bit data d ₁ , d ₂ , d ₃ ,..., D _m ) from the PN initial value setting unit 33 shown in FIG.

Specifically, in the initial setting process when the random error signal generator 20e is turned on, the clock circuit 9 is activated and m pieces of bit data d ₁ , d ₂ , d ₃ ,. than to continue to apply in order to d _m to the input terminal 34, for example, an arbitrary initial value (the initial pattern) into m each register 7, as shown in FIG. 19 (a) [0110 ... 01 ] a configurable It is.

  In the random error signal generator 20e of the sixth embodiment, as shown in FIGS. 19A and 19B, the PN initial value setting unit 33 differs from the k PN signal generators 6b. Set the initial value of the pattern. At the same time, the PN pattern control unit 32 realizes different PN signal patterns by configuring the k PN signal generation circuits 6b to have different connection configurations.

When the random error signal generator 20e according to the sixth embodiment is started when the above initial setting processing is completed, the random error signal generator 20e according to the sixth embodiment is output from each PN signal generator circuit 6b in synchronization with the clock signal CLK output from the clock circuit 9. The numerical values (Ac ₁ , Ac ₂ ,..., Ac _k ) of the m pieces of parallel bit data can be surely made different.

As a result, the numerical values (Cc ₁ , Cc ₂ ,..., Cc _k ) of the m pieces of parallel bit data output from the data position replacement circuits 21 having the same configuration can be reliably made different. Therefore, it is possible to further approximate the error distribution of the random error signal e ₆ output from the final parallel-serial conversion circuit 29 to a Poisson distribution.

Further, as described with reference to FIG. 26, an exclusive logical sum operation is performed on the random error signal e ₆ and the digital test signal a output from the test signal generation circuit 2 by the exclusive OR gate 4, and the signal is output. Becomes the test signal a ₁ .

Here, the exclusive OR operation is performed on the random error signal e ₆ output from the parallel-serial conversion circuit 29. The bit data g ₁ before being input to the parallel-serial conversion circuit 29, The output may be performed for each of g ₂ ,..., g _k .

(Seventh embodiment)
FIG. 20 is a block diagram showing a schematic configuration of a random error signal generator 20f according to the seventh embodiment of the present invention. The same parts as those of the random error signal generator 20c of the fourth embodiment shown in FIG. 10 are denoted by the same reference numerals, and detailed description of the overlapping parts is omitted.

  In the random error signal generator 20f of the seventh embodiment, each of the k data position replacement circuits 21d is configured as shown in FIG. Other configurations are almost the same as those of the random error signal generator 20c of the fourth embodiment shown in FIG.

  21, m bit data output from each register 7 of the PN signal generation circuit 6 are input to m input terminals 22 of P1, P2,. The P1, P2,..., Pm input terminals 22 and the Q1, Q2,..., Qm output terminals 23 are connected via a switching circuit network 35. The switching network 35 connects the input terminals 22 of P1, P2,..., Pm and the output terminals 23 of Q1, Q2,.

A plurality of connection patterns are stored in advance in the switching control unit 36 constituted by a small computer element, and is stored every time a clock having a cycle T _C of the clock signal CLK is input from the clock circuit 9. Each connection pattern of the plurality of connection patterns is set in the switching circuit network 35 in order.

  Accordingly, each data position exchanging circuit 21d synchronizes with the clock signal CLK and sets the data positions of the m pieces of parallel bit data output from each PN signal generation circuit 6 for each clock signal CLK, that is, with the passage of time. Switch to a changing data position.

In the random error signal generation device 20f of the seventh embodiment configured as described above, the k PN signal generation circuits 6 have the same configuration, but the k data position replacement circuits 21d have a connection (replacement) pattern. Changes over time. Even under such conditions, each numerical value (Cd ₁ , Cd ₂ ,..., Cd _k ) formed from a plurality of bit data applied to one end of each comparator 26 can be made even more random. Therefore, the error distribution of the random error signal e ₇ output from the final parallel / serial conversion circuit 29 can be further approximated to a Poisson distribution.

Further, as described with reference to FIG. 26, this random error signal e ₇ and the digital test signal a output from the test signal generation circuit 2 are subjected to an exclusive logical sum operation by the exclusive OR gate 4 and output. Becomes the test signal a ₁ .

Here, the exclusive OR operation is performed on the random error signal e ₇ output from the parallel-serial conversion circuit 29. The bit data g ₁ before being input to the parallel-serial conversion circuit 29, The output may be performed for each of g ₂ ,..., g _k .

(Eighth embodiment)
FIG. 22 is a block diagram showing a schematic configuration of a random error signal generator 20g according to the eighth embodiment of the present invention. The same parts as those of the random error signal generator 20d of the fifth embodiment shown in FIG. 13 are denoted by the same reference numerals, and detailed description of the overlapping parts is omitted.

In the random error signal generation device 20g of the eighth embodiment, the k PN signal generation circuits 6c have different numbers of registers 7 (the number of components m) connected in series as shown in FIG. Therefore, the period (2 ^m −1) of each PN signal created by each PN signal generation circuit 6c is different. Furthermore, the number m of parallel bit data output from each register 7 of each PN signal generation circuit 6c changes.

  Therefore, as shown in FIG. 24, the number of input terminals 22 and the number of output terminals 23 in each data position replacement circuit 21e to which m pieces of parallel bit data output from each PN signal generation circuit 6c are input. Are set to different values so as to match the number m of parallel bit data output from each register 7 of each PN signal generation circuit 6c.

  Further, as shown in FIG. 25, the number of input data at one input terminal (X terminal) of each comparator 26a to which m pieces of parallel bit data output from each data position replacement circuit 21e are input is as follows. The number m of parallel bit data output from the data position replacement circuit 21e is set.

In the random error signal generator 20g of the eighth embodiment configured as described above, the plurality of PN signal generators 6c incorporated in the random error signal generator 20g have different values for the number of stages m of the register 7. Is set. The difference in the number of stages m of the register 7 is that the period (2 ^m -1) of the PN signal is different, so that a numerical value (Ce ₁₎ formed from a plurality of bit data applied to one end (X terminal) of each comparator 26a. , Ce ₂ ,..., Ce _k ) can be made even more random. Therefore, the error distribution of the random error signal e ₈ output from the final parallel / serial conversion circuit 29 can be further approximated to a Poisson distribution.

Further, as described with reference to FIG. 26, an exclusive logical sum operation is performed on the random error signal e ₈ and the digital test signal a output from the test signal generation circuit 2 by the exclusive OR gate 4, and the signal is output. Becomes the test signal a ₁ .

Here, the exclusive OR operation is performed on the random error signal e ₈ output from the parallel-serial conversion circuit 29, but each bit data g ₁ before being input to the parallel-serial conversion circuit 29, The output may be performed for each of g ₂ ,..., g _k .

  The present invention is not limited to the first to eighth embodiments described above. It is also possible to appropriately combine the technical configurations described in the first to eighth embodiments.

1 is a block diagram showing a schematic configuration of a random error signal generator according to a first embodiment of the present invention. Circuit diagram of a PN signal generation circuit incorporated in the random error signal generation device of the first embodiment Circuit diagram of a data position replacement circuit incorporated in the random error signal generator of the first embodiment Time chart showing the overall operation of the random error signal generator of the first embodiment The block diagram which shows schematic structure of the random error signal generator concerning 2nd Embodiment of this invention. Circuit diagram of two data position replacement circuits incorporated in the random error signal generator of the second embodiment The block diagram which shows schematic structure of the random error signal generator concerning 3rd Embodiment of this invention. Circuit diagram of each data position replacement circuit incorporated in the random error signal generator of the third embodiment Time chart showing the overall operation of the random error signal generator of the third embodiment The block diagram which shows schematic structure of the random error signal generator concerning 4th Embodiment of this invention. Error distribution characteristic diagram of random error signal actually created by the random error signal generator of the fourth embodiment Error distribution characteristic diagram of actually created random error signal when the data position replacement circuit is removed from the random error signal generator of the fourth embodiment The block diagram which shows schematic structure of the random error signal generator concerning 5th Embodiment of this invention. Circuit diagram of a PN signal generation circuit incorporated in the random error signal generation device of the fifth embodiment Explanatory drawing of the structure of the PN signal generation circuit incorporated in the random error signal generator of the fifth embodiment Time chart showing the overall operation of the random error signal generator of the fifth embodiment The block diagram which shows schematic structure of the random error signal generator concerning 6th Embodiment of this invention. Circuit diagram of a PN signal generation circuit incorporated in the random error signal generation device of the sixth embodiment Explanatory drawing of the structure of the PN signal generation circuit incorporated in the random error signal generation device of the sixth embodiment The block diagram which shows schematic structure of the random error signal generator concerning 7th Embodiment of this invention. Circuit diagram of each data position replacement circuit incorporated in the random error signal generator of the seventh embodiment The block diagram which shows schematic structure of the random error signal generator concerning 8th Embodiment of this invention. Explanatory drawing of the structure of the PN signal generation circuit incorporated in the random error signal generation device of the eighth embodiment Circuit diagram of each data position replacement circuit incorporated in the random error signal generator of the eighth embodiment The figure which shows each comparator incorporated in the random error signal generator of the same 8th Embodiment The figure which shows schematic structure of the test apparatus incorporating the conventional random error signal generator. The block diagram which shows schematic structure of the conventional random error signal generator Circuit diagram of PN signal generation circuit incorporated in the conventional random error signal generator Time chart showing the overall operation of the conventional random error signal generator

Explanation of symbols

  6, 6a, 6b, 6c... PN signal generation circuit, 9... Clock circuit, 20, 20a, 20b, 20c, 20d, 20e, 20f, 20g ... random error signal generators, 21, 21a, 21b, 21c, 21d, 21e: Data position replacement circuit, 22: Input terminal, 23: Output terminal, 24 ... Connection pattern, 25 ... Printed wiring board, 26, 26a ... Comparator, 27 ... Reference value generation circuit, 28 ... Data buffer, 29 ... Parallel Serial conversion circuit, 30 ... multiplier, 31 ... PN pattern control unit, 32 ... gate, 33 ... PN initial value setting unit, 34 ... input terminal, 35 ... switching network, 36 ... switching control unit

Claims (8)

An M-sequence PN signal generation circuit (6) having a plurality of registers connected in series and outputting a plurality of bit data stored in each register in parallel each time a clock is input;
A data position exchange circuit (21) for exchanging data positions of a plurality of bit data output in parallel from the PN signal generation circuit in synchronization with the clock;
A plurality of bit data whose data positions are switched by this data position exchanging circuit is inputted to one end, the plurality of inputted bit data is taken as one numerical value, and this numerical value is inputted to the designated error rate inputted to the other end. A random error signal generator comprising: a comparator (26) that outputs a random error signal that becomes an error bit when it is equal to or less than a corresponding reference value. An M-sequence PN signal generation circuit (6) having a plurality of registers connected in series and outputting a plurality of bit data stored in each register in parallel each time a clock is input;
A plurality of serially connected data position replacement circuits (21a, 21b) for switching data positions of a plurality of bit data output in parallel from the PN signal generation circuit in synchronization with the clock;
A plurality of bit data whose data positions are switched by a plurality of data position switching circuits connected in series is input to one end, the plurality of input bit data is taken as one numerical value, and this numerical value is input to the other end. And a comparator (26) for outputting a random error signal that becomes an error bit when the value is equal to or less than a reference value corresponding to the designated error rate. One M-sequence PN signal generation circuit (6) having a plurality of registers connected in series and outputting a plurality of bit data stored in each register in parallel each time a clock is input;
A plurality of bit data output in parallel from the one PN signal generation circuit in synchronization with the clock are respectively input, and a plurality of data position replacement circuits that replace the data positions of the input bit data in different patterns ( 21c)
A plurality of bit data whose data positions have been replaced by each data position replacement circuit is input to one end, the input bit data is taken as one numerical value, and this numerical value is input to the other end. A plurality of comparators (26) for outputting bit data to be error bits when the reference value is equal to or lower than a reference value corresponding to
A data buffer (28) for temporarily storing bit data output from each of the comparators as parallel bit data;
Random error signal generation comprising: a parallel-serial conversion circuit (29) for converting parallel bit data stored in the data buffer into one random error signal having a serial specified error rate and outputting the random error signal apparatus. A plurality of M-series PN signal generation circuits (6) each having a plurality of registers connected in series and outputting a plurality of bit data stored in each register in parallel each time a clock is input;
In the plurality of PN signal generation circuits, a plurality of bit data outputted in parallel from each PN signal generation circuit in synchronization with the clock are respectively inputted, and a plurality of bit positions of the inputted plurality of bit data are exchanged in different patterns. Data position replacement circuit (21a) of
A plurality of bit data whose data positions have been replaced by each data position replacement circuit is input to one end, the input bit data is taken as one numerical value, and this numerical value is input to the other end. A plurality of comparators (26) for outputting bit data to be error bits when the reference value is equal to or lower than a reference value corresponding to
A data buffer (28) for temporarily storing bit data output from each of the comparators as parallel bit data;
Random error signal generation comprising: a parallel / serial conversion circuit (29) for converting parallel bit data stored in the data buffer into one random error signal having a serial specified error rate and outputting the random error signal apparatus. A plurality of M-series PN signals that have a plurality of registers connected in series and output a plurality of bit data stored in each register in parallel each time a clock is input, and generate PN signals of different patterns Generating circuit (6a);
In the plurality of PN signal generation circuits, a plurality of bit data output in parallel from each PN signal generation circuit in synchronization with the clock are respectively input, and a plurality of data position replacements for exchanging data positions of the plurality of input bit data respectively. A circuit (21);
A plurality of bit data whose data positions have been replaced by each data position replacement circuit is input to one end, the input bit data is taken as one numerical value, and this numerical value is input to the other end. A plurality of comparators (26) for outputting bit data to be error bits when the reference value is equal to or lower than a reference value corresponding to
A data buffer (28) for temporarily storing bit data output from each of the comparators as parallel bit data;
Random error signal generation comprising: a parallel / serial conversion circuit (29) for converting parallel bit data stored in the data buffer into one random error signal having a serial specified error rate and outputting the random error signal apparatus. It has a plurality of registers connected in series, and each time a clock is input, it outputs a plurality of bit data stored in each register in parallel, and the initial data patterns for the plurality of registers are set to different data patterns. A plurality of M-sequence PN signal generation circuits (6b);
In the plurality of PN signal generation circuits, a plurality of bit data output in parallel from each PN signal generation circuit in synchronization with the clock are respectively input, and a plurality of data position replacements for exchanging data positions of the plurality of input bit data respectively. A circuit (21);
A plurality of bit data whose data positions have been replaced by each data position replacement circuit is input to one end, the input bit data is taken as one numerical value, and this numerical value is input to the other end. A plurality of comparators (26) for outputting bit data to be error bits when the reference value is equal to or lower than a reference value corresponding to
A data buffer (28) for temporarily storing bit data output from each of the comparators as parallel bit data;
Random error signal generation comprising: a parallel / serial conversion circuit (29) for converting parallel bit data stored in the data buffer into one random error signal having a serial specified error rate and outputting the random error signal apparatus. A plurality of M-series PN signal generation circuits (6) each having a plurality of registers connected in series and outputting a plurality of bit data stored in each register in parallel each time a clock is input;
A plurality of bit data output in parallel from each of the PN signal generation circuits in the plurality of PN signal generation circuits is input in parallel, and the data positions of the plurality of input bit data are changed with time. A plurality of data position exchanging circuits (21d) for exchanging with different patterns;
A plurality of bit data whose data positions have been replaced by each data position replacement circuit is input to one end, the input bit data is taken as one numerical value, and this numerical value is input to the other end. A plurality of comparators (26) for outputting bit data to be error bits when the reference value is equal to or lower than a reference value corresponding to
A data buffer (28) for temporarily storing bit data output from each of the comparators as parallel bit data;
Random error signal generation comprising: a parallel / serial conversion circuit (29) for converting parallel bit data stored in the data buffer into one random error signal having a serial specified error rate and outputting the random error signal apparatus. Each of the plurality of registers connected in series outputs a plurality of bit data stored in each register in parallel each time a clock is input, and a plurality of M whose connection numbers of the registers are set to different values. A series of PN signal generation circuits (6c);
In the plurality of PN signal generation circuits, a plurality of bit data output in parallel from each PN signal generation circuit in synchronization with the clock are respectively input, and a plurality of data position replacements for exchanging data positions of the plurality of input bit data respectively. A circuit (21e);
A plurality of bit data whose data positions have been replaced by each data position replacement circuit is input to one end, the input bit data is taken as one numerical value, and this numerical value is input to the other end. A plurality of comparators (26a) for outputting bit data that becomes an error bit when the reference value is equal to or less than a reference value corresponding to
A data buffer (28) for temporarily storing bit data output from each of the comparators as parallel bit data;
Random error signal generation comprising: a parallel / serial conversion circuit (29) for converting parallel bit data stored in the data buffer into one random error signal having a serial specified error rate and outputting the random error signal apparatus.

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