CN115603766A

CN115603766A - System and method for cyclic modulation coding of medium wave transmitter based on FPGA

Info

Publication number: CN115603766A
Application number: CN202211279862.3A
Authority: CN
Inventors: 王明伟; 王峄铭; 程辉; 刘国庆; 卢建平; 宿晓盼; 卢烤; 朱友林; 曾凡锦; 徐华辉; 李伟; 陈晋; 张彤; 吴钰莹; 丁懿爽; 白建军; 陶海峰; 葛锐
Original assignee: Shaanxi University of Science and Technology
Current assignee: Shaanxi University of Science and Technology
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2023-01-13
Also published as: GB202305965D0; GB2623608A

Abstract

The application discloses a system and a method for cyclically modulating and coding a medium wave transmitter based on FPGA, wherein the system comprises a plurality of FPGA chips which are electrically connected in sequence, and each FPGA chip is provided with a large-cycle control module, a small-cycle control module and a power amplifier control module. The system can be deployed in a plurality of FPGA chips or a single FPGA, only a small amount of pin resources are needed for each FPGA, and the cost of applying the FPGA-based 10KW all-solid-state medium wave transmitter cyclic modulation coding system to a cyclic modulation coding link of an all-solid-state medium wave transmitter of more than 100KW is reduced; secondly, the data output delay of the system is 8-10 system clock cycles, and is irrelevant to the number of power amplifier modules to be controlled by the system, so that the requirement on the system clock frequency is reduced.

Description

FPGA-based medium wave transmitter cyclic modulation coding system and method

Technical Field

The application relates to the technical field of digital circuits, in particular to a system and a method for cyclic modulation coding of a medium wave transmitter based on an FPGA.

Background

With the rapid development of broadcasting industry, china's medium wave broadcasting transmission equipment tends to be all-solid-state digitalized. The original electronic tube class B plate tuner is being eliminated gradually, and is substituted by all-solid-state PDM and DAM medium wave broadcast transmitters, particularly DAM digital amplitude modulation technology can be widely applied.

The cyclic modulation coding circuit is an important component of the DAM medium wave transmitter, and a 12-bit data signal from an audio channel, namely a binary audio code, is converted into an on/off control signal by the cyclic modulation coding circuit to perform an on/off operation on an RF module in a power amplification stage of the transmitter.

The existing 10KW all-solid-state medium wave transmitter cyclic modulation coding system based on the FPGA is deployed in an FPGA chip, 48 power amplifier modules need to be controlled by the system, the working frequency of the system is usually 80 MHz-100 MHz, and the output delay of the system and the number of pins of the FPGA needed by the system are positively correlated with the number of the controlled power amplifier modules. In a cyclic modulation coding link of an all-solid-state medium wave transmitter with the power consumption of more than 100KW, 208 power amplifier modules are controlled in the cyclic modulation coding link, if an original 10KW all-solid-state medium wave transmitter cyclic modulation coding system is adopted, only the number of the power amplifier modules controlled by the system is modified, and the original system is deployed in a single FPGA chip, so that the requirement that the single FPGA chip has more than 400 available pin resources is met, and the more abundant the pin resources of the single FPGA chip at the same level are, the higher the price is, and the higher the cost is; secondly, the output delay of the original system is positively correlated with the number of the controlled power amplifier modules, so that the output delay is increased to 3 to 4 times of the original delay, and the working clock frequency required by the corresponding system is also increased by 3 to 4 times. Moreover, based on the above-mentioned defects, the method of using the shift register to balance the usage rate of the power amplifier module in the original system is no longer effective.

Disclosure of Invention

The embodiment of the application provides a cyclic modulation coding system and method of a medium wave transmitter based on an FPGA (field programmable gate array), which are used for solving the problems of high cost, increased delay and increased requirement on a working clock in the prior art that the cyclic modulation coding system of the 10KW all-solid-state medium wave transmitter based on the FPGA is applied to the cyclic modulation coding link of the all-solid-state medium wave transmitter more than 100 KW.

On the one hand, the embodiment of the application provides a medium wave transmitter cyclic modulation coding system based on FPGA, including a plurality of FPGA chips that are connected electrically in proper order, all have in every FPGA chip:

the large-cycle control module is used for determining the actual number of the conducted power amplifiers of each FPGA chip according to the input binary audio codes and the number of the FPGA chips;

the small-cycle control module is used for generating periodic pulses and counting the pulses to obtain corresponding small-cycle count values;

power amplifier control module includes:

the 1 counting submodule is used for accumulating the input power amplifier state codes to obtain the number of normal power amplifiers;

the correction amount calculation submodule is used for determining corresponding correction amounts according to the number B of power amplifiers which are input by other FPGA chips and are required to be additionally closed, the number A of power amplifiers which are required to be additionally opened and the number of conducted power amplifiers, and outputting the number B0 of power amplifiers which are required to be additionally closed and the number A0 of power amplifiers which are required to be additionally opened to other FPGA chips;

the first cyclic mapping submodule is used for carrying out multi-path selection on the input cyclic shift data according to the small cyclic count value to obtain corresponding cyclic shift result data;

the cancellation 1 submodule is used for performing code conversion on the cyclic shift result data, determining the number ND of power amplifiers needing to be closed according to the number of normal power amplifiers and the correction quantity, and performing multi-path selection on the cyclic shift result data after code conversion according to the number ND of the power amplifiers to obtain a corresponding output result;

and the second cyclic mapping submodule is used for carrying out cyclic mapping on the output result to obtain a corresponding power amplifier control signal.

On the other hand, the embodiment of the application provides a cyclic modulation coding method of a medium wave transmitter based on an FPGA, which comprises the following steps:

determining the actual conducting power amplifier number of each FPGA chip according to the input binary audio code and the number of the FPGA chips;

generating periodic pulses and counting the pulses to obtain corresponding small-cycle count values;

accumulating the input power amplifier state codes to obtain the number of normal power amplifiers;

determining corresponding correction amount according to the number B of power amplifiers which are input by other FPGA chips and are to be additionally closed, the number A of power amplifiers which are to be additionally opened and the number of conducting power amplifiers, and outputting the number B0 of power amplifiers which are to be additionally closed and the number A0 of power amplifiers which are to be additionally opened to other FPGA chips;

performing multi-path selection on the input cyclic shift data according to the small cyclic count value to obtain corresponding cyclic shift result data;

performing code conversion on the cyclic shift result data, determining the number ND of power amplifiers needing to be closed according to the number of normal power amplifiers and the correction amount, and performing multi-path selection on the cyclic shift result data after code conversion according to the number ND of power amplifiers to obtain a corresponding output result;

and circularly mapping the output result to obtain a corresponding power amplifier control signal.

The system and the method for cyclically modulating and coding the medium wave transmitter based on the FPGA have the following advantages:

1. the FPGA chip can be deployed in a plurality of FPGA chips or a single FPGA, only 176 pin resources are needed for each FPGA, and the total cost of the FPGA chip with a small number of pins is smaller than that of the single FPGA chip with the same number of pins.

2. The data output delay is 8-10 system clock cycles, and is irrelevant to the number of power amplifier modules to be controlled by the system, so that the required system clock frequency can be reduced to 5-10 MHz, and the communication among a plurality of FPGA chips is facilitated.

3. The ratio of the standard deviation of the utilization rate of each power amplifier module to the average utilization rate of the utilization rates of the power amplifier modules is smaller than 1 per thousand, and the original method for using the circular shift register is replaced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic composition diagram of a cyclic modulation coding system of a medium wave transmitter based on an FPGA according to an embodiment of the present application;

fig. 2 is a block diagram of a single FPGA chip in a cyclic modulation coding system according to an embodiment of the present disclosure;

FIG. 3 is a block diagram of a structure of a meter 1 submodule provided in an embodiment of the present application;

fig. 4 is a block diagram of a structure of a cyclic mapping submodule provided in an embodiment of the present application;

FIG. 5 is a schematic diagram illustrating operation of a circular mapping submodule provided in an embodiment of the present application;

fig. 6 is a block diagram of a cancellation 1 sub-module provided in the embodiment of the present application;

fig. 7 is a state transition diagram of a cyclic code modulation control state machine according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 1-7 are schematic diagrams illustrating a cyclic modulation coding system of an FPGA-based medium wave transmitter according to an embodiment of the present application. The embodiment of the application provides a medium wave transmitter cyclic modulation coding system based on FPGA, including a plurality of FPGA chips that connect electrically in proper order, all have in every FPGA chip:

the large-cycle control module is used for determining the actual conducting power amplifier number of each FPGA chip according to the input binary audio codes and the number of the FPGA chips;

power amplifier control module includes:

Exemplarily, the system in fig. 1 can be used for a 100KW all-solid-state medium wave transmitter, 3 FPGA chips are used to form the system, and the 3 FPGA chips are connected end to end by using signal lines of "the number BX of power amplifiers to be additionally turned off" and "the number AX of power amplifiers to be additionally turned on". The 64-Bit power amplifier state code, the 8-Bit binary audio code, the system clock Clk and the data clock are shared by 3 FPGA chips, and the model of the adopted FPGA chip can be EP1C6Q240C8N. After the FPGA chip is adopted, a system clock is fixed to be 10MHz, a correct power amplifier control signal is required to be output according to an 8Bit binary audio code within a data clock period (500-800 KHz), and a driving fault power amplifier module with the power amplifier control signal error is avoided; the utilization rate of each power amplifier is required to be balanced, and the utilization rate of each power amplifier is balanced as much as possible.

According to the above requirements, the system is respectively deployed in 3 FPGA chips, and the 3 FPGA chips are connected end to end by using signal lines of "number of power amplifiers to be additionally turned off (6)" and "number of power amplifiers to be additionally turned on (6)", system clocks of the 3 FPGA chips are independent from each other but all are 10MHz, wherein signals shared by the 3 FPGA chips are 64Bit power amplifier status codes, 8Bit binary audio codes, and data clocks. The A/D converter converts the analog audio signal into a 12-Bit digital signal, the FPGA chip extracts 8 bits from the analog audio signal as an 8-Bit binary audio code, a sampling clock of the A/D converter is used as a data clock, and then the 8-Bit binary audio code and the data clock are connected into 3 FPGA chips through a flat cable for processing. In the process of system testing, any 1-10 pins in 64Bit power amplifier state are given low level to simulate power amplifier failure, and the system can avoid the failed power amplifier and always output correct power amplifier control signals. The external equipment counts the power amplifier control signals, and the result shows that along with the increase of the operation time, the ratio of the standard deviation of the utilization rate of the power amplifier module to the average utilization rate is gradually reduced, and when the operation time exceeds 10s, the ratio is less than 1 per thousand.

The principle of the large-cycle control module is that 8-Bit binary audio codes are divided by the number of FPGA chips used in a modulation coding link, a quotient is used as the actual conducting power amplifier number of each FPGA, and a remainder is distributed to any FPGA chip, so that the actual conducting power amplifier number of each FPGA chip is the large-cycle-quantity Big in figure 2.

The small circulation control module is internally provided with a circulation control logic, the circulation control logic consists of a counter and a pulse generation submodule, and the pulse generation submodule generates a pulse signal with the length of one system clock period at regular intervals, such as 1-5 seconds; after the counter receives the pulse signal, accumulating 1, and taking the accumulated value as a small-cycle count value; after a certain value, for example 64, is accumulated, a reset process is performed, for example, to 0. The small circulation count value of the counter is a small circulation quantity L, and the small circulation quantity controls the switching circulation of the power amplifier control module in a single FPGA.

The power amplifier control module is used for realizing the core function of the system, wherein the block diagram of the meter 1 submodule is shown in fig. 3. In the figure, bit 0 to Bit 63 are input 64Bit power amplifier state codes, bit x is 0 and represents power amplifier faults, bit x is 1 and represents that the power amplifier is normal, 64 bits are accumulated one by one according to bits, and the accumulated result is the normal power amplifier quantity.

And the correction quantity calculation submodule obtains the number of power amplifiers which should be closed/opened, namely the correction quantity N, according to different equipment numbers, namely the numbers of the FPGA chips, the number B of the power amplifiers which should be additionally closed, the number A of the power amplifiers which should be additionally opened and the large circulation quantity Big. Taking three FPGA chips with numbers of 00, 01, and 10 as examples, the computation logic of the correction amount computation submodule is as follows:

for an FPGA chip with binary number 00:

if the binary audio code < 64, then:

N＝D-B+A+Big

if D is larger than or equal to 64, then:

N＝64-B+A+Big

for the FPGA chip numbered 01:

if the binary audio code < 64, then:

N＝0-B+A+Big

if 128 > D ≧ 64, then:

N＝D-B+A+Big

if 128 is less than or equal to D, then:

N＝64-B+A+Big

for the FPGA chip numbered 10:

if the binary audio code is more than or equal to 128, then:

N＝D-B+A+Big

if D < 128, then:

N＝0-B+A+Big

the first cyclic mapping submodule is shown in fig. 4, and its principle is to input all the cyclic shift data into the multiplexer, and immediately output the cyclic shift result data according to the input cyclic coefficient, i.e. the small cyclic count value, also called the small cyclic amount L. In order to distinguish from a cyclic shift mode that shifts one bit in one cycle, this process is referred to as cyclic mapping. The process of circular mapping can refer to the example shown in fig. 5, and in order to ensure that the whole system meets the setup time requirement, a register should be added at the output end of the first circular mapping submodule, so that the whole module only needs to consume 1 system clock cycle.

The block diagram of the cancel 1 sub-module is shown in fig. 6, whose principle is based on the following equation, which changes the first 1 from the right of n to 0:

n＝n&(n-1)

based on the above formula, a 1 eliminating subunit is formed by an adder and an AND gate array, the subunits are cascaded according to the recursion idea, the result of each level of subunit is output to a multiplexer, and the corresponding output result is selected according to the elimination quantity, namely the power amplifier quantity ND. The meaning of the result of the nth level subunit is to change n bits of 1 from right to left to 0, i.e. the transcoding is completed.

The output result output by the cancellation 1 sub-module is actually a power amplifier state code with the length of 64 bits, and the power amplifier state code is different from the power amplifier state code. And the second cyclic mapping submodule performs cyclic mapping on the output result by subtracting the small cyclic quantity L from the cyclic coefficient of 64 again to restore the original mapping relation, so that the power amplifier control signal can be obtained.

In the embodiment of the present application, the work flow of each sub-module in the power amplifier control module, that is, the control data of the state machine, is as shown in fig. 7, which specifically includes the following steps:

s0, waiting for starting pulse.

S1, using a correction quantity calculation module to obtain the number of power amplifiers which should be closed/opened, namely a correction quantity N, according to the number B of power amplifiers which should be additionally closed, the number A of power amplifiers which should be additionally opened, a large circulation quantity Big and a small circulation quantity L of different equipment numbers.

And S2, mapping the low-order part with the width of small circulation quantity L to the high-order part, so that the power amplifier controlled by the original low-order part is not in a closed state for a long time after passing through the 1 elimination submodule, thereby achieving the effect of circulation, and consuming 1 system clock period in the process.

S3, because the input bit width of a multiplexer in the cancellation 1 submodule is 64 multiplied by 64bit, the combinational logic scale of the submodule is overlarge, and the register establishment time is violated. Therefore, the sub-module with elimination 1 is time-division multiplexed to reduce the scale of the combinational logic of the sub-module with elimination 1, and the specific steps are as follows:

and S3-1, shifting the number of power amplifiers needing to be closed by 1 bit (namely dividing by 2) to the right, and using the number as the input of the 1 eliminating submodule.

And S3-2, taking the output of the elimination 1 sub-module as the input of the elimination 1 sub-module in the S3-3.

And the input of the S3-3 and cancel 1 sub-module is the sum of the power amplifier quantity needing to be closed and the modulo 2 of the power amplifier quantity needing to be closed, wherein the power amplifier quantity needing to be closed is shifted to the right by 1 bit. If the highest bit of the calculation result of subtracting 64 from the number of power amplifiers needing to be closed is 1 (namely ND is less than 64), the input of the cancellation 1 sub-module at the moment becomes 0, and if the highest bit of the calculation result of subtracting 64 from the number of power amplifiers needing to be closed is not 1, the input of the cancellation 1 sub-module is still the output of the S3-2 cancellation 1 sub-module.

And S3-4, taking the output of the eliminating 1 submodule as the input of the second cycle mapping submodule in the S4.

And S4, performing cyclic mapping on the 64-Bit power amplifier state code subjected to the steps S2 and S3 by subtracting a small cyclic amount from the cyclic coefficient of 64 to restore the original mapping relation.

And S5, when the data clock is in a high level, outputting the result of the S4 through the latch.

In a possible embodiment, the output ends of the first circular mapping submodule, the cancellation-1 submodule and the second circular mapping submodule are respectively connected with a register.

Illustratively, the register connected to the output end of the second cycle mapping submodule is further connected with a latch, and the latch is used for latching and outputting the power amplifier control signal when the data clock is at a high level so as to ensure that the code modulation rate is consistent with the data clock.

In a possible embodiment, the power amplifier control module further includes: and the cyclic coding modulation control state machine is used for controlling the working states of the first cyclic mapping submodule, the cancellation-1 submodule and the second cyclic mapping submodule under the control of the starting pulse.

Illustratively, the system further comprises: and the top module is used for buffering the power amplifier state code and the binary audio code respectively through the first input buffering submodule and the second input buffering submodule and then inputting the power amplifier state code and the binary audio code to the power amplifier control module and the large circulation module respectively. The first input buffer submodule and the second input buffer submodule both work under the control of a system clock.

The top module outputs the high-order part of the external 12-Bit data, namely 8-Bit binary audio codes and 64-Bit power amplifier state codes to a subsequent module after processing of the input buffer module driven by a system clock, so as to reduce the metastable state of signals as much as possible.

Further, the top module further comprises: and the rising edge detection submodule is used for detecting the rising edge of the data clock and generating a starting pulse when the rising edge is detected. The rising edge detection submodule can synchronize the rising edge of the data clock signal with the 8Bit binary audio code, and receives the data clock signal and outputs a starting pulse with the length of one system clock period as a starting signal of a cyclic code modulation control state machine in the power amplifier control module.

The application also provides a cyclic modulation coding method of the medium wave transmitter based on the FPGA, which comprises the following steps:

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. The FPGA-based medium wave transmitter cyclic modulation coding system is characterized by comprising a plurality of FPGA chips which are electrically connected in sequence, wherein each FPGA chip is provided with:

power amplifier control module includes:

the meter 1 submodule is used for accumulating the normal power amplifiers in the input power amplifier state codes to obtain the number of the normal power amplifiers;

the correction quantity calculation submodule is used for determining corresponding correction quantities according to the number B of power amplifiers which are input by other FPGA chips and need to be additionally closed, the number A of power amplifiers which need to be additionally opened and the number of conducted power amplifiers, and outputting the number B0 of power amplifiers which need to be additionally closed and the number A0 of power amplifiers which need to be additionally opened to other FPGA chips;

a 1 eliminating sub-module, configured to perform code conversion on the cyclic shift result data, determine the number ND of power amplifiers that need to be turned off according to the normal number of power amplifiers and the correction amount, and perform multi-path selection on the cyclic shift result data after code conversion according to the number ND of power amplifiers to obtain a corresponding output result;

2. The cyclic modulation coding system of the FPGA-based medium wave transmitter of claim 1, wherein the output terminals of the first cyclic mapping submodule, the cancellation-1 submodule and the second cyclic mapping submodule are respectively connected with a register.

3. The FPGA-based medium wave transmitter cyclic modulation encoding system of claim 2, wherein a latch is further connected to the register connected to the output of the second cyclic mapping sub-module, and the latch is configured to latch and output the power amplifier control signal when the data clock is at a high level.

4. The FPGA-based medium wave transmitter cyclic modulation coding system of claim 1, wherein said power amplifier control module further comprises:

and the cyclic coding modulation control state machine is used for controlling the working states of the first cyclic mapping submodule, the cancellation-1 submodule and the second cyclic mapping submodule under the control of the starting pulse.

5. The FPGA-based medium wave transmitter cyclic modulation coding system of claim 1, further comprising:

and the top module is used for buffering the power amplifier state code and the binary audio code respectively through the first input buffering submodule and the second input buffering submodule and then inputting the power amplifier state code and the binary audio code to the power amplifier control module and the large circulation module respectively.

6. The FPGA-based medium wave transmitter cyclic modulation encoding system of claim 5, wherein the first input buffer submodule and the second input buffer submodule both operate under control of a system clock.

7. The FPGA-based MMM coding system of claim 5, wherein the top module further comprises:

and the rising edge detection submodule is used for detecting the rising edge of the data clock and generating a starting pulse when the rising edge is detected.

8. The cyclic modulation coding method of the medium wave transmitter based on the FPGA is characterized by comprising the following steps:

determining the actual conducting power amplifier number of each FPGA chip according to the input binary audio codes and the number of the FPGA chips;

performing code conversion on the cyclic shift result data, determining the power amplifier quantity ND required to be closed according to the normal power amplifier quantity and the correction quantity, and performing multi-path selection on the cyclic shift result data subjected to code conversion according to the power amplifier quantity ND to obtain a corresponding output result;

9. The cyclic modulation coding method of the FPGA-based medium wave transmitter according to claim 8, wherein the determining the actual number of turned-on power amplifiers of each FPGA chip according to the number of the input binary audio codes and the FPGA chips comprises:

dividing the binary audio codes by the number of the FPGA chips, taking the quotient as the actual conducting power amplifier number of each FPGA, and distributing the remainder to any FPGA chip.

10. The method of claim 8, wherein the generating periodic pulses and counting the pulses to obtain corresponding small cycle count values comprises:

generating a pulse signal with the length of one system clock period at regular intervals;

after receiving the pulse signal, accumulating 1 to obtain the small cycle count value;

and when the small-cycle count value is accumulated to a certain value, resetting is carried out.