CN110971489A - Simulation test method and device for variable deflection based on simulation clock generator - Google Patents
Simulation test method and device for variable deflection based on simulation clock generator Download PDFInfo
- Publication number
- CN110971489A CN110971489A CN201911225474.5A CN201911225474A CN110971489A CN 110971489 A CN110971489 A CN 110971489A CN 201911225474 A CN201911225474 A CN 201911225474A CN 110971489 A CN110971489 A CN 110971489A
- Authority
- CN
- China
- Prior art keywords
- clock
- frequency
- model
- period
- normal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/14—Network analysis or design
- H04L41/145—Network analysis or design involving simulating, designing, planning or modelling of a network
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a simulation test method and a device for variable deflection based on a simulation clock generator, wherein the method comprises the following steps: configuring the maximum value of variable skew according to the type of a protocol interface, and configuring the value range of skew offset which is allowed to be added in each clock period according to the period frequency of a normal clock model; configuring a normal clock model for one link of the verification platform, randomly configuring any preset clock model for other links of the verification platform, and in the verification process of the verification platform, if two groups of clock cycles are sequentially executed for each link of the configured preset clock model, re-randomly configuring any preset clock model until data reception is completed. The invention can simulate variable skew on each link in the verification process by configuring clocks with different frequencies on different links; in addition, because the clocks with different frequencies are randomly configured for each link, the testing pressure of the terminal equipment can be ensured, and the verification effect is improved.
Description
Technical Field
The invention belongs to the field of communication design, and mainly relates to a simulation test method and device for variable deflection based on a simulation clock generator.
Background
Many interface protocols, such as 40G/100G ethernet interface, PCIE interface, etc., all have multiple physical links; taking an ethernet interface 40GBase-R as an example, the 40GBase-R is implemented by 4 links with a rate of 10G, and in practical application, the 4 links generate skew, i.e., skew, in data transmitted between links due to different lengths of routing lines or changes of external environments. The Skew is divided into Static Skew and variable Skew, the Skew caused by different routing lengths is Static Skew, and the Skew cannot be changed after the physical connection is determined; slight rate differences between the 4 links over time can be caused by external environmental changes, such as temperature changes, resulting in a variable skew, which is a time-varying parameter.
In the existing verification platform, a plurality of clocks are generally used in verification, for example, 40GBase-R PCS verification is taken as an example, the clock in the PCS receiving direction is a serdes recovery clock, and a 40GBase-R interface has 4 physical links, so that serdes recovery clocks in 4 receiving directions exist; accordingly, the verification platform needs to generate these 4 clocks; however, in the prior art, the clocks of the 4 links are synchronized according to a uniform rate, so that variable skew cannot be simulated, a real test environment cannot be simulated, and the simulation efficiency is not high.
Disclosure of Invention
To solve the above technical problems, an object of the present invention is to provide a method and an apparatus for performing a variable skew simulation test based on an analog clock generator.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for performing a variable skew simulation test based on an analog clock generator, the method including: configuring the maximum value of variable skew according to the type of a protocol interface, expressing the maximum value by Smax, and configuring the value range of skew offset which is allowed to be added in each clock cycle according to the cycle frequency of a normal clock model;
configuring a normal clock model for one link of a verification platform, and randomly configuring any preset clock model for other links of the verification platform, wherein the frequency of each period of the normal clock model is the same; any preset clock model comprises two adjacent groups of clock cycles, the frequency of each clock cycle in one group of clock cycles is greater than the cycle frequency of the normal clock model, and the frequency of each clock cycle in the other group of clock cycles is less than the cycle frequency of the normal clock model; the absolute value of the difference between the frequency of any clock period in the clock period group which is greater than the period frequency of the normal clock model and the period frequency of the normal clock model is within the value range of the skew offset;
in the verification process of the verification platform, for each link configured with the preset clock model, if two groups of clock cycles are sequentially executed, any preset clock model is randomly configured again until data reception is completed.
As a further improvement of an embodiment of the present invention, the preset clock configured in the method includes: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is less than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
As a further improvement of an embodiment of the present invention, the preset clock configured in the method includes: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is 0.
As a further improvement of an embodiment of the present invention, the preset clock configured in the method includes: the clock frequency of each clock period of the first group of clock periods is smaller than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is larger than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
As a further improvement of an embodiment of the present invention, the method further comprises:
and for each link configuring the preset clock model, executing the next group of clock cycles when the sum of absolute values of the difference values of the cycle frequency of each clock cycle in any group of clock cycles and the cycle frequency of the normal clock model is equal to Smax.
In order to achieve one of the above objects, an embodiment of the present invention provides an analog test apparatus for performing variable skew based on an analog clock generator, the apparatus including: the basic parameter configuration module is used for configuring the maximum value of variable skew according to the protocol interface type, expressing the maximum value by Smax and configuring the value range of skew offset which is allowed to be added in each clock cycle according to the cycle frequency of a normal clock model;
the link clock configuration module is used for configuring a normal clock model for one link of the verification platform and randomly configuring any preset clock model for other links of the verification platform, wherein the frequency of each period of the normal clock model is the same; any preset clock model comprises two adjacent groups of clock cycles, the frequency of each clock cycle in one group of clock cycles is greater than the cycle frequency of the normal clock model, and the frequency of each clock cycle in the other group of clock cycles is less than the cycle frequency of the normal clock model; the absolute value of the difference between the frequency of any clock period in the clock period group which is greater than the period frequency of the normal clock model and the period frequency of the normal clock model is within the value range of the skew offset;
and the processing module is used for reconfiguring any one preset clock model at random until data reception is finished if two groups of clock cycles are sequentially executed for each link configuring the preset clock model in the verification process of the verification platform.
As a further improvement of an embodiment of the present invention, the preset clock includes: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is less than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
As a further improvement of an embodiment of the present invention, the preset clock includes: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is 0.
As a further improvement of an embodiment of the present invention, the preset clock includes: the clock frequency of each clock period of the first group of clock periods is smaller than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is larger than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
As a further improvement of an embodiment of the present invention, the processing module is further configured to: and for each link configuring the preset clock model, when the sum of absolute values of the difference values of the cycle frequency of each clock cycle in any group of clock cycles and the cycle frequency of the normal clock model is monitored to be equal to Smax, executing the next group of clock cycles.
Compared with the prior art, the invention has the beneficial effects that: the simulation test method and the device for variable deflection based on the simulation clock generator can simulate variable skew on each link in the verification process by configuring clocks with different frequencies on different links; in addition, because clocks with different frequencies are randomly configured for each link, the test pressure of the terminal equipment can be ensured, and the verification effect is improved; furthermore, in the same test case, clocks with different frequencies are randomly redistributed after two groups of clock periods, so that the test environment can be closer to a real test environment, and the authenticity of the test is ensured.
Drawings
FIG. 1 is a schematic flow chart of a simulation test method for variable skew based on a simulation clock generator according to an embodiment of the present invention;
FIGS. 2, 3, and 4 are schematic diagrams illustrating the period distribution of a default clock model according to an embodiment of the present invention;
FIG. 5 is a block diagram of an analog testing apparatus for variable skew based on an analog clock generator according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
As shown in fig. 1, a simulation test method for variable skew based on a simulation clock generator according to an embodiment of the present invention includes:
configuring the maximum value of variable skew according to the type of a protocol interface, expressing the maximum value by Smax, and configuring the value range of skew offset which is allowed to be added in each clock cycle according to the cycle frequency of a normal clock model;
configuring a normal clock model for one link of a verification platform, and randomly configuring any preset clock model for other links of the verification platform, wherein the frequency of each period of the normal clock model is the same; any preset clock model comprises two adjacent groups of clock cycles, the frequency of each clock cycle in one group of clock cycles is greater than the cycle frequency of the normal clock model, and the frequency of each clock cycle in the other group of clock cycles is less than the cycle frequency of the normal clock model; the absolute value of the difference between the frequency of any clock period in the clock period group which is greater than the period frequency of the normal clock model and the period frequency of the normal clock model is within the value range of the skew offset;
in the verification process of the verification platform, for each link configured with the preset clock model, if two groups of clock cycles are sequentially executed, any preset clock model is randomly configured again until data reception is completed.
For the specific value of Smax, when the type of the protocol interface is determined, the value is a fixed value, taking a 40GBase-R interface as an example, the value is actually the number of bits in any two links, where one link can reach data ahead of the other link, and the number of bits is converted according to the required unit of Smax, so as to obtain the specific value of Smax, and the value is usually in nanoseconds ns.
The range of values of skew offset allowed to be added for each clock cycle is denoted by s1, s 2; the specific numerical value is any value between [ s1, s2 ]; the specific values of s1 and s2 can be set according to the type of the protocol interface; which is typically in units of picoseconds ps. In the specific implementation mode of the invention, the value range of the skew offset is set according to the cycle frequency of a normal clock model; in general, the minimum value of s1 is 0, the maximum value of s2 is 1T, and T represents the cycle frequency of the normal clock model; in a preferred embodiment of the present invention, for example: s1 is 0 and S2 is 20% T.
And verifying the link number of the platform, wherein when the protocol interface type is determined, the link number is a fixed value, and taking a 40GBase-R interface as an example, the link number has 4 links. Accordingly, in this specific example, a normal clock model is configured for one link, and a preset clock model is configured for all the other 3 links.
In an implementation manner of the invention, the preset clock model has three expression modes;
in a first expression mode, as shown in fig. 2, the preset clock includes: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is less than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
In a second expression mode, as shown in fig. 3, the preset clock includes: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is 0.
In a third expression mode, as shown in fig. 4, the preset clock includes: the clock frequency of each clock period of the first group of clock periods is smaller than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is larger than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
Of course, in other embodiments of the present invention, the three preset clock models and the normal clock model may be combined to form other preset clock models, which is not further described herein. It should be noted that, in the examples shown in fig. 2, fig. 3, and fig. 4, in order to visually observe three preset clock models, a normal clock model is synchronously shown on the basis of the preset clock models for comparison and observation.
In a preferred embodiment of the present invention, the default clock model is called by an infinite loop statement, the infinite loop statement is represented by ClkMode, and values of the ClkMode are 0, 1 and 2, respectively, where 0 represents the default clock model shown in fig. 2, 1 represents the default clock model shown in fig. 3, and 2 represents the default clock model shown in fig. 4, so that when a link is configured, and at the beginning of each loop, any default clock model can be randomly configured for any link by calling the ClkMode parameter, and after two clock cycles are completed in any link sequence, the ClkMode parameter is called again in a loop, and a next default clock model is randomly selected until verification is completed.
In addition, it should be noted that, for any preset clock model, the frequency of each clock cycle in the two groups of clock cycles is not necessarily equal, and when each clock cycle arrives, it will perform random processing on the frequency of the cycle, and correspondingly, when each clock cycle arrives, for the preset clock cycle group with the cycle frequency greater than that of the normal clock model, it needs to obtain any value from the value range [ s1, s2] of the skew offset, and subtract the obtained value from the single clock frequency of the normal clock to form the clock frequency of the current clock cycle;
for a preset clock period group with the period frequency not being 0 and being smaller than the period frequency of the normal clock model, any value needs to be obtained from the value range [ s1, s2] of the skew offset, and the obtained value is superposed on the single clock frequency of the normal clock to form the clock frequency of the current clock period.
In the above example, the present invention configures a normal clock model for one of the links of the verification platform, and randomly configures any preset clock model for the other links of the verification platform, so that by randomly selecting one of the links without adding any skew to the clock model of the link, the ideal clock output is used to prevent directions that may be caused when all the links are randomly added with skew from being consistent, and further prevent the current test case from being the test case with the highest pressure. The test pressure reflects the performance of the current terminal equipment, and the higher the test pressure is, the better the performance index is.
Further, in a preferred embodiment of the present invention, the method further includes: and for each link configuring the preset clock model, when the sum of absolute values of differences between the period frequency of each clock period in any group of clock periods and the period frequency of the normal clock model is equal to Smax, namely the sum of the skew offsets of any clock period is equal to Smax, executing the next group of clock periods.
For convenience of understanding, taking an example that one link is configured with the preset clock mode shown in fig. 2 in a certain time period, assuming that Smax is 1ns, skew offsets obtained by each clock cycle in the preceding fast clock cycle group are the same, and are all 100ps is 0.1ns, and the normal clock cycle is T, and each clock cycle in the fast clock cycle group is T-0.1ns, according to the above-mentioned word expression, when the tenth cycle ends, the sum of the skew offsets of the fast clock cycle group is equal to 0.1ns 10 is 1ns Smax, and at this time, if the verification does not end, the next group of clock cycles is executed, and if the verification ends, the link reaches Smax in advance compared with the link configured with the normal clock mode; the Smax is the skew allowed by the link, so that the skew of the link can be truly simulated under the condition of keeping the link pressure; otherwise, if the verification is not finished, the next group of clock cycles will run at the lower frequency, and likewise, when the sum of the skew offsets is equal to Smax; replacing a preset clock model; at this time, the clock accelerated in the previous group of clock cycles is subjected to frequency reduction compensation by the next clock cycle; therefore, on any link, when the speed is accelerated or decelerated, the difference value is at most Smax, and the verification accuracy is ensured.
Referring to fig. 5, an embodiment of the present invention provides an analog testing apparatus for variable skew based on an analog clock generator, the apparatus including: basic parameter configuration module 100, link clock configuration module 200, and processing module 300.
The basic parameter configuration module 100 is configured to configure a maximum value of variable skew according to a protocol interface type, and configure a value range of skew offset allowed to be added in each clock cycle according to a cycle frequency of a normal clock model, where the maximum value is represented by Smax; the link clock configuration module 200 is configured to configure a normal clock model for one link of the verification platform, and randomly configure any preset clock model for other links of the verification platform, where the frequency of each cycle of the normal clock model is the same; any preset clock model comprises two adjacent groups of clock cycles, the frequency of each clock cycle in one group of clock cycles is greater than the cycle frequency of the normal clock model, and the frequency of each clock cycle in the other group of clock cycles is less than the cycle frequency of the normal clock model; the absolute value of the difference between the frequency of any clock period in the clock period group which is greater than the period frequency of the normal clock model and the period frequency of the normal clock model is within the value range of the skew offset; the processing module 300 is configured to, in the verification process of passing the verification platform, for each link configured with the preset clock model, if two groups of clock cycles are sequentially executed, re-randomly configure any preset clock model until data reception is completed.
In a first preferred embodiment of the present invention, the preset clock includes: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is less than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
In a second preferred embodiment of the present invention, the preset clock includes: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is 0.
In a third preferred embodiment of the present invention, the preset clock includes: the clock frequency of each clock period of the first group of clock periods is smaller than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is larger than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
Further, the processing module 300 is further configured to: and for each link configuring the preset clock model, when the sum of absolute values of the difference values of the cycle frequency of each clock cycle in any group of clock cycles and the cycle frequency of the normal clock model is monitored to be equal to Smax, executing the next group of clock cycles.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the modules described above may refer to the corresponding process in the foregoing method embodiments, and is not described herein again.
In summary, the simulation test method and apparatus for variable skew based on the simulation clock generator of the present invention can simulate variable skew on each link in the verification process by configuring clocks with different frequencies on different links; in addition, because clocks with different frequencies are randomly configured for each link, the test pressure of the terminal equipment can be ensured, and the verification effect is improved; furthermore, in the same test case, clocks with different frequencies are randomly redistributed after two groups of clock periods, so that the test environment can be closer to a real test environment, and the authenticity of the test is ensured.
The above-described system embodiments are merely illustrative, wherein the modules illustrated as separate components may or may not be physically separate, and the components shown as modules are logical modules, which may be located in one module in the structural logic or may be distributed across multiple data processing modules in the structural logic. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for performing variable skew analog testing based on an analog clock generator, the method comprising:
configuring the maximum value of variable skew according to the type of a protocol interface, expressing the maximum value by Smax, and configuring the value range of skew offset which is allowed to be added in each clock cycle according to the cycle frequency of a normal clock model;
configuring a normal clock model for one link of a verification platform, and randomly configuring any preset clock model for other links of the verification platform, wherein the frequency of each period of the normal clock model is the same; any preset clock model comprises two adjacent groups of clock cycles, the frequency of each clock cycle in one group of clock cycles is greater than the cycle frequency of the normal clock model, and the frequency of each clock cycle in the other group of clock cycles is less than the cycle frequency of the normal clock model; the absolute value of the difference between the frequency of any clock period in the clock period group which is greater than the period frequency of the normal clock model and the period frequency of the normal clock model is within the value range of the skew offset;
in the verification process of the verification platform, for each link configured with the preset clock model, if two groups of clock cycles are sequentially executed, any preset clock model is randomly configured again until data reception is completed.
2. The method of claim 1, wherein the configuring the preset clock comprises: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is less than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
3. The method of claim 1, wherein the configuring the preset clock comprises: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is 0.
4. The method of claim 1, wherein the configuring the preset clock comprises: the clock frequency of each clock period of the first group of clock periods is smaller than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is larger than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
5. The method for variable skew analog testing based on an analog clock generator of claim 1, further comprising:
and for each link configuring the preset clock model, executing the next group of clock cycles when the sum of absolute values of the difference values of the cycle frequency of each clock cycle in any group of clock cycles and the cycle frequency of the normal clock model is equal to Smax.
6. An analog test apparatus for variable skew based on an analog clock generator, the apparatus comprising:
the basic parameter configuration module is used for configuring the maximum value of variable skew according to the protocol interface type, expressing the maximum value by Smax and configuring the value range of skew offset which is allowed to be added in each clock cycle according to the cycle frequency of a normal clock model;
the link clock configuration module is used for configuring a normal clock model for one link of the verification platform and randomly configuring any preset clock model for other links of the verification platform, wherein the frequency of each period of the normal clock model is the same; any preset clock model comprises two adjacent groups of clock cycles, the frequency of each clock cycle in one group of clock cycles is greater than the cycle frequency of the normal clock model, and the frequency of each clock cycle in the other group of clock cycles is less than the cycle frequency of the normal clock model; the absolute value of the difference between the frequency of any clock period in the clock period group which is greater than the period frequency of the normal clock model and the period frequency of the normal clock model is within the value range of the skew offset;
and the processing module is used for reconfiguring any one preset clock model at random until data reception is finished if two groups of clock cycles are sequentially executed for each link configuring the preset clock model in the verification process of the verification platform.
7. The analog clock generator-based analog testing device for variable skew of claim 6, wherein the preset clock comprises: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is less than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
8. The analog clock generator-based analog testing device for variable skew of claim 6, wherein the preset clock comprises: the clock frequency of each clock period of the first group of clock periods is greater than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is 0.
9. The analog clock generator-based analog testing device for variable skew of claim 6, wherein the preset clock comprises: the clock frequency of each clock period of the first group of clock periods is smaller than the cycle frequency of the normal clock model, and the frequency of each clock period of the second group of clock periods is larger than the cycle frequency of the normal clock model; and the absolute value of the difference between the frequency of any clock period and the period frequency of the normal clock model is within the value range of the skew offset.
10. The analog clock generator-based analog testing apparatus for variable skew of claim 6,
the processing module is further configured to: and for each link configuring the preset clock model, when the sum of absolute values of the difference values of the cycle frequency of each clock cycle in any group of clock cycles and the cycle frequency of the normal clock model is monitored to be equal to Smax, executing the next group of clock cycles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911225474.5A CN110971489A (en) | 2019-12-04 | 2019-12-04 | Simulation test method and device for variable deflection based on simulation clock generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911225474.5A CN110971489A (en) | 2019-12-04 | 2019-12-04 | Simulation test method and device for variable deflection based on simulation clock generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110971489A true CN110971489A (en) | 2020-04-07 |
Family
ID=70032931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911225474.5A Withdrawn CN110971489A (en) | 2019-12-04 | 2019-12-04 | Simulation test method and device for variable deflection based on simulation clock generator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110971489A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020126581A1 (en) * | 2001-03-06 | 2002-09-12 | Masahito Endo | Method of analyzing clock skew between signals |
| CN101471816A (en) * | 2007-12-24 | 2009-07-01 | 瑞昱半导体股份有限公司 | Dithering generator for generating dithering clock signal |
| CN102171966A (en) * | 2011-04-11 | 2011-08-31 | 华为技术有限公司 | Method and apparatus for simulating packet delay variation in current network |
| CN102176030A (en) * | 2010-12-31 | 2011-09-07 | 桂林电子科技大学 | Global positioning system (GPS)/global navigation satellite system (GLONASS) dual-system combination simulator and method |
| CN107979436A (en) * | 2017-11-10 | 2018-05-01 | 广州海格通信集团股份有限公司 | Interference signal generation method, device, computer equipment and storage medium |
| CN109981204A (en) * | 2019-02-21 | 2019-07-05 | 福建星云电子股份有限公司 | A kind of Multi-Machine Synchronous method of BMS analogue system |
-
2019
- 2019-12-04 CN CN201911225474.5A patent/CN110971489A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020126581A1 (en) * | 2001-03-06 | 2002-09-12 | Masahito Endo | Method of analyzing clock skew between signals |
| CN101471816A (en) * | 2007-12-24 | 2009-07-01 | 瑞昱半导体股份有限公司 | Dithering generator for generating dithering clock signal |
| CN102176030A (en) * | 2010-12-31 | 2011-09-07 | 桂林电子科技大学 | Global positioning system (GPS)/global navigation satellite system (GLONASS) dual-system combination simulator and method |
| CN102171966A (en) * | 2011-04-11 | 2011-08-31 | 华为技术有限公司 | Method and apparatus for simulating packet delay variation in current network |
| CN107979436A (en) * | 2017-11-10 | 2018-05-01 | 广州海格通信集团股份有限公司 | Interference signal generation method, device, computer equipment and storage medium |
| CN109981204A (en) * | 2019-02-21 | 2019-07-05 | 福建星云电子股份有限公司 | A kind of Multi-Machine Synchronous method of BMS analogue system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6149150B2 (en) | Timestamp correction in skewed multilane communication links | |
| CN103746884A (en) | Method and system for testing flow through switchboard | |
| CN102981116B (en) | Dedicated integrated circuit checking device and method | |
| CN104865518A (en) | CLB dynamic aging configuration method of SRAM type FPGA | |
| CN110380923B (en) | In-situ component protection ring network testing device | |
| CN103036740A (en) | Ethernet passive optical network (EPON) system testing method for network terminal gigabit Ethernet interface signal | |
| CN101222732B (en) | State control signal testing device | |
| CN108415269A (en) | The emulation platform of MMC systems based on FPGA | |
| CN106161117A (en) | The analogue system of a kind of AFDX network and emulation mode | |
| US8769448B1 (en) | Circuit design simulation | |
| CN108120917B (en) | Method and device for determining test clock circuit | |
| CN103698636B (en) | A kind of method of relay-protection tester parallel synchronous test | |
| CN102291449B (en) | Method for testing and adjusting cluster storage system performance based on synchronous strategy | |
| CN103530166A (en) | Verification platform and verification method for multi-channel chip based on virtual RAM | |
| CN203788305U (en) | Ethernet flow multiplier | |
| CN110971489A (en) | Simulation test method and device for variable deflection based on simulation clock generator | |
| CN104734900A (en) | Sending control method for communication protocol testing | |
| CN102298112A (en) | Method and system for testing programmable logic device | |
| CN209517154U (en) | It supports to realize the circuit structure that accurate delay is handled | |
| CN103559111A (en) | Method and system for input-output (IO) channel debugging of field programmable gate array (FPGA) chips | |
| CN113836675B (en) | Emulator simulation system, method and emulator | |
| CN109450763A (en) | A kind of bus expanding method, gateway and extended bus system | |
| CN103559159A (en) | Information processing method and electronic device | |
| CN108279591B (en) | Simulation platform digital quantity universal output method | |
| CN106899502B (en) | trigger signal segmented routing device and method for PXIe backboard |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Applicant after: Suzhou Shengke Communication Co.,Ltd. Address before: Xinghan Street Industrial Park of Suzhou city in Jiangsu province 215021 B No. 5 Building 4 floor 13/16 unit Applicant before: CENTEC NETWORKS (SU ZHOU) Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20200407 |
|
| WW01 | Invention patent application withdrawn after publication |