JP2003204363A - Serial transmission system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a ratio of transmission speed to data speed in serial transmission, provided with bit error correction function and DC balance guarantee. <P>SOLUTION: A serial transmission unit 4 includes a coding circuit 24 producing a block code having a lower coding ratio than the ratio of transmission speed to data speed, and a scrambling circuit 23 without producing an increase in the transmission speed, whereby a parallel data is framed and serially transmitted. A serial reception unit 5 includes a frame synchronization circuit 43, a decoding circuit 44 for decoding the block code, and a descrambling circuit 46, whereby the frame is restored to a parallel data. Thus, a serial transmission system having a ratio of transmission speed to data speed no greater than 1.25 becomes obtainable. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to serial transmission, and in particular, in-device LSI (Large Scale Integrated Circuit).
The present invention relates to a frame synchronization method in a serial transmission method between terminals.

[0002]

2. Description of the Related Art In a transmission using a serial transmission line, continuous parallel data is converted into serial data.
The serial data received by the receiving side is again converted into correct parallel data. Therefore, it is necessary to detect a word break from the serial data and maintain it (synchronize) continuously.

When the transmission line is connected by AC coupling, continuous "0" data (or "1")
When the data is sent, there is a problem that the DC balance changes.

As a conventional method for solving the above problems,
There is an 8B10B encoding method. The 8B10B encoding method is a method of converting 8-bit parallel data into a 10-bit code, serializing the 10-bit code, and transmitting the serial code through a serial transmission path. 8 bits to 10
When converting to bits, the comma (co
mma) ”separator (“ 0011111 ”or“ 110000
Since 0 ″) is inserted, the division points can be recognized and synchronized.

Also, in the encoding, the DC balance is also taken into consideration, and the number of "0" data and "1" data is exactly "4: 6""5:5""6:4". To encode.

[0006]

Problems to be Solved by the Invention LAN (Local Area N
For bit errors in serial transmission lines such as etwork) and WAN (Wide Area Network), CRC (Cyclic Redundancy) is used in layers higher than the data link layer.
Check) etc. are used for error detection, and packet retransmission is used for error correction.

The above method is useful in a system that can tolerate a delay to the extent that retransmission is possible as described above. However, the above method cannot be applied to a system such as a high-speed bus in a computer device or a backplane in a high-speed router device that requires a low delay such that retransmission cannot be performed.

To cope with the above, a method called FEC (Forward Error Correct) in which redundant data is added in advance to the data to be transmitted and the received data (data including an error) is converted into correct data There is.

In the conventional 8B10B coding method, 8-bit parallel data is converted into 10 bits, so that the coding rate (code length / data length) is 10/8.
= 1.25. However, the FEC
, The FEC encoding is applied to the original data,
Moreover, since 8B10B conversion is performed, the transmission speed is 1.25 times or more (the magnification depends on the encoding method used for FEC).
This is one of the factors that make speeding up difficult.

[0010]

In order to solve the above-mentioned problems, the present invention has a scrambler circuit for scrambling original data in a serial data transmission section, and a coding rate lower than 1.25. Block code with error correction capability (Hamming code and BCH (Bose, Chaudhuri, Hocqueng
hem) code or RS (Reed-Solomon) code), and an FEC encoding circuit for encoding data (hereinafter, FEC encoding),
BIP (Bi
a frame synchronization circuit that establishes synchronization on a frame-by-frame basis in the receiving unit, and a decoding (hereinafter FEC decoding) of data encoded by the block code and an error correction. There is provided a serial transmission system and a serial transmission circuit characterized by comprising an FEC decoding circuit for performing the above, a BIP inspection circuit for inspecting BIP, and a descramble circuit for descrambling data to restore the original data.

DC balance can be ensured by the scrambler circuit and the descrambler circuit. Further, since the block code whose coding rate is lower than 1.25 is used, the transmission speed is 1.25 times or less and the error correction function is also realized. Although it is possible to further reduce the transmission rate by lowering the coding rate, conversion delay increases because FEC decoding cannot be performed until all the codes are received. Preferably, a Hamming code with a short conversion delay,
A code length of 31 bits close to the coding rate of 1.25 (data length 2
6 bits, coding rate 1.192) or 63 bits (data length 57 bits, coding rate 1.105). Encoding methods other than Hamming code (BCH code, RS code, etc.)
Also, if the delay time required for encoding / decoding conversion is within the requirements of the system to which it is applied, it can be used.

A first feature of the present invention is that in serial data transmission using a serial transmission line, a transmission frame buffer, one or a plurality of serial transmission units, one or a plurality of serial reception units, and a reception frame. The serial transmission unit includes a buffer, and the serial transmission unit performs frame error correction, a frame generation circuit that generates a frame that stores parallel data, a scrambler circuit that randomizes the data to ensure DC balance in the serial transmission path, and a bit error correction. Therefore, the serial receiving unit detects the synchronization pattern stored in the frame, determines the division of the frame from the position of the synchronization pattern, and determines the frame synchronization. Identifies error bits from the frame synchronization circuit and the data stored in the frame and check bits , FEC for error correcting an error bit
This is a serial transmission system characterized by comprising a decoding circuit and a descrambler circuit for restoring the original data from the data randomized by the scrambler circuit.

A second feature of the present invention is that, in the FEC encoding circuit, the encoding circuit using the shift register based on the block polynomial generating polynomial is x + n- from the xth clock.
The processing performed in the first clock is performed in the first clock, the result is held in the FF, and in the next clock, the encoding circuit performs the x + nth clock to the x + 2n−1th clock based on the result of the previous clock held in the FF. The FEC encoding circuit is characterized by performing the processing described in 1.

A third feature of the present invention is that, in the FEC decoding circuit, the decoding circuit by the shift register based on the generating polynomial of the block code is x + n- from the xth clock.
The processing performed in the first clock is performed in the first clock, the result is held in the FF, and in the next clock, based on the result of the previous clock held in the FF, the decoding circuit switches from the x + nth clock to the x + 2n−1th clock. The FEC decoding circuit is characterized by performing processing.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an LS according to the present invention.
It is a schematic diagram showing the composition of serial transmission between I. In FIG. 1, from the LSI internal logic circuit 3-1 of the LSI 1-1 to the LSI
1 shows a system for transferring data to a 1-2 LSI internal logic circuit 3-2.

First, the parallel data output from the LSI internal logic circuit 3-1 is sent to the transmission frame buffer 6 through the parallel transmission line 10-1 having m × n lines.

At the input of the transmission frame buffer 6, the transmitted parallel data is stored in the buffer in synchronization with the same clock used in the LSI internal logic circuit 3-1. At the output of the transmission frame buffer 6, the data stored in the buffer is read out in synchronization with the clock used by the serial transmission units (4-1 to 4-m) in the subsequent stage, and the parallel transmission lines (11-1 to 11-11) are read. −
m) is used to send to each serial transmission unit (4-1 to 4-m). At this time, the parallel data composed of mn lines is
The number of lines is divided into n and m sets of parallel data. The number of transmitting units may be one or plural.

Each of the serial transmission units (4-1 to 4-m) converts parallel data of the number of lines n into serial data,
Serial transmission is performed using the serial transmission lines (2-1 to 2-m).

The serial data transmitted serially is L
Serial receiving unit located at SI1-2 (5-1 to 5-
Received at m). The serial receiver converts serial data into parallel data.

One or more serial receivers (5-1
5 m to 5 m) are transmitted to the reception frame buffer 7 using the parallel transmission lines (12-1 to 12-m). There is a difference between the transmitted parallel data due to factors such as a difference in transmission distance of the serial transmission lines (2-1 to 2-m) and a clock fluctuation of each serial receiving unit (5-1 to 5-m). There is a phase difference. Therefore, in the reception frame buffer 7, each serial reception unit (5-1 to 5-
Write parallel data using the clock of m),
It is read at the clock of the LSI internal logic circuit 3-2. Thereby, the phase difference and the serial receiving unit (5-1
.About.5-m) and the clock difference between the LSI internal logic circuit 3-2 are absorbed. Finally, the read parallel data is sent to the LSI internal logic circuit 3-2 using the parallel transmission line 10-2.

Serial transmission units (4-1 to 4) will be described with reference to FIG.
An example of -m) will be described. In configuring the serial transmission unit 4 (4-1 to 4-m when configured with a plurality),
Parallel transmission line 11 (11-1 when configured with multiple sets
.About.11-m) and the transmission characteristics of the serial transmission line 2 (2-1 to 2-m when composed of a plurality of lines), the number n of parallel lines of the parallel transmission line 11 is determined. It is considered that the transmission clock of the serial transmission line 2 is n times that of the parallel transmission line 11 in order to perform parallel-serial conversion in this transmission unit. Further, the parallel transmission lines 10-1 and the parallel transmission lines 11 are compared with each other, and if there is a difference of m times, the serial transmission unit 4 is set to m sets (4-1 to 4-).
m) Prepare and configure them to operate synchronously. Although the description of the present embodiment is given for the serial transmission unit 4-1, the same applies to the other reception units.

The clock used in each circuit will be described. First, the clock signal 3 used by the LSI internal logic
0, and a frame signal 3 obtained by dividing the clock 30
5 (defined as 140 frequency division in this embodiment). The clock signal 30 is used by the write side of the transmission frame buffer 6 and the PLL (Phase Lock Loop) circuit 20.
Based on the clock signal 30, the PLL circuit 20 outputs 5n /
Clock signal 31 multiplied by 4 (n is the number of parallel lines)
Is generated, and P / of each serial transmission unit (4-1 to 4-m) is generated.
It is distributed to the S (Parallel to Serial) conversion circuit 26 and the frequency dividing circuit 21. That is, the clock signal 31 becomes the transmission clock of the serial transmission line. In addition, 5/4 of the above magnification
Is derived from the coding rate of 1.25. The frequency dividing circuit 21 divides the clock signal 31 by n to generate a clock signal 32, which is distributed to each circuit in the serial transmission unit 4-1 and the read side of the transmission frame buffer 6. That is, the clock signal 32 is 5/4 times the clock signal 30.

On the write side, the transmission frame buffer 6 receives the parallel data on the parallel transmission line 10-1 synchronized with the clock signal 30. At this time, one cycle of the frame signal 35 (in this embodiment, the clock signal 3
Parallel data of 0 (dividing by 140) is regarded as one frame data and is written in the frame buffer in synchronization with the frame signal 35. On the read side of the transmission frame buffer 6, a frame signal obtained by delaying the frame signal 35 is generated, and frame data is read from the frame buffer in synchronization with the frame signal. The frame data is output to the parallel transmission line 11-1 in synchronization with the clock signal 32, and at the same time, the frame signals are run in parallel.

The serial transmission unit includes the frame generation circuit 2
2, scrambler circuit 23, FEC encoding circuit 24, B
It is composed of an IP assigning circuit 25, a P / S converting circuit 26 and the frequency dividing circuit 21. The respective circuits will be described below.

FIG. 7 is a format diagram showing an example of the frame format.

The frame generation circuit 22 generates a frame storing the received parallel data according to the frame format shown in FIG. At this time, the frame signal matched with the head of the frame is run in parallel. The frame includes a sync pattern area 120, a payload area 122, and B.
It comprises an IP area 123 and a reserve area 121.
A pattern (hexadecimal value “0xF628” or the like) indicating the beginning of the frame is stored in the synchronization pattern area 120. The pattern is used for pattern matching in the sync pattern detecting circuit 100 of the serial receiving unit 5 to detect the beginning of the frame. In the payload area 122, a block (13
20 sets of 0-1 to 130-20) are stored. Each of the blocks (130-1 to 130-20) has a data area 1
31, FEC area 132, DC balance guarantee bit 13
It consists of three. In the data area 131, the parallel data is stored for 56 bits of the 57 bits, and the final bit 134 is not used (“0” or the like is stored). The DC balance guarantee bit 133 stores a "1" value so that the payload area 122 does not have all "0" values, and guarantees the DC balance at a minimum. The frame generation circuit 22 generates the frame configured as described above and sends it to the scrambler circuit 23.

FIG. 8 is a block diagram showing an embodiment of the scrambler / descrambler.

The scrambler circuit 23 uses the generator polynomial "X
^{The 7th-} order pseudorandom value generated by “ ⁷ + X ⁶ +1” is added to the parallel data (FIG. 8). Further, each shift register is preset (“1”) in synchronization with the frame signal of the input frame. However, scrambling is performed only on the data area 130 of the frame data, and the data other than the above is passed through without any addition and the operation of the shift register is temporarily stopped.

An embodiment of the FEC encoding circuit 24 will be described. In the FEC encoding circuit 24 of the present embodiment, the 57-bit data area 131 (using only 56 bits) that is the original data is checked by the Hamming code generator polynomial “X ⁶ + X + 1” having a code length of 63 bits. Bits (6 bits) are calculated. FIG. 9 shows a general 1-bit FEC encoding circuit that performs a 1-bit operation using a shift register based on the generator polynomial. The FEC
The encoding circuit includes six FFs (Flip Flops) (110-1 to 110-1).
110-6) and two exclusive ORs (hereinafter, EOR). In synchronization with the FF (110-1 to 110-6) clock, 57-bit data is input from the input (Input) to 1
When the bits are input bit by bit, the 6-bit value indicated by the FFs (110-1 to 110-6) becomes the check bit obtained after the final bit (57th bit) is input. FF (110-
1 to 110-6) hold the calculation results held by "F
(0), F (1), ..., F (5) ”, and the 1-bit input data is I
If n, then the 1-bit FEC encoding circuit calculates the following equations (1-1 to 1-6) for each clock. The calculation in the present invention is an operation on the Galois field, and the adder is a 2-input exclusive OR circuit and the multiplier is a 2-input AND circuit. F (5) = F (4)… (1-1) F (4) = F (3)… (1-2) F (3) = F (2)… (1-3) F (2) = F (1)… (1-4) F (1) = F (5) + F (0) + In… (1-5) F (0) = F (5) + In… (1-6) The clock required for the FEC encoding circuit shown in FIG.
Since it becomes equal to the clock signal 31 of the above, it is difficult to realize inside the LSI. Therefore, in the present invention, the FEC encoding operation for the number n of parallel lines is performed with one clock of the clock signal 32. In this embodiment, the number of parallel lines n =
8 In the 1-bit FEC encoding circuit, 8
In order of serial input of bit input data, "bit
(7), bit (6), ..., Bit (0) ”, the value of the FF after 8 clocks can be expressed by the following equations (2-1 to 2-6). F (5) = F (3) + F (2) + bit (5) + bit (4)… (2-1) F (4) = F (2) + F (1) + bit (4) + bit (3)… (2-2) F (3) = F (5) + F (1) + F (0) + bit (7) + bit (3) + bit (2)… (2-3) F (2) = F (4) + F (0) + bit (6) + bit (2) + bit (1)… (2-4) F (1) = F (5) + F (3) + bit (7) + bit (5) + bit (1) + bit (0)… (2-5) F (0) = F (4) + F (3) + bit (6) + bit (5) + bit (0) (2-6) Since the data length of the 63-bit code used in this embodiment is 57 bits, it is 8 when calculated with 8 bits / clock.
A clock is needed. Here, in the 8 clocks,
From the first clock, it is written as “0T, 1T, ..., 7T”. From 0T to 6T, the above equations (2-1 to 2-6) are repeatedly executed to calculate 8 bits at a time.
Since only the 57th bit of input data is calculated in T,
The following formulas (3-1 to 3-6) are implemented. F (5) = F (4) (3-1) F (4) = F (3) (3-2) F (3) = F (2) (3-3) F (2) = F (1)… (3-4) F (1) = F (5) + F (0) + bit (7)… (3-5) F (0) = F (5) + bit (7)… (3-6) The values of F (5) to F (0) finally remaining by the above equation become the check bits (6 bits).

FIG. 4 shows an embodiment of the FEC encoding circuit 24 to which the above method is applied. The 8-bit input data 65 is represented by "bit (7), bit (6), ..., Bit (0)", and FF (60-
1-60-6) hold the calculation results held by "F (0),
F (1), ..., F (5) ”. The FF (60-1 to 6
0-6) is the FF (11) of the 1-bit FEC encoding circuit.
0-1 to 110-6). The 8-bit input data 65 also corresponds to the 1-byte bit string shown in FIG.

First, 57-bit data is divided into 8-bit units and input as input data 65 for each clock. The input data is 8 bits in 0T to 6T and 1 bit only in bit (7) in 7T.

Next, the input data 65 is assigned to the inputs of the selectors (61-1 to 61-6) bit by bit. For example,
The input 0 of the selector 61-1 has “bit (6), bit (5),
Calculate and input the exclusive OR of 3 bits of "bit (0)". Input "bit (7)" in the first input. The selectors (61-1 to 61-6) and the selector 64 are
Input 0 is selected when "0T to 6T", and data input 1 is selected when "7T" is output.

The output values of the FFs (60-1 to 60-6) are input to the coefficient calculation circuit 62 and the coefficient calculation circuit 63. The coefficient calculation circuit 62 calculates only the part corresponding to “F (0) to F (5)” in the equations (2-1 to 2-6), and outputs the result to the input 0 of the selector 64. Similarly, the coefficient calculation circuit 63 also calculates only the part corresponding to “F (0) to F (5)” in the equations (3-1 to 3-6) and outputs the result to the input No. 1 of the selector 64.

The output values of the selectors (61-1 to 61-6) and the selector 64 are exclusively ORed, and the result is held in the FFs (60-1 to 60-6).

By performing the above processing from 0T to 7T, the final remaining values of FF (60-6 to 60-1) F (5) to F (0) are checked bits 66 (6 bits). Becomes
The check bit 66 thus obtained is stored in the FEC area 132, and the frame is sent to the BIP adding circuit 25.

The BIP adding circuit 25 obtains a parity by performing an exclusive OR operation on the parallel data of the n-bit width of the received frame for each clock, and stores the value of the parity in the BIP area 123 of the frame. The processed frame is sent to the P / S conversion circuit 26.

The P / S conversion circuit 26 converts the received frame from parallel data to serial data in synchronization with the clock signal 31 and the clock signal 32. The serial data is sent to the transmission line 2.

As described above, the serial transmission unit 4 converts the parallel data from the LSI internal logic circuit 3-1 into serial data.

The serial receiver (5-1 to 5) will be described with reference to FIG.
An example of -m) will be described. In the configuration of the serial reception unit 5 (5-1 to 5-m when configured with a plurality of units), the number n of parallel lines of the parallel transmission line 12 is determined as in the case of the serial transmission unit 4. Similarly, the parallel transmission line 10-
2 and the number of parallel lines of the parallel transmission line 12 are compared, and when there is a difference of m times, the serial reception unit 5 is set to m sets (5-1 to
5-m) are arranged and they are synchronously operated. Although the description of the present embodiment will be given for the serial receiving unit 5-1,
The same applies to the other receiving units.

First, the clock used in each circuit will be described. Clock signal 55 used by LSI internal logic
Is the read side of the reception frame buffer 7, CDR (Clock
Data Recovery) circuit 40 is used. Further, the frame signal 56 obtained by dividing the clock signal 55 (140 in this embodiment)
Frequency division) is supplied to the read side of the reception frame buffer 7.

The CDR circuit 40 refers to the clock signal 55 to generate the clock signal 50 extracted from the serial data of the serial transmission line 2-1 and to generate the clock signal 50.
The serial data received at 0 is resampled.
The resampled serial data is sent to the S / P conversion circuit 42. The clock signal 50 is the S / P
It is distributed to the conversion circuit 42 and the frequency dividing circuit 41.

The frequency dividing circuit 41 divides the clock signal 50 by n to generate a clock signal 51, and the serial receiving section 5-1.
It is distributed to each circuit inside and the write side of the reception frame buffer 7.

The S / P conversion circuit 42 converts the received serial data into parallel data having the number of lines n in synchronization with the clock signal 50 and the clock signal 51. At this time, the phase adjustment signal 52 output from the frame synchronization circuit 43
To change the phase during serial-parallel conversion. The parallel data is sent to the frame synchronization circuit 43.

An embodiment of the frame synchronization circuit 43 will be described with reference to FIG. The frame synchronization circuit 43 includes a synchronization pattern detection circuit 100, a synchronization protection state circuit 101, and a phase adjustment signal generation circuit 102. Each circuit in the frame synchronization circuit 43 operates in synchronization with the clock signal 51.

The synchronization pattern detection circuit 100 receives the 8-bit parallel data, detects the pattern inserted in the frame synchronization pattern area 120 by the frame generation circuit 22 of the serial transmission unit 4 from the bit string, Find the position of the first bit in the frame. The position of the first bit of the frame is output to the synchronization protection state circuit 101 and the phase adjustment signal generation circuit 102 as the synchronization detection signal 105. Also, a frame signal 53 indicating the beginning of the frame
Is generated and sent to the FEC decoding circuit 44 together with the parallel data.

The synchronization protection state circuit 101 has a function of "front 5
Frame synchronization protection state such as "stage, 2 stages behind".
The state transitions based on the received synchronization detection signal. When the synchronization pattern is received again at the 175th clock after receiving the synchronization pattern, it is determined as “match”, and when it is received at the preceding and subsequent clocks, it is determined as “error”. The "forward 5 steps, backward 2 steps" means a state transition method in which the "error" is repeated 5 times, the status is "out of sync", and the status in which "match" is repeated 2 times is "sync". Show. Also, the position of the frame start bit indicated by the synchronization detection signal is "bit
If it is not in the 7 ”position, it is determined that the phases are out of phase,
The phase adjustment instruction is notified to the phase adjustment signal generation circuit 102.

When the phase adjustment signal generation circuit 102 receives the phase adjustment instruction, it generates a phase adjustment signal 52 indicating how many bits the phase is adjusted, and notifies the S / P conversion circuit 42 of it.

An embodiment of the FEC decoding circuit 44 will be described. Similar to the FEC encoding circuit 24, the code length is 63 bits, and the original data is a 57-bit data area 13
When 1 (only 56 bits are used) and the check bit (6 bits) calculated by the FEC encoding circuit 24, the syndrome derived by the Hamming code generation polynomial "X ⁶ + X + 1" is calculated.

The syndrome arithmetic circuit of the 1-bit FEC decoding circuit can be realized by the same structure as the 1-bit FEC encoding circuit shown in FIG. Therefore, the description is omitted. For the same reason as the 1-bit FEC encoding circuit, the LS
Since it is difficult to realize inside I, the number of parallel lines n
Minute FEC decoding operation is performed with one clock of the clock signal 51. Similarly, in the present embodiment, the number of parallel lines n
= 8. In the 1-bit FEC encoding circuit,
The order of inputting 8-bit input data serially is "bit
(7), bit (6), ..., Bit (0) ”, the FF value after 8 clocks can be similarly expressed by the equations (2-1 to 2-6). Previous 8
In the clock processing, the equations (2-1 to 2-6) are calculated in synchronization with the clock during 0T to 6T.

However, in the syndrome arithmetic circuit, 63
Since the bit code is input, the code is 57 in the last 7T.
~ To calculate the 63rd bit, the following formula (4-1 to 4
-6) is carried out. F (5) = F (4) + F (3) + bit (6) + bit (5)… (4-1) F (4) = F (3) + F (2) + bit (5) + bit (4)… (4-2) F (3) = F (2) + F (1) + bit (4) + bit (3)… (4-3) F (2) = F (5) + F (1) + F (0) + bit (7) + bit (3) + bit (2)… (4-4) F (1) = F (4) + F (0) + bit (6) + bit (2) + bit (1)… (4-5) F (0) = F (5) + F (4) + bit (7) + bit (6) + bit (1)… (4-6) By calculating the above equation in the above 7T, the final value of F (5) to F (0) becomes the syndrome (6 bits).

FIG. 6 shows an embodiment of the syndrome arithmetic circuit in the FEC decoding circuit 44 to which the above method is applied. The 8-bit input data 75 is converted into “bit (7), bit (6),
, ..., Bit (0) ”, and the calculation results held by the FFs (70-1 to 70-6) are described as“ F (0), F (1), ..., F (5) ”, respectively. The FFs (70-1 to 70-6) correspond to the FFs (110-1 to 110-6) of the syndrome arithmetic circuit. The 8-bit input data 75 also corresponds to the 1-byte bit string shown in FIG.

First, 63-bit data is divided into 8-bit units and input as input data 75 for each clock. The input data is 8 bits for 0T to 6T and 7 bits from bit (7) to bit (1) for 7T.

Next, the input data 75 is assigned to the inputs of the selectors (71-1 to 71-6) bit by bit. For example,
The input 0 of the selector 71-1 has “bit (6), bit (5),
Calculate and input the exclusive OR of 3 bits of "bit (0)". Input 1 is calculated by calculating the exclusive OR of 3 bits of "bit (7), bit (6), bit (1)". The selectors (71-1 to 71-6) and the selector 74 are
Input 0 is selected when "0T to 6T", and data input 1 is selected when "7T" is output.

The output values of the FFs (70-1 to 70-6) are input to the coefficient calculation circuit 72 and the coefficient calculation circuit 73. The coefficient calculation circuit 72 uses equations (2-1 to 2-6)
Of "F (0) to F (5)" is calculated, and the result is output to the input No. 0 of the selector 74. Similarly, the coefficient calculation circuit 73 also has “F (0) to F (5)” in the equations (4-1 to 4-6).
Only the corresponding portion is calculated, and the result is output to the input No. 1 of the selector 74. The selector (71-1 to 71-
6) and the output value of the selector 74 are respectively exclusive-ORed, and the result is held in the FFs (70-1 to 70-6).

By performing the above processing from 0T to 7T, the values F (5) to F (0) of the last remaining FFs (70-6 to 70-1) become the syndrome 76 (6 bits). .
The FEC decoding circuit 44 determines an error bit from the value of the syndrome 76 obtained by the syndrome calculation circuit, and inverts the bit to perform error correction. Finally, the error-corrected frame is sent to the descrambler circuit 46.

The BIP checking circuit 45 compares the BIP added by the BIP adding circuit 25 of the serial receiving unit 4 with the data of the received frame, and inspects the bit error. B
Similar to the BIP adding circuit 25, the IP checking circuit 45 performs an exclusive OR operation on the parallel data of the n-bit width of the received frame to obtain the parity, and compares the parity with the parity value stored in the BIP area 123. Then, the error bit position is obtained.

The descrambler circuit 46 is a scrambler.
Similar to the circuit 23, the generator polynomial “X ⁷+ X⁶+1 ”
The 7th-order pseudo-random value generated by
Data (FIG. 8). The frame of the input frame
Preset each shift register in synchronization with the frame signal
("1"). However, descrambling is a scramble
Of the frame data scrambled by the blur circuit 23
Performed only for the data area 130 (56 bits),
For data other than the above, leave it as it is without adding
The operation of the shift register is paused while it is passed.
It

On the write side, the reception frame buffer 7 receives parallel data on the parallel transmission lines (12-1 to 12-m) synchronized with the clock signal 51.
At this time, in synchronization with the frame signals running in parallel on the parallel transmission lines (12-1 to 12-m), the frame data area 131 (only the 56 bits storing the parallel data in the serial transmission unit 4) is stored in the frame buffer. Write in. The read side of the reception frame buffer 7 reads the frame data from the frame buffer in synchronization with the frame signal 56. The frame data is output to the parallel transmission line 10-2 in synchronization with the clock signal 55.

As described above, the serial receiving units (5-1 to 5-
m) converts serial data from the serial transmission units (4-1 to 4-m) into parallel data.

[0060]

As described above, according to the present invention, an encoding / decoding arithmetic circuit for a block code having a low encoding rate,
By using the scrambler circuit and the scrambler circuit, it is possible to provide a serial transmission method in which the transmission rate is suppressed to 1.25 times or less of the data rate and the error correction function and the DC balance guarantee are provided.

[Brief description of drawings]

FIG. 1 is an overall block diagram of the present invention.

FIG. 2 is a block diagram showing a transmission unit.

FIG. 3 is a block diagram showing a receiving unit.

FIG. 4 is a block diagram showing an embodiment of an FEC encoding circuit.

FIG. 5 is a block diagram showing an embodiment of a frame synchronization circuit.

FIG. 6 is a block diagram showing an embodiment of an FEC decoding circuit.

FIG. 7 is a format diagram showing an example of a frame format.

FIG. 8 is a block diagram showing an embodiment of a scrambler / descrambler.

FIG. 9 is a block diagram showing a general FEC encoding circuit.

[Explanation of symbols]

1 ... LSI. 2 ... Serial transmission line. 3 ... LSI internal logic circuit. 4 ... Serial transmission unit. 5 ... Serial receiver. 6 ...
Transmit frame buffer. 7 ... Receive frame buffer. 1
0, 11, 12 ... Parallel transmission lines. 20 ... PLL circuit.
21 ... Divider circuit. 22 ... Frame generation circuit. 23 ... Scrambler circuit. 24 ... FEC encoding circuit. 25 ... BIP
Application circuit. 26 ... P / S conversion circuit. 30, 31, 32 ...
Clock signal. 35 ... Frame signal. 40 ... CDR circuit. 41 ... Dividing circuit. 42 ... S / P conversion circuit. 43 ... Frame synchronization circuit. 44 ... FEC decoding circuit. 45 ... BI
P test circuit. 46 ... Descrambler circuit. 50, 51 ...
Clock signal. 52 ... Phase adjustment signal. 53 ... Frame signal. 55 ... Clock signal. 56 ... Frame signal. 60 ...
FF. 61 ... Selector. 62, 63 ... Coefficient calculation circuit. 6
4 ... Selector. 65 ... Input data. 66 ... Check bit.
70 ... FF. 71 ... Selector. 72, 73 ... Coefficient calculation circuit. 74 ... Selector. 75 ... Input data. 76 ... Check bit. 100 ... Sync pattern detection circuit. 101 ... Sync protection state circuit. 102 ... Phase adjustment signal generation circuit. 105 ...
Sync detect signal. 110 ... FF. 120 ... Sync pattern area. 121 ... Reserved area. 122 ... Payload area.
123 ... BIP area. 130 ... block. 131 ... Data area. 132 ... FEC area. 133 ... DC balance guarantee bit. Final bit 134.

Continued front page    F term (reference) 5J065 AA01 AA06 AB01 AC02 AD04                       AD05 AD08 AE01 AE02 AF01                       AG02 AH02 AH03 AH04 AH05                       AH09 AH14 AH18                 5K014 AA01 BA06 EA07 FA10                 5K029 AA11 BB03 CC01 DD02 DD12                       DD23 DD28 DD29 EE06                 5K047 AA11 BB04 HH01 HH21 MM02                       MM11 MM14 MM46 MM55

Claims (3)

[Claims] 1. A serial data transmission system using a serial transmission path, comprising: a transmission frame buffer, one or a plurality of serial transmission units, one or a plurality of serial reception units, and a reception frame buffer, The serial transmission unit includes a frame generation circuit that generates a frame that contains parallel data, a scrambler circuit that randomizes the data to ensure DC balance on the serial transmission path, and a data scrambler that performs bit error correction. And a FEC encoding circuit for giving a check bit to the serial receiving unit. The serial receiving unit detects a synchronization pattern stored in a frame, determines a division of the frame from the position of the synchronization pattern, and determines a frame synchronization frame. A synchronization circuit,
An FEC decoding circuit that identifies error bits from the data stored in the frame and the check bits and corrects the error bits, and a descrambler circuit that restores the original data from the data randomized by the scrambler circuit are provided. , A serial transmission system characterized in that 2. The FEC encoding circuit performs the processing performed by the encoding circuit using the shift register based on the block code generator polynomial from the xth clock to the x + n−1th clock in one clock and outputs the result. It is held in FF, and in the next clock, based on the result of the previous clock held in FF,
2. The encoding circuit performs processing performed from the (x + n) th clock to the (x + 2n-1) th clock.
Serial transmission method described in. 3. The FEC decoding circuit performs the processing performed by the shift register decoding circuit based on the block code generator polynomial from the xth clock to the x + n−1th clock in one clock and outputs the result. It is held in FF, and in the next clock, based on the result of the previous clock held in FF,
2. The decoding circuit performs a process from the x + nth clock to the x + 2n−1th clock.
Serial transmission method described in.