JPH11122084A - Pseudo-random pattern generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PV pattern generation circuit capable of outputting both serial/parallel PV patterns (pseudo-random patterns) at all times with a single circuit. SOLUTION: The output terminal of an EXOR 12 is connected to the set terminal of a first F/F11a and the set terminal of a second F/F11b is connected to an output terminal. Similarly thereafter, the output terminals of respective F/Fs are connected to the set terminal of F/F of the next stage. Then, the output terminals of a fifth F/F11e and a ninth F/F11i are connected to the input terminal of the EXOR 12. Also, to the reset terminals of the respective F/Fs11a-11i, clock signals are supplied. In this PN pattern generation circuit constituted in this way, the serial PN pattern is taken out from the output terminal of the ninth F/F11i, and the parallel PN patterns D1-D8 are taken out from the output terminals of the second F/F11b to the ninth F/F11i.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial / parallel pseudo-random (PN) pattern generation circuit applicable to a transmission apparatus for detecting and measuring transmission errors.

[0002]

2. Description of the Related Art Normally, a PN pattern is required to monitor n (n = 2, 3,...) Parallel data D1 to Dn in units of signal lines and all bits. And
In order to monitor the n parallel data D1 to Dn in units of signal lines, a PN pattern in which data flows serially as shown in FIG. 3 is required.
To monitor Dn, a PN pattern in which data flows in parallel as shown in FIG. 4 is required. For this reason, conventionally, FIG.
As shown in FIG. 1, a serial / parallel PN pattern generation circuit capable of generating both patterns has been used.

A conventional serial / parallel PN pattern generation circuit of this kind has a serial PN pattern GEN (GEN is a generator unit, the same applies hereinafter) 51 and a parallel PN pattern GEN 52. Both PN patterns GEN5
The outputs of 1 and 52 are output from n serial / parallel selectors 5.
3a to 53n.

[0004] Serial / parallel selectors 53a to 53n
Are provided with a switching signal for switching the two PN patterns to either serial or parallel depending on the unit of data to be monitored, and the switching signals provide desired output signals D1,... Dn-1, Dn. Is sent.

FIG. 6 is a configuration diagram of a main part of the serial PN pattern GEN51. The serial PN pattern GEN51 is
The flip-flops F / F are connected in series, and a serial PN pattern is obtained from the last stage F / F. Also,
The output of the last stage F / F and the output of the i-th stage F / F are input to an exclusive OR gate (hereinafter, EXOR).
The OR output is fed back to the first stage F / F.

FIG. 7 is a configuration diagram of a main part of the parallel PN pattern GEN52. The parallel PN pattern GEN52 is
The serial PN pattern is configured such that the output of the EXOR is input to all the F / Fs, a parallel PN pattern is obtained from the output of each F / F, and the output is fed back to the input stage of the EXOR. Different from GEN51.

[0007]

SUMMARY OF THE INVENTION
In the parallel PN pattern generation circuit, the serial PN
In order to output a pattern and a parallel PN pattern, both P
N patterns GEN51 and GEN52 must be provided. In particular, the parallel PN pattern GEN52 is
Since a multi-stage EXOR is required for each parallel, when the operation speed increases, the timing becomes strict and retiming is required, and there is a problem that the circuit becomes complicated.

Further, since it is necessary to switch the output of the serial / parallel PN pattern by a switching signal, there has been a problem that monitoring cannot be performed simultaneously in units of signal lines and in units of all bits.

It is an object of the present invention to provide an improved PN pattern generation circuit which can always output both serial / parallel PN patterns by a single circuit.

[0010]

A PN pattern generating circuit according to the present invention for solving the above-mentioned problems has an n-bit cyclic shift register provided with an EXOR in a feedback system,
A serial PN pattern is output from the last-stage register of the cyclic shift register, and a parallel PN pattern is output from an output terminal of each register simultaneously with the serial PN pattern. .

The output of the last stage register and the output of the predetermined register are supplied to the input of the EXOR.
The output from R is configured to return to the input of the first-stage register. The parallel PN pattern and the serial PN pattern are always output from individual registers.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 illustrates the present invention with a PN
FIG. 9 is a block diagram showing an example in which the present invention is applied to a 9-stage 8-parallel serial / parallel PN pattern generation circuit.

In FIG. 1, 11a, 11b to 11i
Are the first to ninth flip-flops F / F constituting an n (n is a natural number of 2 or more) bit cyclic shift register;
An EXOR 12 is inserted into the feedback system of the shift register.

EXO is connected to the set terminal of the first F / F 11a.
The output terminal of R12 is connected to the second F /
Connected to the set terminal of F11b. Similarly,
The output terminal of each F / F is connected to the set terminal of the next F / F. Then, the fifth F / F11e and the ninth F / F11
The output terminal of i is connected to the input terminal of EXOR12. A clock signal is supplied to the reset terminals of the F / Fs 11a to 11i.

In the PN pattern generation circuit configured as described above, the serial PN pattern is the ninth F / F 11i.
Of the parallel PN patterns D1 to
D8 is taken out from the output terminals of the second F / F 11b to the ninth F / F 11i.

The operation of obtaining the above-described serial PN pattern from the PN pattern generation circuit of the above-described embodiment is well-known, so that the description is omitted here, and the case of PN 9-stage 8-parallel is described below.

Since the PN9-stage generator polynomial is X 9 + X 5 +1, the PN9-stage generator is composed of a 9-bit shift register having feedback by the EXOR 12 shown in FIG. The output of the ninth F / F11i is a normal PN9-stage pattern, but the eighth F / F11h
Is a pattern from the second bit of the PN9 stage, and the output of each F / F thereafter is a pattern of the PN9 stage delayed by one bit. The second F / F11b to the ninth F / F1
The eight output terminals of 1i are taken out as D1 to D8, and D8
, A PN pattern as shown in FIG. 2 is generated.

Looking at the PN pattern shown in FIG. 2 in units of signal lines, D1 to D8 have different start bits,
Since the flow of the pattern is correct, it can be regarded as a PN pattern. Also, when viewed in units of all bits, it cannot be regarded as a PN pattern, but when viewed at 7-byte intervals, the PN pattern looks correct as indicated by the arrow in the figure. Since the PN pattern is also a PN pattern for each signal line at the same time, the receiving side can simultaneously monitor the signal line unit and the 7-byte unit, and can be sufficiently used as a PN pattern for all bits.

As described above, according to the PN pattern generation circuit of the present embodiment, a highly random bit sequence can be generated by the n-bit cyclic shift register having the feedback by the EXOR 12. Further, since both the serial / parallel PN pattern can be generated only by the components that generate the serial PN pattern, the circuit configuration can be simplified regardless of the operation speed, and the serial / parallel PN pattern is always output. Therefore, there is an advantage that monitoring can be performed simultaneously in units of signal lines and in units of all bits.

[0020]

As is apparent from the above description, according to the present invention, it is possible to provide a PN pattern generating circuit capable of constantly outputting both serial and parallel PN patterns by a single circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PN 9-stage 8-parallel serial / parallel PN pattern generation circuit showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a serial / parallel PN pattern.

FIG. 3 is an explanatory diagram showing a data flow of a PN pattern in signal line units.

FIG. 4 is an explanatory diagram showing a flow of data of a PN pattern in units of all bits.

FIG. 5 is a block diagram showing a conventional serial / parallel PN pattern generation circuit.

FIG. 6 is a circuit diagram of a serial PN pattern generator.

FIG. 7 is a circuit configuration diagram of a parallel PN pattern generator unit.

[Explanation of symbols]

 11a, 11b to 11i F / F 12 EXOR (exclusive OR gate)

Claims (3)

[Claims] An exclusive-OR gate has an n-bit cyclic shift register provided in a feedback system, and a serial pseudo random pattern is output from the last register of the cyclic shift register. A pseudo-random pattern generating circuit configured to output a parallel pseudo-random pattern simultaneously with a serial pseudo-random pattern from an output end of the pseudo-random pattern. 2. The input of the exclusive OR gate is supplied with the output of the last register and the output of a predetermined register, and the output from the exclusive OR gate is fed back to the input of the first register. 2. The method according to claim 1, wherein:
The described pseudo-random pattern generation circuit. 3. The apparatus according to claim 1, wherein said parallel pseudo-random pattern and serial pseudo-random signal are always output from output terminals of said individual registers.
The described pseudo-random pattern generation circuit.