JP3114101B2 - Inspection pattern generator - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a test pattern generator for use in a method for in-subscriber measurements of an integrated services digital network (ISDN) system.

[Conventional technology]

ISDN systems can be divided into so-called subscriber ranges and ISDN operator ranges. The boundary between these two ranges is formed by the end of the network. From this network end, a data bus line passes through the subscriber's space. Network termination or data bus has standardized interfaces various terminal devices can be connected, a so-called S ₀ interface. The S ₀ interface are 4-wire interface for bidirectional data exchange between the one or more terminal devices of the network terminating the subscriber. A so-called AMI-NRZ code is used as the transmission code. That is, if the “0” bit is + 0.75V or −
This is a pseudo ternary code represented by 0.75V and “1” bit by 0V. Successive "0" bit pulses have essentially alternating polarities. The data to be transmitted, as well as the synchronization and control data, are combined into a 250 μs long transmission frame. The start of such a transmission frame is indicated by a code loss. The sign defect is that two consecutive "0" bit pulses have the same polarity. This code deficiency is reliably recognized by the terminal device, thus providing a simple and quick synchronization of the terminal device with the network termination.

Now, for example, before a terminal device can receive or transmit data, it is necessary to establish a corresponding connection by a defined procedure. The transmission channel must therefore be made transparent, i.e. be prepared for the transmission of data, along with said synchronization of the transmission frame.
This procedure, also called activation, consists of the alternate transmission and reception of a specific defined data sequence (hereinafter referred to as Info) between the terminal and the network termination. These components for the special control module, S ₀ bus controller (SBC) and ISDN communications controller (IC
C). The SBC module controls the activation or deactivation procedure. This control is monitored by the internal time setting of the timer. This means that the corresponding Info will always be output only for a certain duration, during which the specific Info must be sent in response to the Info received from the corresponding component. Must. In doing so, the Info to be sent as a reply from the corresponding component is specific to the Info previously received by it, so that each procedure is characterized by a defined hierarchy of Info. If the establishment of the connection (activation) described above as an example is to start from a terminal, the terminal first sends a first sequence of data, called Info1, to the network termination. This is the normal case for receiving the data string Info1
It reacts by sending another data stream called the. This answer must be made during a specific time and
The transmission of 2 occurs only for a limited time. During this time, the terminal device again receives another data string Info3
Must be responded to by transmitting the data string Info4 again from the end of the network. If the Info sent as a reply from the corresponding component does not correspond to the Info to be expected according to the hierarchy (eg sending Info4 as a reply to Info1), the expected Info
Does not arrive during the predetermined time, or the procedure of the subscriber terminal is not started by Info1, so the procedure is interrupted and the S data bus is again in the initial state, ie the disabled dynamic state.

This behavior is conditioned by SBC or ICC module (according to German MPT standard 1TR3 that contains rules for measurements in e.g. S ₀ interface) makes it difficult to measure. Info can only be obtained for a limited time, i.e. for the defined maximum transmission duration or until the expected arrival of the Info, and thus also for the measurement of the response of the corresponding component. Not available. In addition, when measuring Info's hierarchical order, they are required to occur in a particular procedure. In addition, these modules can only produce certain defined Info used in the operating procedure of the system.

These difficulties are caused by "Siemens-P Tester K" instead of network termination or subscriber terminal.
rotokolltester) 1195 ”,“ Siemens-Telecom-
Report (Siemens Telcom Report) 11 ”March 1988-
April, No. 2, pages 61-64, especially page 62, right column, last two paragraphs to page 64, also occurs when used as described in the first three paragraphs . The measurements described there are indeed also measured at the _S0 interface, but in this case the subscriber terminal or network termination is disconnected from the data bus located within this range,
Also, with the protocol tester K1195 connected and the range activated by Info, the protocol measurement task is simply solved and no measurements are made in the physical plane.

[Problems to be solved by the invention]

The present invention, starting from this prior art, S ₀ and the network termination, which is standardized with standardized S ₀ interface
The response of a component of a subscriber range having at least one subscriber terminal having an interface and a data bus for alternating exchange of data strings between the network termination and the subscriber terminal is predefined. A test pattern generator for measuring in a data stream, wherein a subscriber terminal and / or a network end are disconnected from a data bus and S ₀
The present invention relates to a test pattern generator for a data bus for generating a data sequence that plays a role in forming a connection within an interface.

The object of the present invention is to provide a configuration in which the interface of the subscriber unit or the network termination and the data bus can be monitored in a measuring manner.

[Means for solving the problem]

This problem is solved according to the invention by the use of a test pattern generator which can independently generate each of the data strings serving as connections for a desired duration.

(Effects)

In the method according to the invention, the interface and the data bus at the subscriber unit or at the end of the network are not restricted with regard to the duration, sequence and order of the data sequence (Info) output from the test pattern generator for measurement purposes. It can be tested advantageously in terms of measurement technology. That is, a sequence of data from the component to be examined is required as a response and can be indicated or evaluated by a measuring device, which may consist of an oscilloscope or a frequency counter, for example, according to German Federal Ministry of Posts and Telecommunications Standard 1TR3 Its duration is not restricted by procedural rules. This is achieved by the continuous transmission of the data sequence (Info), that is to say by continuously transmitting the data sequence without being affected or interrupted by the data sequence (Info) transmitted back as an answer from the component to be examined. It is possible. further,
The component to be examined can be given an arbitrary sequence of data sequences, wherein the sequence of the data sequences is not predetermined by the hierarchy of the interface-specific procedure.

An advantageous embodiment of the method according to the invention consists in using a test pattern generator which can output at least one freely definable data sequence. Thereby, there is an advantageous possibility of transmitting a freely definable data sequence required for measurement purposes, so that the data sequence (Info) defined by the interface-specific procedure cannot be used as a test pattern. Or insufficient measurements may be taken.

An advantageous embodiment of the method according to the invention consists in using a test pattern generator which can output control and / or identification data in synchronization with a data stream on at least one data output channel. Thereby, the possibility of characterizing a particular information unit (Bit) of the data sequence (Info) in an advantageous manner is provided, so that at the same time as the particular information unit (Bits) via at least one data output channel The identification data is output in the form of, for example, "1" bits. In the same way it can also characterize complete sections of the data sequence (Info). Furthermore, synchronization and control signals can be output, for example, to the measuring device upon the occurrence of a particular information unit (Bit) of the data stream.

The test pattern generator of the present invention includes a memory capable of individually outputting a data sequence serving as a connection forming at least within the range of the _S0 interface for a desired duration, and is connected to the memory and has a desired configuration. Has a control unit that can select the individual data strings of

The control unit can be provided in an advantageous manner with information about the data sequence to be selected on the input side, and with the address input of the memory via a jump element (trigger element for triggering the next stage) on the output side. And the data output of the memory is connected to the release (enable) input of the jump element. The control device is then provided on the input side, for example, with the digital code of the number of the desired data sequence. With this circuit arrangement, it is possible to select a data sequence in any order and duration. This is made possible by the fact that the control unit can be provided with any sequence of information on the input side and with the same information arbitrarily long. If at least one freely definable sequence of data is required for measurement purposes, this at least one
Two freely definable data strings are also stored in the memory. Particularly suitable is a memory from which selected data strings can be read out sequentially. To this end, a preselection (offset) provided by the control unit takes place, in which the memory cell containing the first data bit of the desired data sequence responds to the address thus defined. Subsequent memory cells are read out one after another by the clocked up-counter module until the address of the memory cell containing the last data bit of the data string is reached. If the data stream is to be read anew, for example during a continuous transmission of the data stream, a clock-synchronous reset of the counter takes place and the reading process starts at the newly preselected (offset) address.

In an embodiment for implementing the present invention, an erasable and rewritable memory module is provided as a memory. Thereby, the possibility of changing the data sequence used for measurement purposes and thereby adapting to the changed measurement purpose is advantageously obtained. In this module, for example, a data sequence edited by a corresponding computer program can be written relatively easily, in which case the internal RAM memory of the computer can also be used. As a memory module, for example, an EPROM module is also suitable.

〔Example〕

Hereinafter, the structure and operation of the inspection pattern generator according to the present invention will be described in more detail with reference to the drawings.

According to FIG. 1, the test pattern generator includes a clock generator TG, which clock pulse CLK is supplied via a line 1 to a terminal 2 of the control unit ST. The control unit ST includes a clock selection device TA having another terminal 3 to which an external clock generator, not shown, can be connected. The terminal 2 of the control unit ST is formed by one input terminal of a logical OR element 4, and the terminal 3 of the control unit ST is formed by one terminal of another logical OR element 5. Each other input of the logical OR element 4 or 5 is connected to a terminal INT or EXT, respectively, which is associated with a switch position inside or outside the switch S1. Third that is associated with terminal AUS on switch S1
Switch position. The output of the logic OR element 4 or 5 is led to the input of an AND element 6, whose output forms the clock output 10 of the control unit ST. Inverted clock CL from another output of control unit ST
K 'can be extracted. The control unit ST has another switch S
2 and subsequently connected priority encoder P
E, whose input is provided with 0 or +5 V depending on the position of the switch S2, and whose output forms the outputs 13 to 16 of the control unit ST. The outputs 13 to 16 are led via a first clocked jump element (trigger element for triggering the next stage) KG1 to the address inputs A8 to A11 of the memory module SP. The data output terminal D0 of the memory module SP is a jump element KG
It is led to a release (enable) input 20 of one.
The release input terminal 20 is a control terminal for releasing the jump element KG1, that is, releasing the jump element KG1, and selectively outputting the input of the jump element KG1. The address inputs A0 to A7 of the memory module SP are connected to the outputs A to H of the 8-bit binary counter BZ. This 8-bit binary counter is composed of two cascaded 4-bit binary counters each having a clock synchronous reset input CLR. The binary counter BZ is provided with a clock CLK at its clock input TBZ. The reset input terminal CLR is connected via an AND element 21 to the data output terminal D0 of the memory module SP and the terminal AUS of the switch S1. Data output terminals D1 to D6 of the memory module SP
Are led to the inputs 25 to 30 of the second jumping element KG2. The clock input 31 of the jump element KG2 is connected to the control unit ST
, And is supplied with the inverted clock signal CLK '. Output end of jumping element KG2
NRZ1 and NRZ2 are two driver modules 40 and 41
Through to the terminal of the primary winding of the transformer TR. The secondary winding of the transformer TR has two connection points 50 and 51 which are simultaneously the output points of the test pattern generator, to which the data bus to be tested is connected at two inputs. Jumping element
Another output SR of KG2 is led via another driver module 52 to a connection point 53 of the data output channel S0. This connection point 53 also forms the output point of the test pattern generator.
The three further outputs 54, 55 and 56 of the jump element KG2 are led via data output channels 60, 61 and 62 to terminals 63, 64 and 65 on the other outputs of the test pattern generator. The driver modules 40, 41 and 52 have a release input 70 connected to the output of the clock monitoring circuit T,
71 and 72 are provided. Clock monitoring circuit T
Includes two monostable after-triggerable jump elements 75 and 76 which are provided at their inputs with a clock pulse CLK or an inverted clock pulse CLK '.

The manner in which the test pattern generator functions will be described in more detail in connection with the signals shown in FIG. 2 at key points in the circuit of FIG. In this case, the row a) includes the clock pulse CLK applied to the output 10 of the control unit ST.
However, row b) shows an inverted clock pulse CLK 'which can be taken from the output 12 of the control unit ST. Row c) shows the time course of the signal output at the output D0 of the memory module SP, rows d) and e) show the signal at the data output D1 or D2 of the memory module SP or the output NRZ1 of the jump element KG2 and The progress of the output terminal of NRZ2 is shown. Row f) shows the output signals that can be extracted at the nodes 50 and 51 after the transformer TR.
Row g) shows, in this example, a bit sequence in the form of individual logic states of 8 bits read from the memory module SP. The complete data string (for example, Info1) is 48
For example, Info1 consists of six repetitions of the bit sequence shown in row g). To improve the view, all data columns (Info1) are shown in row h). When the switch S1 (FIG. 1) of the clock selector TA is in the position INT, the test pattern generator generates the clock CLK generated by the clock generator TG provided to the output 10 or 12 of the control unit ST.
Alternatively, an inverted clock CLK 'is supplied. A data string (for example, Info1) to be output is selected by the switch S2. The address inputs A8 to A1 of the memory module SP via the priority encoder PE and the jump element KG1
One is given a bit pattern corresponding to the selected data sequence (eg, Info1). Thereby, the first memory cell to be read is defined. As can be seen from line c) (FIG. 2), at the end of the first clock 1, the end of the reset signal for the 8-bit binary counter BZ output from the data output D0 of the memory module SP is output. You. The first clock of the memory module SP is generated by the second clock.
, And therefore also the first bit of the data string (Info1). During the second clock, a positive pulse occurs at data output D2 (row e), FIG. 2), whereas no pulse is observed at data output D1. During the following six clocks (3 to 6), no pulse is recognized at the data output terminal D1 or the data output terminal D2. During the ninth clock, a positive pulse (row d, FIG. 2) appears at the data output D1. The signals occurring at the output NRZ1 or NRZ2 of the jump element KG2 in response to the signals at the data outputs D1 and D2 provided at the inputs 25 and 26 are supplied to the transformer TR via the driver module 40 or 41. . On the output side, an output signal indicated by an AMI-NRZ code can be extracted from the terminals 50 and 51. Thereby, in the selected example, the bit sequence shown in row f) has been read,
This forms a part of the data string to be read (Info1 in this example). Such a data string consists of a total of 48 bits, so in the present example another 40 bits should be read from the memory module SP in a similar manner. On reaching the last bit to be read (bit 48) of the data train, a pulse output is produced on the data output D0 (first clock, row c), FIG. 2). Pulse is binary counter BZ
And also transmits the bit pattern given to the jump element KG1 on the input side to the address input terminals A8 to A11 of the memory module SP according to the position of the switch S2. If the transmission of the data sequence is desired, the switch S2 of the control unit ST remains in the unchanged position and the reading of the same memory range starts anew. If the position of the switch S2 has been changed during the intermediate time, a bit structure corresponding to the new switch position will appear at the output of the jump element KG1 by the clock and thus also via the data output D0 of the memory module SP. Is applied to the release input terminal 20 of the jump element KG1 and is applied to the address preselection input terminals A8 to A11 of the memory module SP. Thus, at each time point, a new data string to be read (Info) by the switch S2
Can be determined, and that the data string to be read instantaneously is read to the end without being affected. The data output to the data output terminal D3 of the memory module SP is guided to the connection point 53 of the data output channel S0 via the jump element KG2 (output terminal SR) and the driver module 52, and identifies a specific position of the data string. the role of as the S ₀ frame pulse for. That is, this frame pulse is output at the start of the transmission frame and allows the defined start of the frame to be recognized during the measurement. During each clock from the memory module SP, the data output channels 60, 61 and 62 are retrievable from the data outputs D4, D5 and D6 and via the jump element KG2.
Can be read out. These data may fulfill additional functions, such as control of the measurement hardware, identification of specific information units (bits) or sections of the data sequence.

A freely defined data sequence can be read from the memory module SP in the same way. At this time, the data string may be the same as the interface-specific procedure data string except for a code loss indicating the start of a frame. By means of the switch S1, it can be switched to an external clock source which can be connected to the terminal 3 of the control unit ST for a specific measuring purpose. Switch S1
Also serves to switch off the test pattern generator, at which time the 8-bit binary counter BZ is reset. In the event of a clock (internal or external) stop, one of the two monostable elements 75 or 76 of the clock monitor T is no longer triggered, and the clock monitor TU is connected to the release input 70 of the driver module 40, 41 and 52. , 71 and 72 to drive the driver modules 40, 41 and 52 to a high resistance state.

As described above, according to the present invention, the connection relationship between the memory constituting the test pattern generator and the jump element (trigger element) which mediates the output of the control unit to this memory is determined by the plurality of address input terminals of the memory. Coupled to the element and one of the data outputs of the memory is coupled to the release input of the trigger element, so that even if the input to the trigger element is switched during the generation of a data stream from the memory, The data string read from the memory can be reliably read to the end without being changed halfway. Therefore, the inspection pattern of the ISDN system can be reliably generated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a test pattern generator according to the invention for carrying out the method according to the invention, and FIG. 2 is a signal sequence occurring at an important point of the circuit during operation of the test pattern generator according to FIG. FIG. KG1, KG2… jumping element (trigger element) PE… priority encoder SP… memory module ST… control unit TA… clock selection device TG… clock generator TR… transformer TU… clock monitoring device

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-1230 (JP, A) JP-A-61-239729 (JP, A) JP-A-2-26449 (JP, A) JP-A-2- 299351 (JP, A) JP-A-2-272957 (JP, A) JP-A-63-276949 (JP, A) JP-A-62-222755 (JP, A) US Patent 5319631 (US, A) European Patent 435873 (EP, B1) International Publication No. 90/3707 (WO, A1) West German Patent Application No. 3832491 (DE, A1) Telecom Report Vol. 11 No. 2 p61-64 (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 12/02 H04M 3/26-3/32 H04M 11/00

Claims (1)

(57) [Claims] An integrated services digital network (ISDN) system is connected to a standardized So interface, and at least one subscriber terminal is connected to the standardized So interface.
Connected to the So interface and the data bus, exchanges a data sequence between the network terminal and the minimum number of one subscriber terminal device in two directions, and switches the subscriber terminal device or the network terminal to the Disconnecting the test pattern generator from the data bus and connecting a measuring device to the data bus to measure a response from a component of the subscriber range to a plurality of selected data strings; And the subscriber range of the So interface is
Generating a plurality of data strings for use in connecting to a bus, generating individual data strings for use in connection setting during a measurement period related to the measurement of the response, and generating a plurality of data strings for the plurality of selected data strings; A test pattern generator used to measure a response from a component part of a subscriber range of an ISDN system, and generates a plurality of data strings used individually for connection setting in the range of the So interface during a desired period. A memory, a control unit connected to the memory for controlling the selection of a desired individual data stream, and a trigger element having a release input, the control unit receiving an information by the selected data stream. And an output coupled to the trigger element, the memory comprising: a plurality of address inputs coupled to the trigger element; and a relay for the trigger element. A test data generator having a single data output coupled to the input.