RU2299474C2 - Device for generating and transmitting a series of signals - Google Patents

Abstract

FIELD: multifunctional information and control complexes, possible use for generating informational message, containing data about condition of two-positional objects - executive mechanisms, intruder and fire alarms, and also timed series of changes of these.

SUBSTANCE: device is characterized by increased trustworthiness of information due to combined procedures of input and encoding of signals from indicator. Input and encoding of information are performed in two stages - at first stage, current signal values from indicators are recorded in RAM registers, and at second stage signal input and signal encoding procedures are combined with serviceability diagnostics of common and individual units of device and circuits for connecting encoder and sensors. Special feature of proposed device - recording of short-term signals and timed series of their changes, allows its usage as recorder of emergency processes. Device allows usage of telecontrol communication channels.

EFFECT: expanded functional capabilities.

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Description

The invention relates to information and control systems and can be used to encode and sporadically transmit information about the current state of discrete signal sensors that display the state (position) of on-off actuators (sensors), security and fire alarm circuits, as well as to transmit information about the sequence of changes specified signals. Data on the time sequence of changes in signals from sensors allow the use of the proposed device for the analysis of an emergency (emergency) situation. The information message is represented by a serial code, so telemechanical communication channels can be used to transfer data to an external device.

Closest to the proposed one is a device for sporadic transmission of television alarms according to copyright certificate No. 1260996 (M.L. Portnov et al., Bulletin No. 36, 1986), which contains a power source, a block of signal sensors, consisting of individual nodes for each of “N” sensors, first, second and third switches, a parallel to serial code converter consisting of a multiplexer and a first counter, a clock generator, a first allocator, a register - RAM, a serial code comparator, first minutes, second and third flip-flops, the first and second pulse shapers, first, second, third, fourth, fifth, sixth and seventh OR elements, first and second AND gates, a delay element.

The prototype device provides dynamic control of the health of common nodes by conducting two test modes, which ensures the receipt, respectively, of signals "1" and "0" at all individual outputs of the sensor block. In the input and processing mode of real and test signals, the same elements of the device are used, due to which the diagnostics of the operability of the nodes common to all signals is achieved. For this, a non-zero ("U") output of the power source is connected to the first inputs of the first and second switches, and a zero ("0") output is connected to the second input of the second switch, the combined second outputs of the nodes of the signal sensor block are connected to the output of the first and second output of the second switches, and the first individual outputs of the nodes of the signal sensor block are connected to the information inputs of the multiplexer, in which the address inputs are connected to the corresponding main outputs of the first counter and register - RAM, and the output - with the first output of W cerned switch and the input of the third switch, whose output is connected to the first input of the comparator consecutive codes, a second input connected to the first output of the first flip-flop, which is an output "data" of the device, the fifth output of the first distributor is connected to the input of the delay element.

In the prototype device, increasing the reliability of the data is provided by dynamic monitoring of the health of common nodes.

The disadvantage of the prototype device is the lack of diagnostics of the health of individual coding and communication circuits with sensors and the fixation of short-term signals from the sensors and the time sequence of their changes, which does not allow the use of the prototype device to register an emergency (emergency) situation.

The essence and purpose of the invention is to expand the functionality of the device by diagnosing the health of individual communication circuits with sensors, as well as responding to short-term changes in signals from sensors and fixing their time sequence.

To implement the performance monitoring of individual catches, the input and coding procedures are combined, for which an additional first diode is inserted into the individual nodes of the signal sensor block, connected in series with the output element (contact) of the sensor, and a second serial circuit from the sensor and the first additional diode is connected in parallel the second diode and reference element is a zener diode. The direction of inclusion of the diodes in the first and second circuit is opposite. A survey of the state of sensors, combined with coding procedures, is carried out in two stages. At the first stage of polling and coding, a signal is formed alternately for each sensor, which passes through a circuit including the first diode and the output element (contact) of the sensor. A code signal that displays the recorded current (instantaneous) state of the sensor is entered in the register - random access memory (RAM). If the sensor contact is closed, at the first stage a signal “1” is generated, otherwise - a signal “0”. After the completion of the first stage of the survey and coding of the current states of all sensors, the second stage is carried out. At the second stage, a signal is formed alternately for each sensor, which passes through the circuit from the second diode and the zener diode of the signal sensor node, and the polling signal level for each sensor depends on the signal recorded at the first stage of polling the state of this sensor. If at the first stage a signal “1” was recorded, which corresponds to the closed state of the sensor contact (output element), a relatively low level signal is generated at the second stage in order to determine the absence of a short circuit in the sensor communication circuit with the corresponding encoder input. If the communication circuit is closed, i.e. the threshold element - the first zener diode is shunted, the signal of a relatively low level is higher than the encoder sensitivity threshold. As a result, the input and coding unit of the signal, and in the second stage being carried out, will record the “1” signal from the sensor unit. The combination of signals “11” obtained at the two stages of polling and coding the status of the corresponding sensor will be decrypted as a malfunction - a short circuit in the communication circuit of the encoder with the polled sensor. In the absence of the indicated malfunction, at the two stages of polling and coding, a combination of signals “10” will be generated, which will be decrypted by the receiver as the closed state of the sensor and the absence of a malfunction in the communication circuit with it.

If the signal “0” is received from the sensor at the first stage of polling and coding, at the second stage, an open circuit is connected between the sensor and the encoder. To do this, the level of the polling signal, which is fed to the second diode and the first zener diode, increases by an amount greater than the value of the threshold of the zener diode. If the communication circuit of the interrogated sensor with the encoder is not broken, the level of the polling signal is greater than the threshold signal, and the signal “1” will be fixed by the encoder. As a result, at two stages of polling and coding the corresponding sensor, a pair of signals “01” will be generated, which is decrypted by the receiver as the open state of the sensor and the absence of an open circuit in the communication with it. If the communication circuit of the encoder with the interrogated sensor is broken, a pair of signals “00” is formed at two stages of encoding, which is interpreted by the receiver as a malfunction - an open circuit in the communication circuit with the sensor.

The pairs of signals formed at the two stages of polling and coding the status of each sensor: “10” or “01” - in the absence of a malfunction, “11” or “00” - when a malfunction of the general or individual circuit is detected, are entered in the corresponding register cells - RAM. Information from the register - RAM, after the device issues a “request” signal and receives a “transfer” signal, is sent to the “data” output of the device, accompanied by “clock” and “data output” signals.

When two stages of polling and coding are implemented, the same device nodes are used, and for all common and individual circuits, conditions are created under which signals of different levels must be generated (“1” and “0”), which maximizes the depth of diagnostics of the health of elements devices.

To respond to short-term input signals, the proposed device generates two types of data: “data 1” - information about the current values of the signals from the sensors, “data 2” - information including data on the change in the state of the sensors and the time sequence of these changes. “Data 2” is accompanied by time stamps, which allow identifying in an external device - a receiver of information, the real time of “events” - moments of change in the state of the sensors. To identify the type of data generated, the device transmits two request signals to the external device - “request 1” or “request 2”. The data is output to the device in accordance with the transmission permission signal received from the external device - “transmission 1” or “transmission 2”.

To ensure the diagnosis of individual nodes, the device, in contrast to the prototype, introduces a second distributor, the eighth and ninth elements OR, the first and second elements AND-NOT, element OR-NOT, element EXCLUSIVE OR.

To implement the objective of the invention in terms of response to short-term signals, a unit for generating data on changes in signals from sensors accompanied by time stamps is introduced into the device. The data generation unit includes the second, third, fourth, fifth and sixth counters, the fourth and fifth switches, a parallel code comparator, the third distributor, the fourth and fifth triggers, the first, second, third, fourth, fifth and sixth elements NOT, the third, fourth, fifth, sixth, seventh, eighth and ninth elements AND, first and second decoders, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth elements OR, second register - RAM, register - parallel to serial converter spruce.

Figure 1 shows a diagram of an input unit, encoding signals from sensors of discrete signals used to generate and transmit data about the current values of the signals. Figure 2 shows a block diagram that provides for the fixation of short-term signals from sensors and the transmission of recorded information about changes in signals from sensors, accompanied by timestamps that display the time sequence of changes in signals. Figure 3 shows the connections between the blocks of the device shown in figures 1 and 2, as well as the signals transmitted and received from an external device - a receiver of information.

The proposed device, as well as the prototype, includes (Fig. 1) a block for input and coding of signals from sensors, which includes a block of 1 sensors, which according to the number of "n" sensors includes individual nodes 1-1 ... 1-n , first 2, second 3 and third 4 switches, generator 5, a parallel to serial converter, consisting of the first counter 6 and multiplexer 7, in which the address inputs 1A ... mA are connected to the corresponding main outputs of the first counter, and individual information inputs 1I ... nI - with the appropriate individual lnymi outputs 1-1 ... 1-n block nodes 1, wherein the combined second inputs of all the nodes connected to the output of the first and second output of the second switch. The prototype device and the proposed device also includes a serial code comparator 8, the register is RAM 9, in which the main address inputs are connected to the corresponding inputs of the multiplexer, the first 10, second 11 and third 12 triggers, first 13, second 14, third 15, fourth 16, fifth 17, sixth 18, seventh 19 OR elements, as well as the optionally introduced eighth 20 and ninth 21 OR elements, first 22 and second 23 pulse shapers, first 24 and second 25 AND elements, delay element 26, first 27 and (optional included) second 28 distributors carriers, additionally introduced the first 29 and second 30 elements AND-NOT, elements EXCLUSIVE OR 31, OR NOT 32.

The first (direct) output of trigger 10 is the output “data 1” of the device, the output OR 15 is the output “data output” of the device, and the output of the driver 22 is the output of the “clock” of the device.

The composition of the block 1 sensors includes individual sensors D ₁ ... D _n nodes 1-1 ... 1-n. Each node includes the first 33 and second 34 diodes, the threshold element is the first zener diode 35, and the combined anode of the first and the cathode of the second diodes form the first individual outputs of the nodes 1-1 ... 1-n, the cathode of the first diode is connected to one output of the sensor, connected together, the cathodes of the first zener diodes and the second outputs of the sensors of all nodes 1-1 ... 1-n form the second output of block 1, which is connected to the output of the first and second output of the second switches.

The first 2 switch includes the first 36 and second 37 transistors, the second zener diode 38, the cathode of which is connected to the collector 37, and the anode is combined with the collector of the transistor 36. The first 39, second 40, third 41 and fourth 42 resistors set the operating mode and input current of transistors 36 and 37, and the fifth resistor 43 is the level of the working signal at the output of the switch 2. One output of the resistors 39, 41 is connected to the emitters of the transistors 36 and 37 and forms the first input of the switch, which is connected to the non-zero ("U") output of the power source. One output of resistors 40 and 42 is connected, respectively, to the bases of transistors 36 and 37, and the second conclusions 40 and 42 form, respectively, the second and third inputs of the switch and are connected to the outputs of the AND-NOT elements 29 and 30, respectively.

The second 3 switch includes the third 44 and fourth 45 transistors, the third diode 46, sixth 47, seventh 48, eighth 49, ninth 50 resistors that specify the operating mode and input current of transistors 44 and 45 and are connected similarly to the corresponding resistors of the first switch, and the tenth 51 the resistor together with the diode 46 determines the signal level at the first output of the switch 3. The emitter of the transistor 44 forms the first input of the switch and is connected to the output "U" of the power source, the emitter of the transistor 45 forms the second input of the switch and is connected to the output "0" chnika supply and the collector of transistor 45 forms a second output of the second switch, combined with the output of the first switch.

The third 4 switch includes a fifth 52 transistor, a third 53 zener diode, eleventh 54 and twelfth 55 resistors. The resistor 54 sets the operating mode of the transistor 52 and is connected by one output to the base 52, and the second to the zero ("0") output of the power source. One terminal 55 is connected to the collector 52 and forms the output of the third switch, and the second terminal 55 is connected to a non-zero terminal (“U”) of the power source. The zener diode cathode 53 forms the input of the third switch, which is connected to the output of the multiplexer 7 and the first output of the switch 2.

The structure of the device, unlike the prototype, includes the block shown in Fig. 2 for fixing short-term discrete signals and transmitting the time sequence of their changes. The block includes the second 56, third 57, fourth 58, fifth 59 and sixth 60 counters, fourth 61 and fifth 62 switches, parallel code comparator 63, third distributor 64, fourth 65 and fifth 66 triggers, first 67, second 68, third 69, fourth 70, fifth 71 and sixth 72 elements NOT, third 73, fourth 74, fifth 75, sixth 76, seventh 77, eighth 78 and ninth 79 elements And, first 80 and second 81 decoders, tenth 82, eleventh 83, twelfth 84, thirteenth 85, fourteenth 86, fifteenth 87 and sixteenth 88 elements OR, the second register is RAM 89, the register is pre parallel code browser in serial 90.

The outputs "4" and "5" of the distributor 28 are connected, respectively, with the first input And 78 and the third input of the register 90, the outputs 1 ... m of the counter 6 - with the inputs of the register - RAM 89; the outputs 5-P, 6-P, 7-P and 8-P of the distributor 27 are connected, respectively, with the inputs of the element And 74, decoders 80 and 81, the counter 56; the output of the switch 4 - with the information input (i) of the register - RAM 89, the output of the comparator 8 - with the second input of the element And 78; output AND 24 - with the first input OR 88; the output OR 15 - with the first input And 79, and the output of the shaper 23 - with the second input And 79; the output of the shaper 22 with a second input And 73; output OR 88 - with the first input (C) of the distributor 27. The inputs of the element OR 85 are connected to the outputs of the external device "transmission 1" and "transmission 2"; the outputs of the trigger 10 and register 90 - with the inputs of the external device "data 1" and "data 2", respectively; the outputs of the elements And 75, And 76 - with the outputs of the device "request 1" and "request 2", respectively; the driver 22 forms the output signals of the "clock" of the device; output element OR 15 - signals "data output" of the device.

The multiplexer 7 of the parallel code converter (sensor states) to serial can, for example, be implemented on eight-channel 561KP2 series microcircuits. In this case, the number of microcircuits (M) is determined by the total number of sensors “n” according to the formula

where Σ is the sign of rounding to the nearest larger integer. The outputs "B" of all microcircuits are combined. The signals from the counter 6 are fed to the address inputs of the microcircuits, and the number “m” of the main bits of the counter is determined by the formula m = Σlog n. If the number of sensors is more than eight, they are divided into groups of eight sensors in each group. The signals from the three least significant bits of the counter are connected to the corresponding address inputs of the multiplexers, the remaining bits of the counter are converted into positional signals and fed to the input enabling the transition to the operating state of the multiplexer of the corresponding group of sensors. The figure conventionally shows one multiplexer, the input of the enable signal is not shown.

Counters 6, 56, 57, 58, 59, 60 can, for example, be implemented on 561 IE10 chips. Pulse signals are fed to the first clock (C) input of the microcircuit. The counter switches to the adjacent code position when the input signal moves from “0” to “1”, and returns to its initial position (zero code position) when the signal “1” is applied to the third (R) input. The second input of the work enable (P) counter is used to block the sensitivity to the input clock signals. If a zero level signal (“0”) is supplied to the specified input, the counter does not change the state when the next signals arrive at the first input.

Register - RAM 9 implements serial input and serial output of signals and can, for example, be performed on a single chip of RAM 561 RU2, if the number of sensors "n" does not exceed 256. Signals from the main address inputs of RAM 1A ... mA are supplied with the main outputs of counter 6, and to the additional address input (m + 1) A, the signal from the output OR 18. The memory code with numbers from 0 to (2 ^m -1) is used to store the serial code obtained at the first stage of polling and encoding signals from sensors, and in memory cells with numbers from 2 ^m to (2 ^{m + 1} -1) - a serial code obtained in the second stage of the survey and coding of signals from sensors. The code is fed to the information (I) input of the register - RAM, the signal for setting the write-read mode of information - to the control (Y) input from the output OR 17 (the recording mode is implemented when signal “1” is applied to the input Y), and the register transfer signal is RAM in the active state - when a signal is applied to the enable input (P). The W / R input of the 561 RU2 microcircuit is used as the control, and the CE input of the specified microcircuit as the permitting one.

Register - RAM 89 can, for example, be implemented on chips KR 537 RU17, and the number of chips is determined by the required number of address and information inputs. For the proposed device, the number of information inputs of the register - RAM is one more than the sum of the number "m" of the main bits of the counter 6 and the number of "q" bits of the counter 56, i.e. equal to (m + q + 1). The number "s" of RAM address signals is equal to the number of bits of the counter 57. Register - RAM 89 operates in the write and read mode of the parallel code. Data is recorded by the signal “1” at the input “W” when a working signal is applied to the synchronizing (C) input.

Distributors 27, 28 and 64 can be implemented, for example, on chip 561 IE9, combining a binary counter with eight code positions and a decoder. When a signal “0” is applied to the second enable input (P), the distributor loses sensitivity to clock signals.

Triggers 10, 11, 12, 65, 66 can be implemented, for example, on 561 TM2 microcircuits. Triggers can be controlled asynchronously - by the signals supplied to the first input of the state setting “1” (S) or the fourth input of the state setting “0” (R), and also synchronously - by applying an information signal (D) to the second input, and the trigger goes into the state corresponding to the signal at input D, according to the positive difference of the signal at the third clock input (C).

The pulse shapers 22, 23 can be implemented, for example, on the basis of a trigger, the direct output of which is connected to the R input through an integrating RC circuit. The shaper is put into operation by the difference in signal level at the C input of the trigger, if at the given moment the signal “1” is applied to the D input. The duration of the generated pulse is determined by the time constant of the integrating RC chain.

The serial code comparator 8 can be implemented, for example, on an EXCLUSIVE OR element, to the inputs of which the compared signals of the serial codes are supplied. At the output of the comparator, a signal "1" is formed when the input signals do not match.

The delay element 24 may be implemented, for example, on an integrating RC circuit.

The switches 61, 62 can be implemented, for example, on 561 LC2 chips. When a signal “1” is applied to the control input “X” or “Y”, the signals pass from the information inputs “X” (1 for switch 62) or “U” (2 for switch 62), respectively. The number of chips for the implementation of the switch 61 is determined by the larger of the two numbers - (m + q + 1) and "s".

The parallel code comparator 63 can be implemented, for example, on 561 LP2 microcircuits. The number of microcircuits is determined by the number of compared digits from the counters 57 and 59. When the codes are equal and the signal “1” is applied to the control input (Y), the signal “1” is generated at the output of the comparator.

Decoders 81 and 82 can, for example, be implemented on a combination of AND, NOT logic circuits. When a certain combination of direct and inverse (generated by the elements NOT) signals from the counter 60 is fed to the inputs of the And element, the signals “1” turn out to be fed to all the inputs of the And element, which leads to the appearance of the “1” signal at its output. To synchronize the operation of the decoder, the signal applied to its second input is used, while the output signal “1” is formed synchronously with the signal supplied to the specified input of the decoder. The specified structure of the decoders allows you to select the time when the required number of clock pulses is applied to the input of the counter 60.

The remaining elements of the device are implemented, for example, on standard logic circuits of the 561 series, the operation of which does not require explanation.

Figure 1 and 2 shows an example implementation of the proposed device on separate integrated circuits. The functions of the elements shown in the figure can be partially performed programmatically with the help of elements included in a single-chip microcomputer, for example, type AT89C52.

Consider the operation of the proposed device.

The procedures for inputting, encoding, processing and transmitting information reflecting the current values of the signals from the sensors (Fig. 1) are divided into several stages. Each stage is assigned a signal “1” at one of the outputs 1-P ... 8-P of the distributor 27. The distributor 27 is transferred to the next position (and the device to the next stage of operation) by a signal supplied to its first (C) input . The stages are divided into clock cycles, which are set by the generator 5 and the counter 6. The counter 6 switches from one code position to the edge adjacent to the signal at the first (C) input - when signal “1” appears at the output “6” of the second distributor 28. Signal “1 "Appears at the output" 6 "of the second distributor when six clock signals arrive at the first (C) input 28 from the generator 5. At the same time as the signal arrives at the first input of the counter 6, the signal at its first output changes. With each change of the signal at the first output 6, an output of a pulse signal is generated at the output of the first driver 22, which is fed through OR 20 to the R input 28 and transfers the second distributor to its initial state. Thus, using the distributor 28, one code position of the counter 6 - one clock cycle, is converted into six microtacts divided in time. The number of clock cycles that make up one stage of the operation of the device during the input and coding of signals from sensors is determined by the number of sensors "n". After completing a survey or other type of processing information from all sensors, signal “1” is generated at the additional (m + 1) output of the counter 6. The second pulse shaper 23 detects the appearance of signal “1” at the output (m + 1) of the counter and generates a pulse the signal that is supplied to the R input of counter 6. The counter 6 is transferred to the initial state by the indicated pulse signal, and the distributor 27 at the steps 1-P ... 4-P of the input and coding of signals from the sensors switches to an adjacent position. The switching signal 27 is generated by OR 21, AND 24, OR 88. The described operation of the generator 5, the first 27 and the second 28 distributors and counter 6 is carried out cyclically.

When setting the signal "1" at the output 1-P, i.e. at each first stage of operation of the device, the change in state of any sensor is monitored. Since at the indicated time the signal “1” is fed to the input of OR NOT 32, a signal “0” is generated at its output. The result is a circuit: output “U” of the power source — parallel branch from the emitter-base junction of transistor 44 and resistor 47 — resistor 48 — output 32 — output “0” of the power source. The resistor 47 fixes the operating point of the transistor 44 (prevents the transistor from spontaneously transitioning to operating state when the ambient temperature changes over a wide range), and the resistor 48 determines the value of the operating current in the input circuit 44. The current in the input circuit 44 causes a current to appear in the output circuit 44, which runs along two parallel branches. One of the branches includes a resistor 51 and an isolation diode 46, and the second one contains a series circuit of a resistor 49, a base-emitter junction of the transistor 45, and closes to terminal “0” of the power source. Resistor 50, similar to resistor 47, fixes the operating point 45. As a result, a signal with level “0” is supplied to the second output of switch 3 and the second (common) output of block 1. The current flow circuit of the first branch of the transistor 44 is determined by the state of the sensor interrogated during the considered time interval. The number of the interrogated sensor is determined by a combination of code signals at the address inputs 1A ... mA of multiplexer 7, i.e. the current code position of counter 6. So, for example, when m = log n and when setting counter 6 to the initial state, output “B” of multiplexer 7 is connected to the first (1I) information input, and when setting signals “1” on all address inputs of the multiplexer 7, the output "B" is connected to the input nI, i.e. to the first output of the node 1-n of the sensor block 1.

Suppose that the contact (output element) of the interrogated at the considered time point of the sensor D ₁ is closed. Then a circuit is created: output 44-51 - 46 - output "B" 7 - input 1I of the multiplexer 7 - first output of the unit 1-1 - 33 - D ₁ - second output of the unit 1 - collector-emitter junction 45 - output “0” of the source nutrition. Since the sum of the voltage drops on the multiplexer 7, the diode 33 and the closed contact of the sensor D _{1 is} lower than the threshold voltage of the zener diode 53 of the switch 4, no current passes through the input circuit of the third switch 4. As a result, the transistor 52 remains inoperative, and the signal level on its collector is equal to "U", i.e. logical signal "1". Thus, in the considered mode of operation of the device with a closed contact of the sensor, the signal at the output of the switch 4 is equal to "1". If the sensor contact is open, the current circuit described above is not created. The current of the transistor 44 is closed through a resistor 51, a diode 46, a zener diode 53, the base-emitter transition of the transistor 52 to the output "0" of the power source (note that the operating point of the transistor 52 is fixed by the resistor 54). As a result, the transistor 52 is put into operation, current flows through its output circuit, and the output signal level of the switch 4 becomes “0” (we neglect the voltage drop across the transistor 52). Similarly to the described signals are determined from all sensors. The output signal of the switch 4 is fed to the first input of the EXCLUSIVE OR element 31, the second input of which in the case under consideration is the signal "0" from the output 4-P of the distributor 27. Element 31 in step 1-P performs the function of a repeater of the signal received at its first input . The output signal 31 is supplied to the information (I) input of the register - RAM 9. At step 1-P, the signal "1" is not applied to the control input (U) 9, so the register - RAM is switched to the read mode of previously recorded information. Since the signals supplied to the address inputs of the multiplexer 7 and the register - RAM 9 are identical, the outputs of the switch 4 and the register - RAM 9 receive signals corresponding to the same sensor. The signal at output 4 reflects the current value of the signal from the sensor, and at output 9, the value of the signal recorded in it earlier. The output signal of the register - RAM 9 is fixed by trigger 10, and to trigger 10, the signal from the register - RAM 9 is overwritten in the third microtact (when signal “1” is generated at the third output of distributor 28), i.e. with a shift of one microtact relative to the moment the register - RAM 9 was put into operation by a signal at the output of OR 13. It is important that the moment the register - RAM 9 was put into operation was also shifted by one microtact relative to the change in the code position of counter 6, i.e. regarding the moment of connection of the signal from the newly selected (interrogated) sensor to the input of the multiplexer. It is seen that the use of time-divided microtacts eliminates the influence of transients on the operation of the device.

If the current state of the polled sensor has changed relative to the previously recorded and entered in the register - RAM 9, the inputs of the comparator 8 receive signals of different levels, and the signal at the output 8 becomes equal to "1", otherwise the output signal of the comparator is equal to "0". The fact of a change in the signal from the sensor is conventionally called an “event” - the basis for subsequent transmission of information. The comparator signal, showing the result of comparing the “old” and “new” signal values from the sensor, is detected by trigger 11 by signal “1” at its third (C) input when signal “1” appears on the fourth output of distributor 28, i.e. with a shift in one microtact relative to the moment of fixing the signal from register 9 by trigger 10 and applying the signal to the second (D) input of trigger 11. After switching trigger 11 to state “1”, the signal from its first (direct) output is transmitted through OR 16 to the second ( D) an input, blocking the return of trigger 11 to the state “0” regardless of the ratio of current and previously recorded signals registering the status of other sensors. Thus, trigger 11 after a single transfer to state “1”, i.e. after fixing at least one “event”, it saves the set state until the end of the stage of comparing signals from all sensors. The stage is completed when a pulse signal is generated by the shaper 23, which through AND 24, OR 88 is supplied to the first (C) input of the distributor 27 and to the R input of the counter 6. The distributor 27 goes into the next state - signal “1” is generated at its output 2-P . If at this moment no "event" is detected, trigger 11 remains in the state "0", and the signal "1" is generated at its second (inverse) output. The signal from 11 is fed to the second (D) input of the trigger 12. On the edge of the signal 2-P, which is fed to the third (C) input, the trigger 12 is transferred to the state “1”, as a result of which the distributor 27 is a signal at the third (R) input returns to its original state. The device returns to the stage of comparing the current and previously entered in the register - RAM 9 signals from the sensors. Upon transition to each new stage of operation by a signal from the former 23, which is received at the fourth (R) input, trigger 11 returns to its initial state. After the return of the distributor 27 to the initial state by the signal “1” from the output 1-P, the trigger 12 returns (at the input R) to the initial state.

If at the moment of signal formation “1” at trigger 2-P, trigger 11 is set to state “1”, signal “0” is generated at its second output, trigger 12 is not set to state “1”, and dispenser 27 does not return to its initial state , the device proceeds to step 2-P.

At stage 2-P, the current signals from the sensors are recorded in the register - RAM 9. The signal “1” is applied to the input OR-NOT 32, so the signals generated at the outputs of the switch 3 are identical to those generated at stage 1-P. The signal "1" is fed to the input of OR 17, so the signal "1" from the output of OR 17 is sent to the control input (U) of the register - RAM 9. With this signal, the register - RAM 9 is transferred to the recording mode of information from all sensors, starting from the first, since the counter 6 to the beginning of stage 2-P is set to the initial state. On the second microtact of each clock cycle, according to the signal “1” from the OR 13 output, applied to the register enable (R) input - RAM 9, the signal from the switch 4 repeated at the EXCLUSIVE OR 31 output and fed to the information (I) input 9 is recorded in the selected register cell is RAM 9. The cell number is determined by the address signals at inputs 1A ... mA of multiplexer 7 and the register is RAM 9. By the end of stage 2-P, the signals corresponding to the current states of all “n” appear in the register - RAM 9. sensors.

At the next stage 3-P, a timeout is set, which separates the moments of the initial and repeated data recording in the register - RAM 9 and reduces the likelihood of information distortion by noise in the communication circuits of the sensors with the encoder implemented on the counter 6, multiplexer 7, switches 2, 3 and 4, EXCLUSIVE OR 31.

Stage 4-P is allocated for diagnosing the operability of the general and individual nodes of the device and the absence of damage to the communication circuits of the sensors of unit 1 with the encoder. At step 4-P, signal “1” is not supplied to the inputs of OR-NOT 32, so the signal at its output is “1”, and switch 3 remains inoperative. Switch 2 is put into operation. The signal that is generated by switch 2 is determined for each sensor individually, depending on the signal previously recorded in the register - RAM 9. On the second microtact to the register enable (P) input - RAM 9 from OR 13 output a working signal is supplied, and on the indicated microtact, a “0” signal is supplied from the OR output 17 to the control input (U), and a “0” signal from the OR output 18 is sent to the address input (m + 1) A. As a result, the register is RAM 9 It appears in the mode of reading information from cells into which earlier, at the stage 2-P, information was entered. The signals read from 9 are fed to the second (D) trigger input, and on the third microtacts, they are transferred to trigger 10 by the signal “1” at the third input. As shown earlier, at stage 2-P, the signal “1” is written to the register - RAM 9, if the contact of the interrogated sensor is closed. In order to diagnose the operability of circuit elements and communication circuits of the sensor with the encoder, in step 4-P, for such sensors, the absence of a short circuit in the communication circuit of the sensor with the encoder is checked. In this case, the signal "1" from the first output of the trigger 10 is fed to the first input of the NAND 30. Since the signal "1" is sent to the second input of the NAND 30, the signal "0" is generated at the output of the element. The circuit closes: the output "U" of the power source - parallel branches from the resistor 41 and the emitter-base transition of the transistor 37 - resistor 42 - input 3 of the switch 2 - output NAND 30 - output "0" of the power source. As mentioned earlier, the resistor 41 fixes the operating point of the transistor 37, and the resistor 42 determines the operating current of the transistor 37. The current in the input circuit 37 leads to the appearance of current in the output circuit: the output "U" of the power source - the emitter-collector junction 37 - the zener diode 38 - resistor 43 - second (common) output of block 1 - node 1-1 ... 1-n, corresponding to the number of the interrogated sensor, - zener diode 35 - diode 34 - information input of the multiplexer 7, corresponding to the number of the interrogated sensor, - output "B" multiplexer 7 - zener diode 53 switch 4 - parallel ve and a resistor 54 and the base-emitter voltage of transistor 52 - the output "0" power source. If the zener diode 35 is not excluded from the considered circuit (the sensor – encoder communication circuit is not closed), the level of the output working signal of the switch 2 is lower than the threshold level for the considered circuit. As a result, the transistor 52 of the switch 4 remains inoperative, there is no current in the output circuit 52, the signal level at the output of the switch 4 is “1”. Since the signal “1” is applied to the second input of the EXCLUSIVE OR 31 in the considered operation mode, the element 31 performs the function of an inverter. As a result, for the case under consideration, the signal at the output 31 and the information input of the register - RAM 9 is equal to "0". On the fourth microtact, a working signal is supplied to the enable (R) input of the register - RAM 9, the signal “1” from the OR output 17 is supplied to the control input (Y), since the signal “1” from the output And 25, the signal “ 1 ”is also sent to the address input (m + 1) A of the register - RAM 9 from the output OR 18. As a result, in the considered operating mode, the signal“ 0 ”is entered into the cell 9 corresponding to the polled sensor. It should be emphasized that the number of the cell into which information from the sensor is re-entered is shifted by "n" relative to the number of the cell into which information from this sensor was originally entered. As a result, in the case under consideration, a combination of signals “10” is recorded in the indicated pair of register cells - RAM 9.

If for the case under consideration (the initial recording in the register - RAM “1” signal) the communication circuit of the interrogated sensor with the encoder turns out to be closed, the zener diode 35 is excluded from the considered output current flow circuit of switch 2. As a result, the working signal of switch 2 will exceed the threshold level for switch 4; the transistor 52 of the switch 4 will be put into operation. At the output of the switch 4, a signal “0” is generated, which is converted into a signal “1” at output 31. As a result, a combination of signals “11”, which is interpreted as malfunction (short) of the communication circuit with the sensor or any other equivalent malfunction of the device elements. It is important to emphasize that during the diagnostics of the operability of the device elements and the sensor’s communication links with the encoder, the circuits that were used for the initial recording in the register - RAM 9 of the signal reflecting the current state of the sensor in the 2-P stage are used, which maximizes the degree of control. So, if the closed state of a sensor is initially recorded, a pair of signals “10” if a malfunction is not detected, and “11” when a malfunction is detected, will be recorded in two cells of the register - RAM 9 (allocated for one sensor).

Consider the operation of the device in step 4-P for the case when the open state of the sensor is initially recorded, i.e. The signal “0” was recorded in the register cell corresponding to the interrogated sensor - RAM 9. In this case, at step 4-P, trigger 10 (when reading the signal from the corresponding register cell - RAM) is in the “0” state, I-NOT 30 is inoperative, and “1” signals are sent to two I-NOT 29 inputs , the signal "0" is generated at the output of the element. In this case, in the same way as it was described when the I-NOT 30 was put into operation, the transistor 36 is brought into operation by the signal “0” at the second input of the switch 2. The output signal of the transistor 36 is not attenuated by introducing a zener diode 38. As a result, conditions are created for diagnosing the absence of a break in the communication circuit of the sensor with the encoder. The working signal generated at the output of switch 2 is sufficient to put the transistor 52 of switch 4 into working condition, therefore, with healthy circuit elements and the communication circuit with the interrogated sensor, the signal at the output of switch 4 should be equal to "0", and at the output of EXCLUSIVE OR 31 - equal to " one". As described above, this signal is entered in the register cell allocated to the interrogated sensor - RAM 9, and the cell number is shifted by "n" relative to the cell in which the signal representing the current state of the sensor was previously recorded. Thus, when the open state of the sensor is fixed and there is no break in the communication circuit between the sensor and the encoder, the two cells of register 9 allocated to the interrogated sensor are recorded “01” signals. If the communication circuit of the sensor with the encoder is broken (or an equivalent malfunction of circuit elements is detected), the transistor 52 of the switch 4 is not put into operation, the signal “1” is generated at its output, and the signal “0” is written at the output of the EXCLUSIVE OR 31, which is recorded in the corresponding register cell is RAM 9. Thus, when an open state of the sensor is detected and a malfunction (rupture) of the sensor and encoder communication circuit is detected, two register cells - RAM 9, which are recorded as 00 signals, are allocated to the two register cells - RAM 9. This situation is identified by the receiver as a malfunction, and the sensor number and type of malfunction are determined from the received data.

Similarly to the described diagnostics and repeated recording in the register - RAM 9 of information received for all sensors is carried out, after which the operation of the device at step 4-P is completed, the device goes to step 5-P.

Stage 5-P is designed to generate and transmit to the external control device the signal “request 1” or “request 2”, which identifies the entry in the register - RAM information that must be transmitted to the receiver. The signal "request" is received at the output of the device from the output of the And 75 or And 76 element. In response to the signal "request 1" or "request 2" from the external device, the signal "transmission 1" or "transmission 2" should be received, respectively. The delay element 26 records that the device is held in step 5-P for more than a predetermined time, i.e. its inputs do not receive the signal "transmission 1" or "transmission 2". In this case, the device does not transmit the latched data, since the signal “1” is generated at the output 26, which, through OR 19, is supplied to the first (S) input of the trigger 12. As noted above, the signal “1” from the trigger 12 distributor 27 returns to the initial state. For the time from the device issuing the “request” signal and until the response signal “transmission” is received by the “1” signal from the output 5-P of the distributor 27, the operation of the distributor 28, and therefore the counter 6, is blocked through OR 20. If, in response to the “request” signal "From the external device receives the signal" transmission 1 "or" transmission 2 ", the signal" 1 "is generated at the output of OR 85, which through AND 77, OR 88 is fed to the first (C) input of the distributor 27. The device proceeds to step 6-P .

Consider the data transmission mode for the case when at stage 4-P only one “event” is recorded, i.e. there is no need to transmit data on the time sequence of several changes in the signals from the sensors. In the considered operating mode, the device (as discussed below) generates a “request 1” signal, in response to which an “transmission 1” signal should be received from an external device. In this case, the signal “1” at the input “transmission 2” is absent, the signal “1” is formed at the output of NOT 72 and at the input “X” of the switch 62, through which the signal transmitted to the first input 62 from the output And 79. The signal “1 "At the output And 79 is formed at stages 6-P and 7-P (when the signal" 1 "is supplied to the first input from the output OR 15) synchronously with the signal from the driver 23 supplied to the second input And 79. In the specified operating mode, the signal from And 79 controls the operation of the dispenser 27. Steps 6-P and 7-P in the considered operation mode are allocated for data transmission read from the register - RAM 9. The data is accompanied by a control signal “data output”, which is formed OR 15. At stages 6-P and 7-P, a “0” signal is sent to the control (Y) input of the register - RAM 9, so it is switched to data reading mode. The signal “0” was sent to the address input (m + 1) A of the register - RAM 9 at step 6-P, so the information is read from the cells in which the current values of the signals from the sensors of block 1 were entered. Data read from the register - RAM 9 the second microtact is transferred to trigger 10, from the first (direct) output of which information is fed to the output “data 1” of the device. The data is accompanied by signals "clock" from the output of the pulse shaper 22.

After reading the status signals of all sensors, another signal is generated at the output of the former 23, by which the counter 6 returns to its initial state, and the distributor 27 is transferred to the next position - 7-P. Step 7-P is allocated for outputting information from register cells - RAM 9, the numbers of which are shifted by "n" relative to the numbers from which the information was read in step 6-P. As indicated above, diagnostic information is stored in the specified address area. The second input OR 18 receives a signal "1", which is relayed to the address input (m + 1) A of the register - RAM 9, determining the read zone. Otherwise, the data reading procedures in steps 6-P and 7-P are the same. After transmitting all the diagnostic signals, the next signal is generated at the output of the former 23, which distributor 27 (through And 79, switch 62, OR 88) is transferred to position 8-P.

The signal "1" from the output 8-P of the distributor 27 through OR 19 is fed to the first (S) input of the trigger 12. The signal "1" from the trigger is fed to the R input of the distributor 27, bringing the device to its initial state. The signal “data output” is removed, the cycle of input, coding, diagnostics and data transmission is completed, the device is prepared to perform the procedures of the next cycle of work.

As you can see, the encoding and data transfer procedures provide dynamic diagnostics of common sensors and individual nodes, and the received diagnostic data is entered into the device information message, which allows identifying not only the location, but also the type of malfunction. When conducting diagnostic procedures and working procedures for entering and encoding information from sensors, the same nodes and elements are used, which increases the depth of diagnosis.

Consider the operation of the device when generating data that displays both signals from sensors and the time sequence of their changes.

When the state of any sensor changes, signal “1” is generated at the output of comparator 8, which is fed to the clock (C) input of counter 57 through the AND 78, OR 86 on the fourth microtact “4” of the distributor 28. Counter 57 counts the number of “events”. At the same time, signal “1” is also supplied to the clock input (C) of the distributor 64, which records: the absence of at least one “event” (the signal “1” is generated at the output 1 of the distributor 64), only one event (the signal is “1 "Is formed at the output 2 of the distributor 64), several" events "(the signal" 1 "is formed at the output 3 of the distributor 64). After fixing two "events" to the enable (P) 64 input, the signal "0" from NOT 71 is supplied, the distributor 64 loses sensitivity to clock signals and remains in the received state until the signal "1" arrives at its R input. In the mode of transmitting data on the time sequence of "events", the transition of the distributor 27 to the 6-P position is delayed by the set monitoring time.

The maximum monitoring time depends on the number of bits (q) of the counter 56, and the countdown starts from the moment the first "event" is fixed, when the signal "0" appears on the output 1 of the distributor 64, the signal "1" appears on the output NOT 67 and the operation AND is released 73. The output signals And 73 are fed to the first (C) input of the counter 56 synchronously with the signals of the "clock".

Consider the dynamic parameters of the device. The frequency of the pulses arriving at the clock (C) input of the counter 6 is equal to f _g / 6 (f _g is the frequency of the signals of the generator 5), corresponds to the rate of interrogation of the sensors. With a sequential interrogation of "n" sensors, the frequency of the signals at the input of the counter 56 is f _g / 6n, and the maximum time for monitoring the time sequence of changes in signals from the sensors (T _K ) is:

The frequency f _g / 6n determines the minimum time shift between two adjacent "events" at which different time changes of the signals from the sensors are recorded. It is important to emphasize that related “events” refer to changes in different or of the same sensor. Therefore, the set minimum time - discreteness of fixation of "events" determines the minimum duration of the signal from the sensor, which is recorded by the device. For example, to obtain the discreteness of fixation of “events” no more than 1 ms at n = 32, the frequency of the signals of the generator 5 should be no less than 10 ³ · 6 · 32 Hz (200 kHz). The number of bits "q" of the counter 56, the time resolution T _D and the monitoring time T _{To are} connected by the equation:

To ensure T _K = 10000 ms at T _D = 1 ms, it is necessary that q = 13. In addition to fixing the completion of the set monitoring time of the “events”, the counter 56 is used to determine the time shifts between the “events”, i.e. to form the first timestamp. Since the counter 56 is held in the initial state until the first “event” is fixed, the time stamp of the first “event” is conventionally set to zero.

The data of each "event" is entered into the register - RAM 89 by a signal from OR 86 (via AND 78), which is received at the synchronizing (C) input when any "event" is fixed by comparator 8. The time shift of the "event" relative to the first (first time stamp) is determined by the number of pulses received at the input of the counter 56 at the time of fixing this "event", and the established T _D. Code - the status of the counter 56, is fed to the information inputs (1 ... q) of the register - RAM 89. Simultaneously with entering into the register - RAM 89 the code of the counter 56, the code from the main digits is also entered in it (at inputs 1 ... m) counter 6, which determines the sensor number. The signal received on the register “i” bus - RAM 89 from the output of the switch 4, determines the state of the sensor at the moment of recording the “event”. Thus, the total number of information bits characterizing one “event” is (m + q + 1). The bit depth of the register memory cells — RAM 89 — is determined from this number. The number of register memory cells — RAM 89 is selected taking into account the established maximum number of “events”, which is determined by the number of bits of the counter 57. For the example shown in FIG. 2, the number of bits of the counter 57 is “S,” and the maximum possible number of events is 2 ^S-1 . Upon reaching the specified number of "events", the sensitivity of the counter 57 to clock signals arriving at its first (C) input from the output OR 86 (via AND 78) is blocked by the signal "0" from NOT 69, applied to the second (P) input. The signals from the counter 57 are fed to the address bus register - RAM 89.

As indicated, counter code 56 is used as the first time stamp by which the time sequence of “events” can be restored in the external device. The second time stamp used to restore real-time “events” is generated by counter 58 and corresponds to a time shift between the last of the recorded events and the beginning of the transmission of information to the receiver. To do this, pulses are fed to the clock (C) input of the counter 58 synchronously with their arrival at the input of the counter 56. When any "event" is fixed by the signal from And 78, applied to the R input, the counter 58 is set to the initial state. Thus, after the end of the monitoring time, the counter code 58 corresponds to the time elapsed from the moment the last “event” was recorded. If the data transfer does not start before the maximum permissible code is set in counter 58, the sensitivity of the counter to clock pulses is blocked by the signal “0”, which arrives at its second (P) input from NOT 70. The combination of two time stamps determines the time shift of the “event” relative to the start time transmitting information to the receiver. By the time of data transmission (T _P ), as well as the time determined by the first and second time stamps (T _1M / T _2M ), and the absolute (astronomical) time of recording information in an external device (T _A ), you can determine the real time of the "event" x "(T _PX ):

where T _1MX is the time according to the first relative time stamp for the "event" X.

Here is an example of calculating T _P7 (“events” 7) for the following initial data:

- T _A = 12 hours 34 minutes 23 s 460 ms,

- the fixed number of "events" is 8,

- the code of the first time stamp recorded by the counter 56 for the seventh "event" - 487 ₁₀ (in decimal system), the number of bits of the code of the first time stamp (counter 56) - 16,

- code of the second time stamp - 228 ₁₀ with the number of bits of the code of the second time stamp (counter 58) - 16,

- the number of sensors is 32, i.e. m = 5,

- frequency of the generator signals 5-200 kHz, discreteness of fixation of "events" T _D = 1 ms.

The transmission time T _{P to the} data receiver according to the second time stamp and information from the register 89 is determined by the total number of transmission clocks, which is [16 + 8 (16 + 5 + 1)]. Then T _P = 6 [16 + 8 (16 + 5 + 1)] / 200 ms = 6 ms.

The time shift T _1M7 = 487 · 1 ms, T _2M = 228 · 1 ms. Then Т _Р7 = 12 hours 34 minutes 23 s 460 ms - (6 + 487 + 228) ms = 12 hours 34 minutes 22 s 739 ms.

It should be noted that the above calculations are valid when transmitting data to the receiver in a mode close to real time. When relaying data at a speed equal to, for example, 200 bit / s, to determine the real time of the “event”, it is necessary to take into account T _P = [16 + 8 (16 + 5 + 1)] / 0.2 ms = 960 ms (given in In the examples, the calculations do not take into account the transmission time, except for the data on the “event”, other components of the information message, for example, the start combination, address field, protection field).

Consider the operation of the device when transmitting "data 2". The time of fixing “events” is limited by the installed (maximum) capacity of the counter 56 or by the established (maximum) number of “events”, i.e. the maximum capacity of the counter 57. Using OR 83, the maximum number of pulses is entered into the counter 56 or 57. The signal "1" from OR 83 through AND 74 (to the second input of which a signal "1" is supplied from the output of the 5-P distributor 27) is fed to one input of the And 75, And 76 elements. If at this moment one "event" is fixed, the signal "1" and the output signal of the device "request 1" are formed at the output AND 75. In this case, the device implements, as described above, the procedure for transmitting "data 1". If the register 64 recorded at least two “events”, the signal “1” and the output signal “request 2” are generated at the output And 76.

In response to the “request 2” signal, the external device supplies the “transmission 2” signal to the input of the device. Since there is no “transfer 1” signal in the considered operating mode, the signal “0” from the output of NOT 72 is supplied to the input “X” of the switch 62, and the signal “1” from the input of NOT 72 is sent to the input “U”. The transmission of signals from AND 79 to the output of the switch 62 is blocked, and the distributor 27 is not transferred from the position 6-Р to the positions 7-Р and 8-Р according to the signals from the driver 23. Position 6-Р is used to transmit to the external device the code of the second time stamp fixed by the counter 58 . According to the signal "1" at the output 6-P of the distributor 27, applied to the control input "X" of the switch 61, at the exit At the switch, signals are sent from the DX input group, i.e. from the outputs of the counter 58. The output signals of the switch 61 by the signal "1" applied to the control (Y) input of the register 90 from the output OR 84, are recorded in the register. The parallel code recorded in the register 90 is converted into a serial one using the clock signals supplied to the synchronizing (C) input 90 from the output 5 of the distributor 28. The serial output code of the register 90 is fed to the output “data 2” of the device. The number of clock ticks of the code of the second time stamp must correspond to the set number of bits (q) of the counter 58. The number of clock ticks is equivalent to the code at the outputs 1 ... t of the counter 60, which is put into operation by the signal “1” at the second (P) input upon receipt to the input of the signal device "transfer 2" and counts the clock signals from the output 5 of the distributor 28. The completion of the transmission of the code of the second time stamp is determined by the code state of the counter 60. The required code state of the counter is fixed by the decoder 80. Signal "1" with the output of the decoder 80 through OR 82, the switch 62, OR 88 is fed to the first (C) input of the distributor 27, translating it into position 7-P. At the same time, the signal "1" at the input of R counter 60 returns to its initial state. Position 7-P of the distributor 27 is used to transmit to the output “data 2” information previously recorded in the register - RAM 89. By the signal “1” applied to the control input “U” of the switch 61, signals from the information outputs 1 are sent to the outputs of the switch ... (m + q + 1) of the register - RAM 89. To read and transfer to the external device all the recorded data from the register - RAM 89, data must be read from the cells, the number of which is equal to the number of recorded "events". The number of previously recorded events is stored in counter 59. The code read from the register - RAM 89 includes data characterizing one event. The specified parallel code is entered in the register 90, which converts it into a serial, received on the output "data 2" of the device. The number of data transfer cycles characterizing a single event is equal to the number of bits of the register output code - RAM 89 - (m + g + 1) = t, therefore, the number of bits of the counter 60 must be at least “t”. The number of transmission clocks is fixed by the decoder 81, which generates a signal “1” at the output when the required code is installed at the output of the counter 60. The signal from 81 through OR 86 is fed to the first (C) input of the counter 57, which at the beginning of stage 7-P, the signal "1" at the input R (from the output of OR 87) was transferred to the initial state. Thus, the output code of the counter 57 at step 7-P corresponds to the number of data transmission cycles read from the register - RAM 89.

The signal from OR 86 is also fed to the synchronizing (C) input of the register - RAM 89, so that a code characterizing the next "event" is received at the output of the register, and the number of the "event" corresponds to the output code of the counter 57. As described, the code from the register is RAM 89 through the switch 61 is entered in the register 90 and converted into serial code. To determine the moment of completion of the formation of “data 2”, the counter code 57 is compared by the comparator 63 with the code previously entered into the counter 59 and corresponding to the number of recorded “events”. If the counter codes match, the output signal “1” is generated, which is fed to the second (D) input of the trigger 65. By the signal “1” at the third (C) input, the trigger 65 is transferred to the state “1” in this case. The signal from the trigger 65 through OR 82 and the switch 62 is fed to the first (C) input of the distributor 27. The device is transferred to step 8-P and, as indicated above, the process of transmitting "data 2" is completed.

It is shown that the new elements of the proposed device and the connections between them and the elements introduced into the prototype device allow to obtain new functionalities - in-depth diagnostics of the nodes' health, fixing short-term signals from sensors and the time sequence of "events" - changes in the state of sensors. According to information messages from the proposed device in an external device connected to it via a telemechanical communication channel, the real time of any “event” is restored, which ensures the use of the proposed device as a recorder of emergency (emergency) situations.

Claims (1)

A device for generating and transmitting a sequence of signals that contains a power source, a block of signal sensors, first, second and third switches, a parallel-to-serial converter, consisting of a multiplexer and a first counter, a clock generator, a first pulse distributor, a first register - RAM, a comparator sequential codes, first, second and third triggers, first and second pulse shapers, first, second, third, fourth, fifth, sixth, seventh elements OR, first and second oh elements AND, delay element, first and second elements AND NOT, elements EXCLUSIVE OR, OR NOT, and non-zero ("U") output of the power source is connected to the first inputs of the first and second switch, the second inputs of the first counter, the first distributor, and the zero (“0”) output - to the first and fourth inputs of the first trigger, the first input of the second trigger, to the second input of the second switch, the combined second outputs of the nodes of the signal sensor block are connected to the output of the first and second output of the second switches, and the first ones are individual the e outputs of the nodes of the signal sensor block are connected to the information inputs of the multiplexer, in which the address inputs are connected to the address inputs of the first register - RAM and the corresponding output bits (1 ... m) of the first counter and the output - with the first output of the second switch and the input of the third switch, in which the output is connected to the first input of the serial code comparator, connected by the second input to the first output of the first trigger, which forms the output "data 1" of the device, characterized in that the device includes W A second pulse distributor, the second input of which is connected to a non-zero output of the power source, EXCLUSIVE OR, OR NOT elements, second, third, fourth, fifth and sixth counters, fourth and fifth switches, a parallel code comparator, third pulse distributor, fourth and fifth triggers , the second register is RAM, the register is a parallel-to-serial converter, the first and second decoders, the third, fourth, fifth, sixth, seventh eighth and ninth elements. And, the eighth, ninth tenth, eleventh, twelfth, thirteenth, fourteenth fifteenth and sixteenth elements are OR, the first, second, third, fourth, fifth and sixth elements are NOT, with the first output of the first trigger connected to the first input of the second element AND NOT, the output which is connected to the third input of the second switch, and the second input to the second inputs of the EXCLUSIVE OR element and the first AND-NOT element connected by the output to the second input of the first switch, the second input of the second AND element, and the fourth output of the first about the distributor, which is also connected: the second output with the third (C) input of the third trigger, the second inputs of the fifth OR element and the OR-NOT element connected by the output to the third input of the second switch, the first output - with the first input of the OR-NOT element and the fourth (R) the input of the third trigger, the fifth output - with the second input of the eighth OR element and the input of the delay element connected by the output to the first input of the seventh OR element, the sixth output - connected to the first, and the seventh output - with the second input of the third OR element connected the output to the output is “data output” of the device, and the second input of the sixth OR element connected by the output to the additional address input of the first register is RAM, the eighth output is with the second input of the seventh OR element connected by the output to the first (S) input of the third trigger, which the first (direct) output is connected to the third (R) input of the first distributor, and the second (D) input is connected to the second (inverse) output of the second trigger connected by the first (direct) output to the second (D) input of the second trigger through the first input of the fourth element OR of which the second input is connected to the output of the comparator, at the second trigger the third (C) input is connected to the second inputs of the first and second OR elements, and the fourth (R) input is connected to the third (R) input of the first counter and the output of the second pulse shaper connected to the input with output discharge (m + 1) of the first counter, in which the first (C) input is connected to the sixth output of the second distributor, which also has the following connections: (C) the input - with the output of the clock generator, the third output - with the first input of the second OR element, and the third (C) input of the first t rigger, the third (R) input - with the output of the eighth OR element, connected by the first input to the outputs of the "clock" of the device and the first pulse shaper, connected by the input to the first output of the first counter, and the second output - with the first input of the first OR, which has an output connected to the permission input (P) of the first register - RAM, in which the output is connected to the second (D) input of the first trigger, in which the second (inverse) output is connected to the first input of the first AND-NOT element, the information input of the first register - RAM is connected to output ele EXCLUSIVE OR, connected by the first input to the output of the third switch, and the control (Y) input - with the output of the fifth OR element, connected by the first input with the first input of the sixth OR element and the output of the second AND element, connected by the first input with the output of the second OR element, block sensors contains for each sensor the first and second diodes, the first stabilizer, and the anode of the corresponding first diode and the cathode of the corresponding second diode are combined and are the first outputs of the signal sensor block, the cathode corresponding its first diode is connected to one output of the corresponding signal sensor, the anode of the corresponding first zener diode is connected to the anode of the corresponding second diode, the second outputs of the signal sensors, each connected to the cathode of the corresponding zener diode, are combined and form a second, common output of the signal sensor block, the first switch includes the first and second transistors, the first, second, third, fourth and fifth resistors and a second zener diode, and the cathodes of the first and second transistors and the first conclusions of the first and third the resistors are interconnected, form the first input of the switch and connected to a nonzero (U) output of the power source, the second outputs of the first and third resistors are connected, respectively, with the bases of the first and second transistors and the first outputs of the second and fourth resistors, the second outputs of which form, respectively , the second and third inputs of the first switch, the output of which is connected to the first output of the fifth resistor, the second output of which is connected to the collector of the first transistor and the anode of the second zener diode connected cathode with the collector of the second transistor, the second switch includes the third and fourth transistors, the sixth, seventh eighth, ninth and tenth resistors and the third diode, and the emitter of the third transistor and the first output of the sixth resistor are connected through the first input of the switch to a non-zero (U) output of the power source , the base of the third transistor and the second output of the sixth resistor are combined and connected to the first output of the seventh resistor, the second output of which is the third input of the second switch, the second input of which is connected with a zero output of the power source and the combined emitter of the fourth transistor and the first output of the ninth resistor, the second output of which is connected to the base of the fourth transistor, and through the eighth resistor with the collector of the third transistor and the first output of the tenth resistor, the second output of which is connected to the anode of the third diode connected cathode to the first output of the second switch, in which the second output is connected to the collector of the fourth transistor, the third switch includes a fifth transistor, a third zener diode, about eleventh and twelfth resistors, the first output of the twelfth resistor connected to a non-zero output of the power source, the second output of the twelfth resistor forms the output of the third switch and connected to the collector of the fifth transistor, in which the base is connected to the first output of the eleventh resistor and the anode of the third zener diode, the cathode of which forms the input the third switch, and the emitter of the fifth transistor is connected to the second output of the eleventh resistor and the zero output of the power source, and the ninth element that OR the first, second, third and fourth inputs are connected to the corresponding outputs of the first distributor, and the output is connected to the first input of the first AND element connected to the second input to the output of the second pulse shaper, and the output to the first input of the sixteenth OR element, the output of the third OR element connected to the first, and the output of the second pulse shaper - with the second input of the ninth element And, the outputs (1 ... m) of the main bits of the first counter are connected to the information inputs (1 ... m) of the second register - RAM, information in odes (m + 1 ... m + q) which is connected to the outputs (1 ... q) of the second counter, and the information input (m + q + 1) - to the output of the third switch, at the first distributor are connected: the fifth output - with second inputs of the fourth and seventh elements AND, the sixth output - with the second input of the fifteenth OR element, the first (X) control input of the fourth switch, the first input of the twelfth OR element and the second input of the first decoder, the seventh output - with the second (Y) control input of the fourth switch, the third, the control input of the comparator parallel code c, the second inputs of the twelfth OR element and the second decoder, the eighth output with the fourth (R) inputs of the fourth and fifth triggers, the third (R) inputs of the second and fifth counters, the third distributor and the first input of the fifteenth OR element, the output of the first pulse shaper is connected to the second input of the third element And, the fifth output of the second distributor is connected to the third (C) input of the register - the converter of the parallel code into serial and the first (C) input of the sixth counter, and the fourth output of the second distributor The device is connected to the first input of the eighth AND element, connected by the second input to the output of the serial code comparator, and the first (C) input of the first distributor is connected to the output of the sixteenth OR element and the third (R) input of the sixth counter, the outputs of which are connected to the group of information inputs of the first and the second decoders, and the second (P) input - with the third (C) input of the fifth trigger, the input of the sixth element NOT, the output "transfer 2" of the external device, the second input of the thirteenth OR element connected by the first input to the output " 1 ”transmission of an external device, and the second control input (Y) of the fifth switch connected by the first control input (X) to the output of the sixth element NOT, the first information input to the output of the ninth AND element, the second information input to the output of the tenth OR element, and the output to the second input of the sixteenth OR element, connected by the third input to the output of the seventh AND element, in which the first input is connected to the output of the thirteenth OR element, the zero ("0") output of the power source is connected to the first inputs of the fourth and fifth trigger, and non-zero ("U") output of the power source - with the second (P) input of the fifth counter, in which the first (C) input is connected to the first (C) input of the third distributor, the output of the eighth element And, the third (R) input of the fourth counter and the second input of the fourteenth OR element, and the outputs of the fifth counter are connected to the second group of information inputs of the parallel code comparator, the first group of information inputs of which are connected to the address inputs of the second register - RAM and the outputs of the third counter, and the output - to the second (D) input the fourth trigger, in which the direct output is connected to the second input of the tenth OR element connected by the first input to the output of the first decoder, and the third (C) input of the fourth trigger is connected to the output of the second decoder and the first input of the fourteenth OR element, in which the output is connected to the first ( C) the input of the third counter and the synchronizing (C) input of the second register - RAM, in which the control input (W) is connected to the second (inverse) output of the fifth trigger, and the group of information outputs is connected to the second group (DY) of information of the inputs of the fourth switch connected by the first group of information inputs to the outputs of the fourth counter, and by the group of information outputs - with the group of information (D) inputs of the register - the parallel-to-serial code converter, in which the control input (Y) is connected to the output of the twelfth OR element, and the output is the output “data 2” of the device, and the output “request 1” of the device is connected to the output of the fifth, and the output “request 2” of the device is connected to the output of the sixth element And, the first inputs of the fifth and sixth elements And about are single and connected to the output of the fourth AND element connected by the first input to the output of the eleventh OR element, the second input of the fifth AND element is connected to the second, and the second input of the sixth AND element to the third output of the third distributor, the second (D) input of the fifth trigger and the input of the fifth the element NOT connected by the output to the second (P) input of the third distributor, whose first output is connected to the input of the first element NOT connected by the output to the first input of the third element And connected by the output to the first (C) inputs of the WTO of the second and fourth counters, in which the second (P) inputs are connected, respectively, with the output of the second and fourth elements NOT, the input of the fourth element is NOT connected to the output of the highest bit of the fourth counter, and the input of the second element is NOT connected with the output of the highest bit of the second counter and the first the input of the eleventh OR element connected by the second input to the high-order output of the third counter and the input of the third element NOT connected by the output to the second (P) input of the third counter, in which the third (R) input is connected to the output of the fifth the fourth element OR.

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