SU1182541A1 - Device for checking electronic equipment - Google Patents

Abstract

1. DEVICE FOR THE CONTROL OF RADIO ELECTRONIC EQUIPMENT, containing the first and second elements OR, the first elements of coincidence, which are only due to the fact that, in order to expand the functional capabilities of the device, a clock pulse generator, a reset pulse generator, a shift register, a test driver, signal, test generator, first decoders, memory blocks, valve, counter trigger, second match element, memory block, code converter and indicator, the generator output the documentary pulses coupled to the clock matching between the second element, the control signal shaper, a shift register and a reset pulse generator, the output from the United mounting block inputs random access memory, a shift register with p -Log counting trigger input and a mounting shaper. a control signal connected by an output through a test generator to the device outputs, and directly to the information input of the shift register connected by outputs to the first inputs of the corresponding first coincidence elements connected by second inputs through the corresponding first decoders to the corresponding inputs of the device, and outputs to the inputs of the corresponding blocks memory with the inputs of the first OR element connected to the first input of the valve connected to the second input with the inverse one counting trigger, an output — to the C input of a counting trigger, connected by an inverse output to a second input of the second coincidence element, connected by a third input to the output of a second IL element, connected by inputs to the outputs of the corresponding% of thin blocks of memory, information input IsD of the block RAM is connected to the output of the second element of the coincidence output through the code converter with the input of the indicator. 2. The device according to claim 1, that is, that the pilot of the pilot signal contains a counter connected by a counting input to the synchronous input of the formatter, a setup input to the installation input of the former, outputs to the inputs of the second decoder connected by outputs to the outputs of the former.

Description

The invention relates to automation and computer technology and can be used to control electronic equipment. The purpose of the invention is to expand the functionality of the device. The drawing shows a diagram of the device. The device contains a generator of 1 clock pulses, a generator of 2 reset pulses, a shaper of a control signal, a 4-shift register and a generator of 5 tests, the first decoders are 6.1-fi.f4, where N is the number of devices: gx of the functional parts of the equipment, the first elements are 7.1-7 , N matches, fixed memory blocks 8,1-8 .N, first element 9 OR, in til 10, second element of RSHI 11, counting trigger 12, second element 13 of matching, memory block 14, code converter 15, indicator 16, counter 17 and the second decoder 18., decoders 18, 6.1-6.N executes with inv PTOP PI elements EXACT audio, the particular decoder circuit for each value of decrypted code is different. A clock pulse generator 1 and a reset pulse generator 2 are square pulse generators. The pulse frequency at the output of the generator 2 of the reset pulses is significantly lower than the pulse frequency at the output of the generator 1 of clock pulses. The generator of 5 tests generates a test multi-digit code upon arrival from the generator 3 of the control signal in the form of a pulse. The test signal is set between two clock pulses. The test generator 5 can be executed on two-input coincidence elements, at one input which a logical zero or logical unit is connected, and at the other input - a signal from the output of the driver 3 of the control signal. In blocks 8.1-8.N of constant memory, binary values of the number codes assigned to the functional parts of the con (controllable equipment) are written to the blocks. and to the second input is a polling signal of elements 7.1–7.M coincidence. The code converter 15 converts the binary code into a decimal one and is a decoder. diodes that flash decimal digits. RAM memory unit 14 can be performed on R5 triggers. The device operates as follows. a logical one is generated at the output of the decoder 18. In all other conditions of the counter 17, there is a logical zero at the output of the decoder 18. The control signal, compressed in shaper 3, is fed to the input of the shift register 4 and to the generator input of 5 tests. When a logical unit appears at the generator input 5 tents, it generates a multi-unit test code at the output, which is fed to the input of the monitored equipment. Clock pulses from the output of the generator 1 are also fed to the synchronization input of the shift register 4, to the generator input 2 of the reset pulses, and to the input of the matching element 13. The logical unit of the generated pilot signal from the output of the decoder 18 is recorded in the first register bit 4 shift. The subsequent clock pulses the logical unit shifts from one bit of register 4 to the other. The signals from the outputs of each bit of shift register 4 are fed to the inputs of matches 7.1-7.N. From the output of the generator 1 clock pulses, the clock pulses are fed to the input of the generator 2 reset pulses. The generator 2. Reset pulses form square-clock pulses from the clock pulses, which have a lower frequency. The reset pulses arrive at the input to the zero setting of the counter 17, register 4, trigger 12, memory block 14. The reset pulses used to reset counter 17 and register 4 set

cycle control. Pulses reset trigger 12 and block 13 matches may be more rare. They are used to zero the circuits that generate and indicate a fault signal.

Each i- functional part of the controlled equipment is connected

to the appropriate decoder 6.1, which is tuned to the code corresponding to this part, due to its good health.

From the outputs of the functional parts of the monitored equipment, the signals through the 6.1-6.N decoders, to which the decoded control code is converted into a logical unit, arrive at the inputs of the elements 7.1-7.N matches, sequentially polled by signals from the codes of the 4 shift register.

Time ticks, in which the inputs of the elements 7.1-7. N matches, the control test signals from the decoder outputs 6.1–6, N, and the interrogation signals from the outputs of the shift register 4, coincide. The polling signal from the shift register 4 arrives in the form of a logical unit. From the output of the decoder 6.1 in the case of proper operation of the monitored equipment, the corresponding logical element 7.i arrives at the corresponding element 7.i coincidence signal. At the output of the element 7.g in this case, a logical zero is formed. In case of malfunctioning of the equipment from the output ,, decoder 6.i, the logical unit enters the input of the element 7.i coincidence, which in the presence of a logical unit from the shift register 4 passes to output of element 7, v coincidence.

If at the output of one of elements 7.1-7. M matches, for example, element 7. a logical unit appeared, it arrives at the input of the corresponding memory block 8. and polls it. When polling block 8, a code corresponding to the number of the failed node appears in the memory of the logical unit on its output. This code is fed to the input of the element OR 1 and through it to the input of the element 13 of coincidence.

The signals from the outputs of elements 7.1–7 coincidence also go to the inputs of element 9 OR and through it to the open valve 10 to the synchronization input of the counting trigger 12. To the other input of the valve 10, the logical unit from the inverse output of the trigger 12 arrives, Since the trigger 12 is at zero after the arrival of the reset pulse to the input P from generator 2, the logical unit from the inverse output of the trigger 12 enters the input of the matching element 13 and allows the codes from the output of block 8, i of the memory to pass through the matching element 13. The clock input from the generator 1 clock pulse output arrives at the synchronizing input of the 13-step element. Clocking of the matching element 13 is necessary to eliminate the decoder interference that occurs when working on the decoders 6.t-6.N, After the block signal 8, {the memory is rewritten into the memory block 14, the trigger 12 is set to one. The logical zero signal from the inverse output of the trigger 12 is fed to the input of the valve 10 and to the third input of the block 13 of coincidence and closes them, passing through the subsequent fault signals. The trigger 12 works as a latch, providing testing and indication of the first. time of interrogation of a signal of malfunction and prohibition of indication of subsequent signals of malfunction.

The output code of the IL 11 element enters the input of the coincidence element 13 and if there are logical units at its other inputs from the inverse output of the trigger 12 and a clock pulse from generator 1 passes to the input of the matching element 13 and then to the input of memory block 14.

In the initial state, at the output of the flip-flops of the memory block 14 there is a logical zero. If there is a fault, the S-inputs of the triggers of the memory block 14 receive signals in the form of a logical zero or in the form of a logical unit represented by a pulse equal in duration to the clock pulse. With these pulses, the triggers of the memory block 14 are set to one. As a result, the output code ci of the matching element 13 is triggered by the triggers of the memory block 14. When closing element 13 match the cut-off signal with

an inverse output of the trigger 12 at the output of the matching element 13 is set to a zero code, which does not affect the triggers of the memory block 14.

The recorded binary code is stored in memory block 14 until the arrival of a reset pulse from generator 2.

From the output of the memory block 14, the binary code is input to the converter of the 15 codes, in which it is converted into the binary-decimal 16 required for the operation of the indicator, with the output of the converter 15

the binary-decimal code enters the indicator 16, which highlights the decimal digits corresponding to the number 5 of the faulty functional part of the equipment.

Thus, the device provides a visual indication of 10 numbers that failed functional (Parts of electronic equipment, i.e., an on-line diagnostics mode is performed with an accuracy of the defective part of the equipment, which expands the functionality of the device

Claims (2)

1. DEVICE FOR CONTROL OF RADIO ELECTRONIC EQUIPMENT, containing the first and second elements OR, first matching elements, characterized in that, in order to expand the functionality of the device, a clock pulse generator, a reset pulse generator, a shift register, a control signal shaper, a generator are introduced into it tests, the first decoders, read-only memory blocks, a gate, a counting trigger, a second coincidence element, a random access memory block, a code converter and an indicator, and the clock generator output pulses are connected to the sync inputs of the second coincidence element, the driver of the control signal, the shift register and the reset pulse generator, connected by the output to the installation inputs of the RAM block, the shift register, with ((the input of the counting trigger and the installation input of the shaper. control signal connected by the output through test generator with the outputs of the device, and directly with the information input of the shift register connected by the outputs to the first inputs of the corresponding first matching elements connected by the second inputs through the corresponding first decoders with the corresponding inputs of the device, and the outputs with the inputs of the corresponding blocks of read-only memory and with the inputs of the first OR element, connected by the output to the first input - the input of the counting trigger connected by an inverse output to the second input of the second coincidence element, connected by the third input to the output of the second OR element, connected by the inputs to the outputs, respectively uyuschih permanent memory blocks of RAM data input unit connected 'with the output of the second matching element via the converter output codes to the input indicator. 2. The device according to p. 1, characterized in that the driver of the control signal comprises a counter connected by a counting input to the sync input of the driver, the installation input to the installation input of the driver, outputs from the inputs of the second decoder connected to the outputs of the outputs of the driver. 00 tO ςπ