JP3285524B2 - Bit error measurement device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit error measuring device for measuring a bit error contained in a digital signal, and more particularly, to converting an input signal into a parallel signal having a plurality of bits and then converting each bit value of the parallel signal. The present invention relates to a bit error measuring device for measuring an error of a bit.

[0002]

2. Description of the Related Art In digital communication networks,
In order to ensure the reliability of data transmitted through this digital communication network, bit errors in digital signals transmitted through this digital communication network at regular intervals at the time when this digital communication network is newly constructed and after operation. Measurements need to be performed.

[0003] Generally, as a method of performing a bit error measurement of a digital signal, a reference pattern signal such as a pseudo random pattern (PRBS) signal is applied to a communication device or a transmission line to be measured using a reference signal generator. And
The bit pattern of the signal that has passed through the measurement target is measured to determine how much bit error is included in the bit pattern of the original reference pattern signal.

As a specific method of measuring the error rate,
The bit error rate of the input signal obtained from the measurement target and the reference pattern signal is calculated by counting the bit errors output from a bit error detection circuit including an exclusive OR circuit or the like.

However, when the frequency of the bit rate (data transmission rate) of the digital signal is increased to a level exceeding Gb / s, it is necessary to prepare high-performance and expensive electronic components which operate normally at this high frequency. The whole will be expensive.

In order to eliminate such inconvenience, the digital signal is converted into a parallel signal having a plurality of bits by using a serial / parallel converter, thereby reducing the bit rate of the plurality of signals constituting the parallel signal. Let it. Then, a method is generally used in which bit errors of each signal whose bit rate has been reduced are detected, and they are summed to obtain the number of bit errors of the original digital signal.

FIG. 3 is a schematic block diagram of a bit error measuring device employing the above-described serial / parallel conversion processing. An input signal a having a bit rate of f, for example, composed of a PRBS signal that has passed through the measurement target and is input from the input terminal 1 is converted by the serial / parallel converter 2 into a parallel input signal A having, for example, an N-bit configuration. Therefore, the parallel input signal A includes N signals a ₁ , a ₂ ,..., A _N whose bit rates are respectively reduced to 1 / N of the frequency f of the input signal a. The parallel input signal A is input to the next error detector 3.

The clock recovery circuit 4 recovers the clock signal c ₀ having the frequency f included in the input signal a and sends it to the next switching circuit 7. The switching circuit 7 has an input terminal 6
Either the clock signal c ₀ was recovered clock signal c ₁ and inputs the select to, as a new clock signal c, and sends it to the frequency divider 5. The frequency divider 5 divides the frequency f of the selected clock signal c by 1 / N to obtain a new clock signal c ₂ , the reference pattern signal generator 8, the error detector 3, the synchronization controller 9, the error rate Apply to calculation unit 10.

The reference pattern signal generator 8 synchronizes with the input clock signal b ₂ to generate a pseudo random pattern (PRBS) signal having the same bit pattern as the pseudo random pattern (PRBS) signal applied to the object to be measured. Is output as an N-bit parallel reference signal D in the same manner as the serial / parallel converter 2.

Therefore, as shown in FIG. 4, the parallel reference signal D output from the reference pattern signal generator 8 has N bit rates reduced to 1 / N of the bit rate f of the input signal a. The signals d ₁ , d ₂ ,..., D
_N is included.

As is well known, PRB before serial / parallel conversion
The S signal is represented by n, where G is the number of stages of the shift register.
= (2 ^G -1). Therefore, as shown in FIG. 4, n pieces of data are sequentially allocated to N pieces of signals d ₁ , d ₂ ,..., D _N. Each of the 1st to Nth bit data constituting one frame (1 bit period) is converted into N signals d ₁ , d ₂ ,.
The signal to be assigned to d _N is defined as a “bit array”. The N-bit parallel reference signal D output from the reference pattern signal generator 8 is input to the error detector 3.

The error detection unit 3 is composed of, for example, of N exclusive-OR circuit, in synchronization with the rising timing of the clock signal c ₂ being applied to the trigger terminal, and a parallel input signal A Each bit value of each signal a ₁ , a ₂ ,..., A _N and each signal d ₁ , d constituting the parallel reference signal D
_2, ..., by comparing each with each bit value of d _N, when they are different only, bit error signal e ₁ of high level,
e _2, ... parallel the error signal E error rate calculation unit 1 consisting of e _N
0 to the synchronization control unit 9.

The synchronization control section 9 has a function of synchronizing the parallel reference signal D output from the reference pattern signal generation section 8 with the parallel input signal A. Also, the bit arrangement indicating the data allocation for each signal d ₁ , d ₂ ,..., D _N in the parallel reference signal D matches the bit arrangement of the parallel input signal A data allocated by the serial / parallel converter 2. Not necessarily. For example, when N = 4, as shown in FIG.
There are four types of bit arrangements of the parallel input signal A output from the serial / parallel conversion unit 2, (1) to (4).

As a result, since the parallel reference signal D is not synchronized with the parallel input signal A at the time of activation of the bit error measuring device, the bit error signal e is continuously output from the error detector 3 for each clock. ₁ , e ₂ ,..., E _N are output.

The synchronization controller 9 establishes synchronization between the parallel reference signal D and the parallel input signal A in accordance with the flowchart of FIG. In S (step) 1, the index j specifying the bit arrangement of the parallel input signal A is set to an initial value of 1, and in S2, the reference pattern signal generator 8
Is set to an initial value of 1 for specifying the output timing of the parallel reference signal D from.

Then, the parallel error signal E output from the error detector 3 is fetched, and the bit error signals e ₁ , e
It is checked whether ₂ ,..., E _N are output. When the bit error signals e ₁ to _N are continuously output (S
4) Since the synchronization has not been established, it is confirmed that the index i has not reached the final index i _E obtained from the value (n / N) obtained by dividing the bit period n of the bit pattern by the number N of bit arrays (S5). ). A bit shift command g for shifting the output timing of the parallel reference signal D from the reference pattern signal generator 8 by one clock (1 bit).
Is transmitted to the reference pattern signal generator 8 (S6). Then, 1 is added to the index i (S7), the process returns to S3, and the parallel error signal E is fetched again.

In S5, if the index i has reached the final index i _E but synchronization is not established, it is determined that the bit arrangement of the parallel reference signal D and the bit arrangement of the parallel input signal A do not match. I do. The process proceeds to S8, to make sure that the index j for specifying a bit sequence of parallel input signals A has not reached the final index j _E represented by the bit sequence number N (S8).

In S9, a bit arrangement change command h is sent to the serial / parallel converter 2. Upon receiving the change instruction h, the serial / parallel converter 2 shifts (prohibits) the fetch timing of each data of the input signal a by one bit, thereby changing the bit arrangement shown in FIG. To the bit array. Then, 1 is added to the index j (S10), the process returns to S2, and the index i for specifying the output timing of the parallel reference signal D is set to 1
And the parallel error signal E is fetched again.

Finally, at S4, the parallel reference signal D
When the synchronization between the signal and the parallel input signal A is established, a synchronization establishment signal k is sent to the error rate calculator 10. Error rate calculator 1
0, upon receiving the synchronization establishment signal k, takes in the parallel error signal E output from the error detection unit 3 and
_1, e _2, ..., by summing the e _N number, we calculate the error rate in the input signal a.

[0020]

However, the bit error measuring device shown in FIG. 3 still has the following problems to be solved. That is, the parallel input signal A output from the serial / parallel converter 2 in the synchronization controller 9 and the parallel reference signal D output from the reference pattern signal generator 8
As shown in the flow chart of FIG. 6, the synchronization establishment process between the index i specifying the output timing of the parallel reference signal D and the index j specifying the bit arrangement of the parallel input signal A is sequentially performed. went changed, the error signal e ₁ of the parallel error signal a output from the error detecting unit 3 of each combination, e _2, ..., it is determined whether a synchronization establishment examines e _N number.

Therefore, in the worst case, i _E × j _E =
It is necessary to read and determine the parallel error signal A [(2 ^G -1) / N] × [N] times. For example, when G = 9, it is necessary to perform (2 ⁹ −1) = 511 times.
As a result, there is a problem that the synchronization establishment processing time is increased and the bit error rate measurement processing efficiency for the input signal of the bit error measurement device is greatly reduced.

The present invention has been made in view of such circumstances, and by providing a frame detection unit for detecting a frame of a bit pattern of a parallel input signal, the synchronization control unit can control the parallel input signal with respect to the parallel reference signal. It is an object of the present invention to provide a bit error measuring device capable of omitting a search process for a suitable bit array, reducing the number of times of reading an error signal, shortening a processing time required for establishing synchronization, and improving a bit error rate measurement processing efficiency.

Further, by adding a function of detecting a bit value in the serial direction to the frame detection unit, synchronization can be established by a single setting process, and the bit error rate measurement processing efficiency can be further improved. It is intended to provide a device.

[0024]

According to a first aspect of the present invention, there is provided a bit error measuring device which converts an externally input signal having a bit pattern of a predetermined period into a parallel input signal having a plurality of bits. A serial / parallel converter for converting, a frame detector for detecting a bit pattern frame in a parallel input signal output from the serial / parallel converter to detect a bit arrangement in a parallel direction, and the same as the bit pattern of the input signal A reference pattern signal generator that outputs the bit pattern as a parallel reference signal having a plurality of bits, and a bit arrangement in a parallel direction of the parallel input signal detected by the frame detector are rearranged to obtain a reference pattern. A bit array rearranging unit for matching the bit array in the parallel direction of the parallel reference signal output from the signal generating unit; An error detection unit that compares the parallel input signal output from the array rearrangement unit with the parallel reference signal output from the reference pattern signal generation unit and outputs an error signal when there is a mismatch, and outputs the error signal from the error detection unit The output timing of the parallel reference signal output from the reference pattern signal generator is adjusted so that the error signal is equal to or less than a prescribed amount, and the output timing of the parallel input signal and the parallel reference signal output from the bit arrangement rearranging unit is adjusted. A synchronization control unit that establishes synchronization, and an error rate calculation unit that calculates a bit error rate of an input signal based on an error signal output from the error detection unit after synchronization is established by the synchronization control unit. Have.

In the bit error measuring device configured as described above, the frame detector detects a frame of a bit pattern in the parallel input signal output from the serial / parallel converter and detects a bit arrangement in the parallel direction. . That is, in the serial / parallel converter, the frame detector detects which bit arrangement has been converted to a parallel input signal.

On the other hand, the reference pattern signal generator outputs a parallel reference signal having a predetermined reference bit arrangement. The bit arrangement rearranging unit converts the bit arrangement of the parallel input signal having the bit arrangement known by the frame detection unit into the reference bit arrangement of the parallel reference signal. That is, the arrangement of each signal constituting the parallel input signal is matched with the arrangement of each signal constituting the parallel reference signal.

Therefore, in this state, the synchronization control unit obtains synchronization between the parallel input signal and the parallel reference signal only by adjusting the output timing of the parallel reference signal output from the reference pattern signal generation unit. be able to.
As a result, at least the time required for the synchronization establishment processing is reduced by the processing time for sequentially changing the bit arrangement. Therefore, the bit error measurement processing efficiency in the entire bit error measurement device is improved.

According to another aspect of the present invention, there is provided a bit error measuring device, comprising: a serial / parallel converter for converting an externally input input signal having a bit pattern of a predetermined period into a parallel input signal having a plurality of bits; A frame detector that detects a frame of a bit pattern in a parallel input signal output from a parallel / parallel converter and detects a bit arrangement in a parallel direction and a bit value in a serial direction, and a bit pattern identical to the bit pattern of the input signal A reference pattern signal generating unit that outputs this bit pattern as a parallel reference signal having a plurality of bits, and a bit pattern in a parallel direction of the parallel measurement signal detected by the frame detecting unit is rearranged to generate a reference pattern signal. A bit arrangement rearranging unit for matching the bit arrangement in the parallel direction of the parallel reference signal output from the unit, and a reference pattern An output timing setting unit that matches the output timing of each bit in the serial direction of the parallel reference signal output from the signal generation unit with each bit in the serial direction detected by the frame detection unit; An error detector that compares the parallel input signal with the parallel reference signal output from the reference pattern signal generator and outputs an error signal when there is a mismatch, and an input signal based on the error signal output from the error detector. An error rate calculator for calculating a bit error rate.

In the bit error measuring device configured as described above, the frame detecting unit performs not only the above-described parallel bit arrangement in the parallel input signal output from the serial / parallel conversion unit but also each bit value in the serial direction. Has been detected. That is, the output timing of the bit pattern sequence when the bit pattern sequence of the input signal is converted in parallel is detected.

The output timing setting section matches the output timing of each bit in the serial direction of the parallel reference signal output from the reference pattern signal generation section with the output timing of each bit in the serial direction detected by the frame detection section. Let me.

Therefore, at this time, the output timings of the parallel reference signal and the parallel input signal in the bit pattern coincide with each other. Therefore, in order to synchronize the two, the process of sequentially changing the output timing of the parallel reference signal is performed. unnecessary. Therefore, synchronization between the parallel input signal and the parallel reference signal can be immediately established by the bit arrangement rearranging unit and the output timing setting unit without performing any trial and error.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of a bit error measuring device according to a first embodiment of the present invention. The same parts as those of the conventional bit error measuring device shown in FIG. Therefore, the detailed description of the overlapping part is omitted.

An input signal a externally input via the input terminal 1 is input to the serial / parallel converter 2. The serial / parallel converter 2 converts the input signal a into an N-bit parallel input signal A. As shown in FIG. 5, the serial / parallel-converted parallel input signal A has N signals a ₁ ,
a ₂ ,..., a _N.

Then, each data included in the input signal a is converted into N signals a ₁ , a ₂ ,.
indicates allocate to which the signal of a _N "bit sequence"
Depends on the signal to be written next at the time when the head data of the bit pattern constituting one frame in the input signal a input to the serial / parallel converter 2 is input. Therefore, for example, (1) to (4) shown in FIG.
Which “bit array” of the “bit array” (in the case of N = 4) is not uniquely determined.

The parallel input signal A output from the serial / parallel converter 2 is input to the bit arrangement rearranging section 11 and the frame detecting section 12. The frame detection unit 12 stores a bit pattern of one frame of the pseudo random pattern of the input signal a in the internal storage unit, and outputs the signals a ₁ , a _{2 ,.} Each bit value (data value) in the serial direction (time direction) is read and each signal a
_From the array of bit values in the serial direction of ₁ , a ₂ ,..., A _N , the bit array of the corresponding parallel input signal A in the parallel direction is N
It detects which bit array of the type of bit array. The frame detection unit 12 sends the detected bit arrangement of the parallel input signal A to the bit arrangement rearranging unit 11.

On the other hand, the reference pattern signal generator 8
As shown in, in synchronism with the clock signal c ₂ to be input,
Each bit data of a pseudo-random pattern (PRBS) having the same signal pattern as the input signal a is output as an N-bit parallel reference signal D as in the serial / parallel converter 2.

Therefore, the parallel reference signal D output from the reference pattern signal generator 8 is composed of _N signals d ₁ , d ₂ ,..., D _N as shown in FIG. An N-bit reference parallel signal D is output. The bit sequence of the parallel direction of the reference parallel signal D is the bit sequence leading data [1] is set in the bit pattern of one frame signal d _1. The N-bit reference parallel signal D having the reference bit array is sent to the error detection unit 3.

The bit array rearranging section 11 converts the bit array of the parallel input signal A having the bit array known by the frame detecting section 12 into the reference of the parallel reference signal D output from the reference pattern signal generating section 8. The order of arrangement of the _N signals a ₁ , a ₂ ,..., A _N is changed so as to match the bit arrangement.

For example, as shown in FIG. 5, N = 4, and the bit arrangement of (1) is the reference bit arrangement of the reference parallel signal D. When the bit array of the parallel input signal A detected by the frame detection unit 12 is the bit array of (4), the signals a ₂ → a ₁ , a ₃ → a ₂ , a ₄ → a ₃ , a ₁
→ to move the contents of each signal to a _4, and the signal a ₂ after the movement, a _3, to shift the data of a ₄ to 1 bit backwards. As a result, the bit array of (4) is converted to the basic bit array of (1).

The bit arrangement rearranging section 11 sends the parallel input signal A in which the pit arrangement matches the basic bit arrangement to the error detection section 3. Error detecting unit 3 in synchronization with the rising timing of the clock signal c ₂ being applied to the trigger terminal, each signal a _1, a constituting the parallel input signals A
_2, ..., the signals d _1, d ₂ of a parallel reference signal D and the bit values of a _N, ..., by comparing each with each bit value of d _N, when they are different only in a high level The parallel error signal E including the bit error signals e ₁ , e ₂ ,... E _N is sent to the error rate calculator 10 and the synchronization controller 13.

The synchronization control unit 13 performs synchronization establishment processing between the parallel input signal A output from the bit arrangement rearranging unit 11 and the parallel reference signal D output from the reference pattern signal generation unit 8. Since the bit arrangement of the parallel input signal A and the bit arrangement of the parallel reference signal D already match,
Each signal a ₁ , a ₂ ,..., A _N and each signal d ₁ , d ₂ ,.
It is only necessary to synchronize with d _N.

That is, while shifting the output timing of the parallel reference signal D output from the reference pattern signal generator 8 by one bit (one clock), each of the parallel error signals E output from the error detector 3 is shifted. Error signals e ₁ and e
_2, ..., it is determined that synchronization is established when the e _N number falls below a specified value, transmits a synchronization establishment signal k to the error calculating unit 10.

The error rate calculation unit 10, upon receiving the synchronization establishment signal k, is captures and parallel error signal E output from the error rate detection unit 3, the error signal _{e 1, e 2, ...,} e N number To calculate the error rate of the input signal a.

In the bit error measuring device configured as described above, the frame detector 12 detects the frame of the bit pattern constituting the original input signal a in the parallel input signal A output from the serial / parallel converter 2. It is detected whether or not the bit sequence of the corresponding parallel input signal A is detected. That is, when the input signal a is input to the serial / parallel converter 2,
(1) It is detected which of the N types of bit arrays from (N) has been converted to the parallel input signal A having the bit array.

On the other hand, the reference pattern signal generator 8 outputs a parallel reference signal D having a predetermined reference bit arrangement shown in FIG. The bit arrangement rearranging unit 11 converts the bit arrangement of the parallel input signal A having the bit arrangement known by the frame detection unit 12 into the reference bit arrangement of the parallel reference signal D. That is, each signal forming a parallel input signal _{A a 1, a 2, ...} , parallel array of a _N reference signal D
Each signal constituting the d _1, d _2, ..., to match the sequence of d _N.

Therefore, in this state, the synchronization control unit 13 only adjusts the output timing of the parallel reference signal D output from the reference pattern signal generation unit 8 and controls the timing between the parallel input signal A and the parallel reference signal D. Can be established. As a result, at least the time required for the synchronization establishment processing is reduced by the processing time for sequentially changing the bit arrangement.

Therefore, the bit error measurement processing efficiency of the entire bit error measurement device is improved as compared with the conventional bit error measurement device shown in FIG. (Second Embodiment) FIG. 2 is a block diagram showing a schematic configuration of a bit error measuring device according to a second embodiment of the present invention. The same parts as those of the bit error measuring device of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description of the overlapping parts will be omitted.

In the apparatus of the second embodiment, an output timing setting section 14 is newly provided by eliminating the synchronization control section 13 in the apparatus of the first embodiment shown in FIG. The frame detection unit 12a detects the bit arrangement in the parallel direction of the N-bit parallel input signal A output from the serial / parallel conversion unit 2, and detects each of the N pieces of the parallel input signal A. The signals a ₁ , a ₂ ,. a. Read each bit value (data value) in the serial direction of _N. That is, the output timing of the bit pattern sequence when the bit pattern sequence of the input signal a is converted in parallel is detected.

The frame detector 12a sends the detected bit arrangement to the bit arrangement rearranging section 11, and sends the output timing of the bit pattern sequence to the output timing setting section 14.

The output timing setting section 14 sets each bit value ( _N ) of the _N signals d ₁ , d ₂ ,..., D _N constituting the parallel reference signal D output from the reference pattern signal generation section 8 in the serial direction. The output timing of the data value), that is, the output timing of the bit pattern sequence of the PRBS signal that is the basis of the parallel reference signal D, is made to coincide with the output timing detected by the frame detection unit 12a.

Therefore, at this point, the parallel input signal A and the parallel reference signal D have the same bit arrangement in the parallel direction, and furthermore, the parallel input signal A and the parallel reference signal D constitute one frame. For example, the output timing of the first bit (data) in the corresponding bit pattern matches.

Therefore, in the second embodiment, in order to synchronize the parallel input signal A and the parallel reference signal D, as shown in the first embodiment of FIG. There is no need to perform the processing for changing the timing in order.

Therefore, the parallel input signal A and the parallel reference signal D
Can be immediately established by the bit arrangement rearranging unit 11 and the output timing setting unit 14 without performing any trial and error.

Therefore, in the bit error measuring device of the second embodiment, the bit error measuring device of the first embodiment shown in FIG. Even in comparison, the bit error measurement processing efficiency is further improved.

[0055]

As described above, the bit error measuring device of the present invention is provided with the frame detecting section for detecting the frame of the bit pattern of the parallel input signal and detecting the bit arrangement. Is used to match the bit arrangement of the parallel input signal with the bit arrangement of the parallel reference signal.

Therefore, it is possible to omit the process of searching for a suitable bit array of the parallel input signal with respect to the parallel reference signal in the synchronization control unit, to reduce the number of times of reading an error signal, and to shorten the processing time required for establishing synchronization. The bit error rate measurement processing efficiency can be improved.

Further, a function of detecting not only the bit arrangement in the parallel direction but also the bit value in the serial direction is added to the frame detection unit. Therefore, the synchronization between the parallel input signal and the parallel reference signal can be established by one setting process, and the bit error rate measurement processing efficiency can be further improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a bit error measuring device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a bit error measuring device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a conventional bit error measuring device.

FIG. 4 is a time chart of each signal constituting a parallel reference signal output from a basic pattern signal generator.

FIG. 5 is a diagram illustrating each possible bit arrangement of a parallel input signal output from a serial / parallel unit;

FIG. 6 is a flowchart showing the operation of the synchronization control unit of the conventional bit error measuring device.

[Explanation of symbols]

 2 Serial / parallel conversion unit 3 Error detection unit 4 Clock recovery circuit 5 Frequency divider 8 Basic pattern signal generation unit 10 Error rate calculation unit 11 Bit arrangement rearrangement unit 12, 12a Frame detection unit 13 ... Synchronization control unit 14 ... Output timing setting unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 1/00 H04L 29/14 H04L 7/00 H04J 3/00

Claims (2)

(57) [Claims] 1. A serial / parallel converter (2) for converting an externally input input signal having a bit pattern of a predetermined period into a parallel input signal having a plurality of bits, and an output from the serial / parallel converter. A frame detection unit (12) that detects a frame of the bit pattern in the parallel input signal and detects a bit arrangement in the parallel direction, and has the same bit pattern as the bit pattern of the input signal. A reference pattern signal generation unit (8) that outputs a parallel reference signal having a bit configuration, and rearranges a bit arrangement in a parallel direction of the parallel input signal detected by the frame detection unit, and is output from the reference pattern signal generation unit. A bit arrangement rearranging unit (11) for matching the bit arrangement of the parallel reference signal in the parallel direction, and a parallel input signal output from the bit arrangement rearranging unit. An error detection unit (3) that compares the signal with the parallel reference signal output from the reference pattern signal generation unit and outputs an error signal when there is a mismatch, and an error signal output from the error detection unit is a specified amount. Adjusting the output timing of the parallel reference signal output from the reference pattern signal generation unit so that the synchronization between the parallel input signal output from the bit arrangement rearranging unit and the parallel reference signal is established as follows. A synchronization control unit (13) for performing a synchronization, and after the synchronization is established in the synchronization control unit, an error rate for calculating a bit error rate of the input signal based on an error signal output from the error detection unit A bit error measurement device comprising a calculation unit (10). 2. A serial / parallel converter (2) for converting an externally input input signal having a bit pattern of a predetermined period into a parallel input signal having a plurality of bits, and an output from the serial / parallel converter. A frame detector (12a) for detecting a frame of the bit pattern in the parallel input signal and detecting each bit value in the parallel direction and each bit value in the serial direction; and a bit pattern identical to the bit pattern of the input signal. A reference pattern signal generator (8) that outputs this bit pattern as a parallel reference signal having a plurality of bits, and a rearrangement of a parallel bit arrangement of the parallel measurement signal detected by the frame detector, the reference pattern A bit arrangement rearranging section (11) for matching the bit arrangement in the parallel direction of the parallel reference signal output from the signal generation section; and An output timing setting unit (14) that matches the output timing of each bit in the serial direction of the parallel reference signal output from the unit with each bit in the serial direction detected by the frame detection unit; and An error detection unit (3) that compares the output parallel input signal with the parallel reference signal output from the reference pattern signal generation unit and outputs an error signal when there is a mismatch, and outputs the error signal from the error detection unit. An error rate calculator (1) that calculates a bit error rate of the input signal based on the error signal
0).