JP3138598B2 - Delay measurement method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a passive double star (hereinafter, PDS) for performing bidirectional communication between an intra-office device and a plurality of subscriber devices via a star coupler disposed on a transmission line.
The present invention relates to a transmission method, and particularly to a delay measurement method for measuring a delay difference of a transmission signal based on a transmission path distance between an intra-station device and each subscriber device.

[0002]

2. Description of the Related Art As an apparatus for measuring a delay difference of a transmission signal based on a transmission path distance between an intra-office apparatus and each subscriber apparatus, FIG.
There is a device as shown in FIG. 2, a transmission line frequency oscillator 21, a separation circuit 22 for inputting a signal from a subscriber unit, a delay measurement command receiving circuit 23 for inputting one output of the separation circuit 22, a delay measurement command generation A circuit 24, an insertion circuit 25 to which the main signal A to the subscriber unit and one output of the delay measurement command generation circuit 24 are input, an output of the transmission line frequency oscillator 21, an output of the delay measurement command reception circuit 23, and delay measurement It comprises a counter 26 to which each of the other outputs of the command generation circuit 24 is input.

The transmission line frequency oscillator 21 outputs a clock signal required for transmitting a signal to the subscriber unit. The delay measurement command generation circuit 24
Is a delay measurement start command B addressed to each subscriber unit to measure a signal delay difference between the intra-office unit and each subscriber unit.
A delay measurement start command output timing signal C is generated and output. The counter 26 has a transmission line frequency oscillator 2
One output clock is counted, and the start timing of the count is determined by the output timing signal C from the delay measurement command generation circuit 24.

The delay measurement start command B from the delay measurement command generation circuit 24 is output to the insertion circuit 25, inserted into the main signal A to the subscriber unit by the insertion circuit 25, and output to the subscriber unit. Upon recognizing that the delay measurement command addressed to the own device has been transmitted, the subscriber device transmits response data to the intra-office device. The main signal including the response data output from the subscriber unit is separated by the separation circuit 22 into the main signal F.
, And outputs the response data (delay measurement command) to the delay measurement command receiving circuit 23. The delay measurement command receiving circuit 23 determines whether or not the response is a response to the delay measurement command from the subscriber device performing the delay measurement, and if it is determined that the response is the delay measurement command from the corresponding subscriber device, , Outputs a count stop signal D to the counter 26.

Accordingly, the delay measurement result E output from the counter 26 is determined by the above-described count stop signal D and then stopped by the above-described count stop signal D after the counter 26 starts counting with the output timing signal C from the delay measurement command generation circuit 24. It can be obtained as a count value until it is performed.
That is, the count value of the counter 26 is equal to 1 of the transmission line frequency.
This value is based on a clock, and indicates a delay difference of a signal transmitted on a transmission path between the subscriber unit and the intra-office unit.

[0006]

In such a conventional delay measuring device, the signal delay difference from the subscriber unit to the intra-station device is measured by operating the counter at the transmission line frequency. When the frequency of the device becomes high, the device must be operated at a high speed, and there is a disadvantage that power consumption increases. Accordingly, an object of the present invention is to suppress an increase in power consumption of a measuring device when measuring a signal delay difference from a subscriber device to an intra-station device.

[0007]

SUMMARY OF THE INVENTION In order to solve such a problem, the present invention relates to an n frequency dividing circuit for dividing a frequency by n by inputting a transmission line clock, and a counter for counting the output of the n frequency dividing circuit. A first latch circuit for latching the output of the counter every time a transmission reference timing signal indicating a transmission reference of data to be transmitted to a transmission line is input, and converting serial data received from the transmission line into 1: n parallel data A 1: n serial-to-parallel conversion circuit, a synchronization circuit that generates a reception timing signal based on the output of the 1: n serial-to-parallel conversion circuit, a second latch circuit that latches an output of the counter for each input of the reception timing signal, A local circuit is provided with a subtraction circuit for calculating the difference between the outputs of the first and second latch circuits and an addition circuit for multiplying the output of the subtraction circuit by n and outputting the result as a delay measurement result. Further, an encoding circuit for inputting synchronization information generated by the synchronization circuit based on the output of the 1: n serial-parallel conversion circuit and indicating the start position of the received data and for digitizing the same is provided in the intra-station device, and the addition circuit is multiplied by n. The output of the encoding circuit is added to the output of the subtraction circuit to output a delay measurement result.

[0008]

The transmission line clock is divided by n and counted, and this count output is latched by the first latch circuit each time a data transmission reference timing is input, while the second latch circuit is latched by each reception timing input. And the subtraction circuit obtains the difference between the outputs of the first and second latch circuits, and the addition circuit multiplies this difference by n to calculate a delay measurement result. As a result, even if the frequency of the transmission line becomes high, the transmission line clock is not directly counted, so that an increase in power consumption of the device can be suppressed. In addition, synchronization information indicating the head position of the received data is digitized and added to the output of the subtraction circuit multiplied by n, and the result is output as a delay measurement result.
As a result, an accurate delay measurement result can be obtained.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. The apparatus of this embodiment is provided in a PDS transmission system in which an intra-office apparatus and a plurality of subscriber apparatuses perform bidirectional communication via a star coupler disposed on a transmission line, and transmits data between the intra-office apparatus and the subscriber apparatus. It measures the delay difference of the data to be obtained. By the way, the intra-station device performs an operation of aligning the phases of the signals on the signal transmitting side, which is the transmission direction from the intra-station device to the subscriber device, and the signal receiving side, which is the transmission direction from the subscriber device to the intra-station device. The apparatus of this embodiment is provided in such an intra-office apparatus.

In FIG. 1, reference numeral 1 denotes an n frequency dividing circuit for inputting a transmission line clock a output from, for example, the transmission line frequency oscillator 21 shown in FIG. 2 and dividing the frequency by n (n is a natural number);
A counter for inputting and counting the output of the frequency dividing circuit 1;
Is a first latch circuit for inputting a transmission reference timing signal b such as an output timing signal output from the delay measurement command generation circuit 24 shown in FIG. A second latch circuit 5 for inputting a reception timing signal c to be transmitted and a transmission line data d, which is serial data received, are converted into parallel data by a 1: n serial-parallel conversion circuit (hereinafter, serial-parallel conversion circuit). ).

Reference numeral 6 denotes a synchronization circuit which receives the output of the serial-parallel conversion circuit 5 and generates and outputs the above-mentioned reception timing signal c and synchronization information e. Reference numeral 7 denotes an encoding circuit which receives and digitizes the synchronization information e. A circuit 8, a subtraction circuit for inputting and calculating each output of the first latch circuit 3 and the second latch circuit 4, 9
Is an adder circuit which receives and adds the output of the subtraction circuit 8 and the output of the encoding circuit 7 and outputs a delay measurement result f.

Next, a description will be given of a delay measuring operation of the apparatus according to the present embodiment configured as described above. Transmission line clock a
Is commonly used by the signal transmitting side and the signal receiving side. Here, when the transmission line clock a is input, the n-frequency dividing circuit 1 divides the input clock by n and outputs it to the counter 2. The counter 2 counts the input clock divided by n. The first latch circuit 3 that inputs the output of the counter 2 and the transmission reference timing signal b latches the output of the counter 2 every time the transmission reference timing signal b is input.

On the other hand, the serial-parallel conversion circuit 5 that inputs the transmission line data d converts the input data into 1: n parallel data and outputs it to the synchronization circuit 6. The synchronization circuit 6 synchronizes the transmission line data from the input data, and
And synchronization information e. The second latch circuit 4 that inputs the output of the counter 2 and the reception timing signal c from the synchronization circuit 6 latches the output of the counter 2 every time the reception timing signal c is input. In this case, the subtraction circuit 8
Inputs the respective outputs of the first latch circuit 3 and the second latch circuit 4, calculates the difference between the two outputs, and outputs the difference to the adder circuit 9.

By the way, the synchronization information e output from the synchronization circuit 6 indicates at which position from 1 to n the head of the received data is located in a state of being developed in a parallel ratio of 1: n. The encoding circuit 7 that inputs such synchronization information inputs the synchronization information e indicating the bit position (the head position of the received data), converts it into a numerical value of 1 to n, and outputs the numerical value to the addition circuit 9. The adding circuit 9 adds the output of the encoding circuit 7 to the result obtained by multiplying the output of the subtracting circuit 8 by n, and outputs the result as a delay measurement result f. Delay measurement result f obtained by such calculation
Indicates how many bits the delay difference is based on one clock of the transmission line frequency.

As described above, in the present embodiment, when measuring the signal delay difference based on the transmission path distance between the intra-office apparatus and each subscriber apparatus, the result of dividing the transmission path clock by n is counted. Therefore, there is no need to perform the counting operation at a higher speed than in the conventional device, and therefore an increase in power consumption of the device can be suppressed. In addition, since the transmission line data is expanded in parallel using the synchronization information to correct the error in the head position of the received data, the signal delay difference can be reduced with the same accuracy as compared to a device operating at the same speed as the transmission line frequency. Can be measured.

[0016]

As described above, according to the present invention,
The transmission line clock is frequency-divided by n and counted, and the count output is latched by the first latch circuit for each input of data transmission reference timing, while the second latch circuit is latched for each input of reception timing. At the same time, the subtraction circuit obtains the difference between the outputs of the first and second latch circuits, and the addition circuit multiplies this difference by n to calculate the delay measurement result. However, since the transmission line clock is not directly counted, an increase in power consumption of the device can be suppressed. Further, since the synchronization information indicating the head position of the received data is digitized and added to the output of the subtraction circuit multiplied by n and output as a delay measurement result, a highly accurate delay measurement result can be obtained. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an apparatus to which a delay measurement method according to the present invention is applied.

FIG. 2 is a block diagram of a conventional device.

[Explanation of symbols]

1 ... n frequency dividing circuit, 2,26 ... counter, 3 ... first latch circuit, 4 ... second latch circuit, 5 ... serial-parallel conversion circuit,
6 synchronization circuit, 7 encoding circuit, 8 subtraction circuit, 9 addition circuit, a transmission line clock, b transmission reference timing signal, c reception timing signal, d transmission line data, e
... Synchronization information, f ... Delay measurement result.

Claims (2)

(57) [Claims] 1. A passive double-star transmission system in which an intra-office device and a plurality of subscriber devices perform bidirectional data communication based on a transmission line clock via a star coupler disposed on the transmission line. To divide by n (n is a natural number)
A frequency dividing circuit, a counter for counting the output of the n frequency dividing circuit, a first latch circuit for latching the output of the counter for each input of a transmission reference timing signal indicating a transmission reference of data to be transmitted to the transmission line, Serial-to-parallel conversion circuit for converting serial data received from a channel into 1: n parallel data, a synchronizing circuit for generating a reception timing signal based on the output of the serial-parallel conversion circuit, and an output of a counter for each input of the reception timing signal A second latch circuit for latching the first and second latch circuits;
A subtraction circuit for calculating the difference between the outputs of the latch circuits of the above, and an addition circuit for multiplying the output of the subtraction circuit by n and outputting the result as a delay measurement result. A delay measurement method, wherein a delay difference of a transmission signal based on a path distance is measured. 2. The delay measuring system according to claim 1, wherein the encoding circuit inputs synchronization information generated by the synchronization circuit based on an output of the serial-parallel conversion circuit and indicating a head position of the received data and digitizes the synchronization information. A delay measurement system provided in an intra-office device, wherein the addition circuit adds the output of the encoding circuit to the output of the subtraction circuit multiplied by n and outputs a delay measurement result.