KR970009679B1 - Device for measuring phase difference between clocks - Google Patents

Abstract

An apparatus for measuring a phase difference between clock signals is disclosed. The apparatus comprises a phase difference detector(10) detecting a phase difference between two clocks to provide a clock phase difference signal corresponding to the phase difference; a phase difference measuring unit(20), responsive to the clock phase difference signal, for outputting a phase difference data corresponding to the ratio of the clock phase difference signal; a latching unit(30,40) for latching the first phase difference data and latching each phase difference data at each input period to output an instant phase difference data; a phase difference changing detector(50) for receiving the first phase difference data and the instant phase difference data to provide a phase difference changing data corresponding to the changing quantity between the first phase difference data and the instant phase difference data; and an interrupt generator(60), responsive to the phase difference changing data, for generating a phase difference measuring data corresponding to the measured phase difference between two clocks.

Description

Clock-to-clock phase difference meter

1 is a block diagram of a phase difference measuring device between clocks according to an exemplary embodiment of the present invention.

2 is an example of input / output timing of the phase difference detector 10 in the configuration of FIG.

3 is a detailed configuration diagram of the phase difference measuring instrument 20 in the configuration of FIG.

4 is a timing diagram showing a reference clock division value of 4.096 MHz for a data clock of 19.2 Kbps data rate.

5 is a state diagram showing a clock counting value and phase difference data (DCBA) according to each percentage of phase difference from the division value of FIG.

6 is a determination state of phase difference amount data determined by comparing initial phase difference data latched by the initial value latch unit 30 and instantaneous phase difference data latched by the instantaneous value latch unit 40 according to an embodiment of the present invention. Degree.

7 is a waveform diagram showing an example of a phase difference between two clocks generated from different clock sources.

FIG. 8 is a state diagram of phase difference measurement data determination of the interrupter generator 60 according to phase difference variation data input during configuration of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data communication systems forming a network, and more particularly to a phase difference measurer between generation outputs from different clock sources of a data communication system.

In general, in a data communication system forming a network, a transmitting side and a receiving side use data clocks generated by different clock sources, respectively, to perform data transmission and reception with each other. However, in the above-described data transmission / reception, a data transmission / reception error occurs when a phase difference between clocks does not occur precisely between two data clocks by using different clock sources.

That is, if the two clocks of the transmitting side (such as the main communication system of the network) and the receiving side (such as the terminal) are not synchronized correctly, the clock of the transmitting side may be faster or slower than the clock of the receiving side (such as the terminal). exist. At this time, when the clock of the receiver is fast, there is a problem in that the receiver takes both sides of the same data among the data sent from the transmitter. In addition, when the clock of the receiver is slow, an error may occur in which the receiver loses some of the data transmitted from the transmitter. Therefore, in order to eliminate data loss or double reception caused by the phase difference between two clocks generated from different clock sources, the phases between the two data clocks must be measured and compensated according to the measured values.

Accordingly, an object of the present invention is to provide a phase difference clock measurer for measuring a phase difference between two clocks generated from different clock sources in a data communication system forming a network.

According to an aspect of the present invention, a data communication system for forming a network includes a first and second clocks and a predetermined reference clock inputted from different clock sources, and are synchronized with the reference clock. And phase difference detection means for obtaining a phase difference between the second clocks and generating and outputting a clock phase difference signal corresponding to the phase difference, and receiving the clock phase difference signal and synchronizing with the reference clock to generate a phase difference signal based on the reference clock for one period of the clock phase difference signal. The counting value is calculated in the current period, and the phase difference data is fed back one cycle, and the counting value is replaced by one counting value. The counting value of the current period and the one-period counting value are compared to correspond to the rate of change of the clock phase difference signal. Phase difference measuring means for outputting phase difference data and the phase difference data sequentially A latch means for latching and outputting the first phase difference data and the phase difference data in each input period as instantaneous phase difference data, respectively, and receiving the first phase difference data and the instantaneous phase difference data, respectively, the first phase difference data and the instantaneous phase difference data; Phase difference amount detecting means for generating and outputting phase difference amount data corresponding to the phase difference amount of phase difference data, and interrupt generation means for receiving the phase difference amount data and generating and outputting phase difference measurement data corresponding to the measured phase difference between the two clocks. do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a phase difference measuring device between clocks according to an exemplary embodiment of the present invention, wherein the phase difference detector 10 includes first and second clocks R1 and R2 and predetermined reference clocks inputted from different clock sources. C4M) is input, and the phase difference between the two input clocks R1 and R2 is obtained in synchronization with the reference clock C4M and output as a clock phase difference signal R2-R1.

The phase difference measuring unit 20 receives the clock phase difference signals R2-R1, and counts one reference period of the clock phase difference signals R2-R1 in synchronization with the reference clock C4M to calculate the reference clock counting values Q0 to Q6. ) Is compared with the counting values (Q0 'to Q6') of the previous period, and the 4-bit phase difference data (DCBA) corresponding to the change in the phase difference signal is output.

The initial value latch unit 30 receives the phase difference data DCBA, and latches and outputs the phase difference data DCBA input as the first phase difference data after system initialization.

The instantaneous value latch unit 40 sequentially receives the phase difference data DCBA for each input period and latches it as instantaneous phase difference data.

The phase difference change detection unit 50 receives the first phase difference data latch output from the initial value latch unit 30 and the instantaneous phase difference data output from the instantaneous value latch unit 40 to correspond to the amount of change between the two input phase difference data. Outputs phase difference change data.

The interrupt generator 60 receives the phase difference change amount data, converts the phase difference measurement data D6 to D0, and generates and outputs an interrupt signal INT corresponding to the change of the phase difference.

2 is a timing diagram illustrating input and output timing of the phase difference detector 10 that receives two clocks R1 and R2 generated from two different clock sources and outputs the clock phase difference signals R2-R1.

FIG. 3 is a schematic diagram of the phase difference measuring unit 20 of FIG. 1, wherein the first counter 21 receives the clock phase difference signals R2-R1 and the reference clock C4M. The low state section is counted to the reference clock C4M using the clock phase difference signals R2-R1, and the counting values Q0 to Q6 are output.

The substitution comparator 22 receives the counting values Q0 to Q6, and the phase difference data D'C'B'A 'before one cycle according to the clock phase difference signals R2'-R1' input one cycle ago. Is replaced with the counting values Q0 'to Q6' one cycle before, and compared with the counting values Q0 to Q6 in the current period to output the comparison result signal OUT.

The second counter 23 receives the comparison result signal OUT as a count enable signal, hexadecimal counts in synchronization with the reference clock C4M, and sets the count value according to the current clock phase difference signal. Output to (DCBA).

4 is a timing diagram showing a reference clock division value of 4.096 MHz for a data clock of 19.2 Kbps. 4 is an example according to the recommendation of CCITT V.100, which is one of a data rate of 600bps × ²ⁿ (n = 0,1,2,3,4,5) during synchronous operation, and the first clock R1. The crystal of is 0.6 x [8 Kbps x 2 ⁿ (n = 0, 1, 2)]. Therefore, in this case, the measurement of the phase difference measures the phase difference for the cases of 19.2Kbps, 9600bps and 4800bps.

For example, using a 4.096 MHz reference clock (C4M) for a data clock of 19.2 Kbps.

Based on the above equation, the phase difference is measured by performing division of 213.333 on the data clock of 19.2 Kbps. That is, FIG. 4 shows the divided value and the timing, and is defined as the divided value of 213, 213, and 214 instead of the divided value of 213.333.

FIG. 5 is a state diagram showing a clock counting value and phase difference data DCBA corresponding to each percentage of phase difference from the division value of FIG. 4 described above.

6 is a state diagram of the phase difference change data determined by comparing the initial phase difference data latched by the initial value latch unit 30 and the instantaneous phase difference data latched by the instantaneous value latch unit 40.

7 is a waveform diagram illustrating a phase difference between two clocks generated from different clock sources.

FIG. 8 is a phase difference measurement data determination state diagram of the interrupt generator 60 according to the phase difference variation data input in FIG. 1, and FIG. 8A is a speed code determination state, and FIG. 8B is a phase difference code determination state.

Hereinafter, features and operations according to an exemplary embodiment of the present invention will be described in detail with reference to the above-described configuration of FIGS. 1 and 3 and the state diagrams and timing diagrams of FIGS.

First, in an embodiment feature and operation of the present invention to be described below, as shown in the brief description of FIG. 4, a basic clock (C4M) of 4.096 MHz is used as an example, and a data clock (R1, of 19.2 Kbps) is used. R2) is used.

First, when the data clocks R1 and R2 having a transmission rate of 19.2 Kbps are input from different clock sources, the phase difference detector 10 is synchronized with a 4.096 MHz reference clock C4M input from a predetermined reference clock source (not shown). The phase difference between the two data clocks R1 and R2 is detected to output the clock phase difference signals 9R2-R1. At this time, the clock out-of-clock difference signal output state of the phase difference detector 10 with respect to the two data clocks (R1, R2) can be shown as an example of FIG.

Thereafter, the first counter 21 in the phase difference measuring unit 20 receives the clock phase difference signals R2-R1 and synchronizes the low state section of the clock phase difference signals R2-R1 in synchronization with the reference clock C4M. Binary counting outputs the counting value. At this time, it is determined how many bits of data are to be counted based on the number of binary counters constituting the first counter 21. The configuration of the first counter 21 described above may be increased or decreased according to the speeds of the input clocks R1 and R2 and the reference clock C4M. That is, in one embodiment of the present invention, since the maximum counting value counting the low state section to the reference clock C4M does not exceed 107, the configuration of the first counter 21 for performing the counting operation of 107 at maximum is It is possible with seven binary counters connected in series. Accordingly, the counting values Q0 to Q6 are represented by 7-bit data types.

The substitution comparator 22 receives the counting values Q0 to Q6 and also outputs the phase difference from the second counter 23 in response to the clock phase difference signals R2 'to R1' input one cycle before. The data D'C'B'A 'is fed back. Subsequently, the replacement comparator 22 converts the counting values Q0 'to Q6' of the clock phase difference signal one cycle before from the phase difference data D'C'B'A 'one cycle before to count the current clock phase difference signal. Q0 to Q6). At this time, the substitution configuration of the substitution comparator 22 with the counting value Q0 'to Q6' before one cycle can be configured by the following equation.

That is, according to the calculation configuration of D'C'B'A 'as shown in the following equation where Q0'-Q6' satisfies the output of '1',

It may be substituted by.

Subsequently, the substitution comparator 22 outputs the counting values Q0 'to Q6' one cycle before as a comparison result signal OUT.

The second counter 23 receives the comparison result signal OUT as a count enable signal and counts hexadecimal in synchronization with the reference clock C4M, and outputs the counting value as 4 bits of phase difference data DCBA. do. In this case, the phase difference data DCBA represents a displacement value with respect to the phase difference in each period, and is represented by data of 0-9 representing 0-5% as shown in FIG. Therefore, referring to FIG. 5 described above, if the phase difference data DCBA, which is enabled in the comparison result signal OUT and hexadecimal counted as 0011, is 0011, the current phase shift with respect to the phase difference before one cycle is 20%. Indicates.

The initial value latch unit 30 receives only the phase difference data DCBA input for the first time and latches the first phase difference data. The instantaneous value latch unit 40 receives the phase difference data DCBA sequentially input and latches the instantaneous phase difference data.

When the system is powered on, the initial value latch unit 30 latches the phase difference data DCBA input after the clocks of R1 and R2 start. At this time, the initial value latch unit 30 latches the phase difference data DCBA determined by a plurality of values among the first three phase difference data DCBA that are subsequently input. That is, the initial value latch unit 30 latches the same initial phase difference data when two or more of three consecutive phase difference data DCBAs are the same, and in the case of different values, the next three phase differences do not latch. Retrieve the data (BABA) again and latch out. The above operation is to prevent an error in an unexpected case due to noise of R1 and R2. At this time, the first phase difference data latched at the first latches an actual value according to the phase difference, and performs a relative comparison with the next phase difference data to determine the instantaneous change of phase, regardless of which value is latched.

The phase difference change detection unit 50 receives the first phase difference data latch output from the initial value latch unit 30 and the instantaneous phase difference data output from the instantaneous value latch unit 40, and compares the two input phase difference data. The phase difference change data determined according to the crystal state of 6 degrees is output through the corresponding output terminals CK00 to CK80.

Hereinafter, the operation of the phase difference detection unit 50 will be briefly described with reference to the determination state of FIG. 6.

As an example, in FIG. 6, when the first phase difference data (FLV) is 7 and the instantaneous phase difference data input in the current period is 8, the instantaneous value is increased because the instantaneous value is increased from the initial value. If the instantaneous value is 10, ± 15% (± 20%), odd 6, ± 35% (± 40%), even 2 15% ( 20%) and 0% for even 7th. Then, whether the speed of R2 is slower or faster than R1 based on the state of R2 using the up state determined in the above-described operation is determined according to the speed determination state diagram of FIG. For example, referring to the waveform diagram of FIG. 7, when the up state is determined as shown in A, the clock relationship between R1 and R2 is a case where R2 is slow, and when it is a down state, E2 is faster. In case of B, R2 is fast in the up state and R2 is slow in the down state. For example, the phase difference determination amount When the ratio is 35% and R2 is faster than R1, the phase difference detection unit 50 outputs phase difference change data through the CK40 output terminal.

The interrupt generator 60 receives the phase difference change data input through the phase difference change detector 50 and outputs the phase difference change data as phase difference measurement data and outputs an interrupt signal INT indicating that there is a phase difference change in the input clock. In the conversion to the phase difference measurement data, when the phase difference amount data is inputted through the CK40 output terminal of the phase difference amount detecting unit 50, the phase difference amount is recognized as +40, and R2 is faster than R1 according to the crystal state diagram of FIG. Since the data value of D6D5 is 01 and the phase difference determination amount is 40, the final output of the phase difference measurement data is 1101110 (D0 to D6).

Therefore, as described above, the present invention can accurately measure the phase difference of the data clocks generated from different clock sources, and thus, there is an advantage in that the data clock compensation of the transmission / reception side can be accurately achieved during data transmission of the data communication system.

In addition, since the present invention is implemented with a digital logic gate, it is easy to design a single chip.

Claims (6)

In a data communication system forming a network; Receiving a first reference clock and a predetermined reference clock input from different clock sources, obtaining a phase difference between the first clock and the second clock in synchronization with the reference clock, and generating and outputting a clock phase difference signal corresponding to the phase difference Phase difference detection means; Receiving the clock phase difference signal and obtaining a counting value in the current period by the reference clock for one period of the clock phase difference signal in synchronization with the reference clock, receiving the phase difference data one cycle before, and replacing it with a counting value before one cycle, Phase difference measuring means for comparing the counting value of the current period and the counting value before one period and outputting phase difference data corresponding to the rate of change of the clock phase difference signal; Latch means for sequentially receiving the phase difference data and latching the first phase difference data first inputted and the phase difference data in each input period as instantaneous phase difference data; Phase difference change detection means for receiving the first phase difference data and the instantaneous phase difference data, respectively, and generating and outputting phase difference amount data corresponding to the phase difference change amount of the initial phase difference data and the instantaneous phase difference data; And an interrupt generator which receives the phase difference change amount data and generates and outputs phase difference measurement data corresponding to the measured phase difference between the two clocks. The method of claim 1, wherein the phase difference measuring means; A division means for receiving the clock phase difference signal and the reference clock, dividing the clock phase difference signal into the reference clock and outputting the division ratio, and receiving the division ratio, and receiving feedback input of phase difference data one cycle before Substitution comparison means for substituting the frequency division ratio of the mechanical clock phase difference signal by one cycle, calculating the operation ratio of the division ratio and the division ratio before one cycle, and outputting a comparison result signal, and receiving the comparison result signal as a count enable signal. And counting means for counting in synchronization with the reference clock and outputting the counting value as the phase difference data according to a current clock phase difference signal. 3. The apparatus of claim 2, wherein the counting means is a hexadecimal counter. The method of claim 1, wherein the latch means; An initial value latch means for receiving the phase difference data sequentially inputted from the initial stage, and latching and outputting phase difference data representing at least two or more identical values among the phase difference data as initial phase difference data; And an instantaneous value latching means for sequentially receiving the phase difference data and latching them as instantaneous phase difference data, respectively. In a data communication system forming a network; Receiving a first reference clock and a predetermined reference clock input from different clock sources, obtaining a phase difference between the first clock and the second clock in synchronization with the reference clock, and generating and outputting a clock phase difference signal corresponding to the phase difference Phase difference detection means; A division means for receiving the clock phase difference signal and the reference clock, dividing the clock phase difference signal into the reference clock and outputting a division ratio thereof; The division ratio is input, and the phase difference data is inputted one cycle before, and the cycle ratio is divided by one cycle before the clock phase difference signal, and the comparison ratio is divided by one cycle before the cycle. Substitution comparison means; Counting means for receiving the comparison result signal as a count enable signal, counting in synchronization with the reference clock, and outputting the counted value as the phase difference data according to a current clock phase difference signal; An initial value latch means for receiving the phase difference data sequentially inputted from the initial stage, and latching and outputting phase difference data representing at least two or more identical values among the phase difference data as initial phase difference data; Instantaneous value latching means for sequentially receiving the phase difference data for each input clock period and latching them as instantaneous phase difference data; Phase difference change detection means for receiving the first phase difference data and the instantaneous phase difference data, respectively, and generating and outputting phase difference amount data corresponding to the amount of phase difference change between the first phase difference data and the instantaneous phase difference data; And an interrupt generator which receives the phase difference change amount data and generates and outputs phase difference measurement data corresponding to the measured phase difference between the two clocks. 6. The phase difference measuring device of claim 5, wherein the counting means is a hexadecimal counter.