KR100202946B1 - Apparatus and method for transmitting a synchronization by using a state machine in a synchronous residual time stamp - Google Patents

Abstract

The present invention, formed on the basis of the network clock frequencies (f _n) n division reference clock frequency (f _nx) formed on the basis of the service clock frequency (f _s) in the synchronous transfer apparatus of a synchronous residual time stamp (SRTS) n A synchronous residual time stamp (SRTS) synchronization using a state machine in which a remaining time stamp (RTS) is outputted by the remaining time stamp load signal (RTS_LD) formed from the division service clock frequency (SRTS_cycle) A third counter (10) for outputting an n-division service clock frequency (SRTS_cycle) based on a service clock frequency (f _s ); A fourth counter 12 for outputting an n-division reference clock frequency f _nx based on the network clock frequency f _n ; The remaining time stamp load signal RTS_LD is output based on the n-division service clock frequency SRTS_cycle from the third counter 10 and the n-division reference clock frequency f _nx from the fourth counter 12 A state machine 14; A P bit counter (18) for outputting time data (C _T ) based on the reference clock frequency (f _nx ); And an RTS register 16 for outputting a synchronous remaining time stamp (SRTS) including the time data (C _T ) of the P bit counter by the remaining time stamp load signal (RTS_LD).

Description

Synchronous transfer of synchronous residual time stamp (SRTS) using a state machine and a transfer method thereof

The present invention is based on a network clock frequencies (f _n) in the synchronous transfer apparatus of a synchronous residual time stamp (SRTS) synchronization with the transfer unit, and relates to the transmission method, in particular a synchronous residual time stamp (SRTS) for using a state machine The remaining time stamp RTS is generated by the remaining time stamp load signal RTS_LD formed from the n divided service clock frequency SRTS_cycle formed based on the n divided frequency clock f _nx and the service clock frequency f _s formed, (SRTS) using a state machine capable of transmitting stable synchronization information, and a transmission method therefor.

Generally, one of the important functions of AAL for real-time service is clock recovery. In case of ATM based network, ATM cell arriving at receiving side is not periodic even in case of CBR (constant bit rate) service. .

If there is no common reference clock in the ATM network, the only information on the transmission side clock frequency that can be obtained from the receiving side is only the average rate of the cells measured over a long period of time. In such a case, The clock can be restored.

In addition, when there is a reference clock, for example, it is possible to synchronize the transmission and service rate with the reference clock of the network when the clock of each node can be adjusted to a single reference clock. In this case, a synchronization pattern or a time stamp can be used for synchronization information transmission.

On the other hand, a cell propagated through the ATM network generates a random delay due to a queue such as a statistical multiplexer and a cross-connector, and this delay occurs at first in a periodic manner, Statistical multiplexing, etc., is received at the receiving side as a statistical cell flow, which results in a change in the initial time structure of the cell.

This phenomenon is referred to as cell delay variation (CDV) or cell jitter, which affects the peak cell rate, and the cell delay displacement is the maximum The clumping is defined as a dispersion where the instantaneous maximum cell rate is less than the cell occurrence rate and the average cell rate of the receiving end is larger than the average cell rate of the receiving end, and a dispersion where the continuous cell arrival interval is larger than the maximum cell occurrence rate, .

1 is a block diagram illustrating a synchronous transmission apparatus of a general synchronous residual time stamp (SRTS), wherein the transmission apparatus includes first and second counters 50 and 52, a pulse condition determining unit 54, A P bit counter 56, and a latch unit 58.

The first counter 50 divides the service clock frequency f _s by n and outputs the n divided service clock Sp and the second counter 52 divides the network clock frequency f _n by n And outputs the n-divided reference clock frequency f _nx .

The pulse train state determination unit 54 determines the pulse train state based on the n divided service clock frequency Sp from the first counter 50 and the n divided reference clock frequency f _nx from the second counter 52, And outputs a time stamp load signal Sp1. The P-bit counter 56 is driven by the n-division reference clock frequency f _nx , and the output value is sampled every RTS period. The RTS period is output from the pulse-string-state determining unit 54 Sp1).

Therefore, the latch unit 58 outputs the remaining time stamp (RTS) based on the output clock from the P bit counter 56 and the output clock Sp1 from the pulse string state determination unit 54, The transmission is performed.

On the other hand, one of the important functions of the AAL for real-time service is clock recovery. In the ATM-based network, even in the case of the CBR service, the ATM cells arriving at the receiving side are not periodic, . Therefore, the ITU-T standardizes the synchronous residual stamp (SRTS) method as a method of restoring the source clock, and it can eliminate the cell delay displacement by using it.

The SRTS method uses the same reference clock frequency as that of the transmitting terminal to transmit the difference between the service frequency and the frequency at which the transmitting terminal has obtained the network frequency. In the receiving terminal, the difference between the transmitted frequency and the network frequency is used Thereby restoring the clock on the transmission side.

FIG. 2 is a diagram showing a pulse condition state resolver shown in FIG. 1, wherein the determination unit 54 is composed of a plurality of inverter elements, an OR gate, and an AND gate. The pulse train conditions configured by the hardware, such as determiner 54, and outputs the remaining time stamp load signal (Sp1) on the basis of the service clock frequency (Sp) and the reference clock frequency (f _nx).

In this way, the pulse condition determination section, but can prevent the cell delay displacement, or cell jitter, by forming a predetermined number of drive elements and the AND gates in order to prevent the cell delay displacement, or cell jitter, the reference clock frequency (f _nx) There has been a problem in that the configuration must be changed according to the variation.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide an apparatus and method for synchronous transmission of a synchronous residual time stamp (SRTS) in which an n-division reference clock frequency f _nx , which is formed based on a network clock frequency f _n , (RTS) is output by the remaining time stamp load signal (RTS_LD) formed from the n-division service clock frequency (SRTS_cycle) formed based on the n-division service clock frequency (f _s ) so that stable synchronization information can be transmitted And a synchronous transmission apparatus of synchronous residual time stamp (SRTS) and a transmission method thereof.

According to another aspect of the present invention, there is provided a synchronous transmission method for synchronous remaining time stamp, comprising: a third counter for outputting an n-division service clock frequency based on a service clock frequency; A fourth counter for outputting an n division reference clock frequency based on the network clock frequency; A state machine for outputting a remaining time stamp load signal based on an n-division service clock frequency from the third counter and an n-division reference clock frequency from the fourth counter; A P bit counter for outputting time data based on the reference clock frequency; And an RTS register for outputting a synchronous remaining time stamp including time data of the P bit counter by the remaining time stamp load signal.

The present invention configured as described above is characterized in that in the synchronous transmission device of the synchronous remaining time stamp, an n-division reference clock frequency formed based on the network clock frequency and a remaining time stamp load formed from an n-division service clock frequency formed based on the service clock frequency The remaining time stamp is outputted by the signal, so that the synchronization information can be transmitted stably.

1 is a block diagram showing a synchronous transmission device of a general synchronous residual time stamp (SRTS)

FIG. 2 shows a pulse condition resolver shown in FIG. 1,

3 is a block diagram showing a synchronous transmission apparatus of a synchronous residual time stamp (SRTS) using a state machine according to the present invention;

4 is a diagram illustrating the configuration of a residual time stamp (RTS) value for general transmit side clock reproduction,

FIG. 5 is a timing chart showing operation timings of a synchronous transmission apparatus of a synchronous residual time stamp (SRTS) using a state machine according to the present invention;

FIG. 6 is a flowchart illustrating an operation of a synchronous transfer method of synchronous residual time stamp (SRTS) using a state machine according to the present invention.

Description of the Related Art [0002]

10, 12: third and fourth counters, 14: state machine,

16: RTS register, 18: RTS register.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

On the other hand, there are two methods of synchronous information transmission for the CBR service: synchronous encoding technique (SEET; synchronous encoding technique) and time stamping technique. All of these schemes are applied in situations where there is a common reference clock within the network.

The basic concept of the SEET method is to generate a reference clock from a common clock in the network that can be obtained simultaneously on the transmitting side and the receiving side and use the reference clock as a reference for transmitting these synchronous information. First, the transmission side clock, which is asynchronous with the network, is compared with the generated reference clock, and when the frequency difference information is transmitted to the reception side, the reception side restores the transmission side clock from the frequency difference information and the reference clock.

The SRTS method uses a residual time stamp (RTS) to measure and convey information about the frequency difference between the reference clock and the service clock generated from the network clock. In the SRTS, it is assumed that a common clock derived from the network can be obtained from both the transmitting side and the receiving side, and this SRTS method can satisfy the jitter requirements specified in ITU-T Recommendations G.823 and G.824 .

On the other hand, SRTS method, using two frequencies, such as the network clock frequency of the reference clock frequency (f _nx) and the service clock frequency (f _s) according to the service created from the (f _n) and said reference clock frequency (f _nx) is only equal to or less than twice of the service clock frequency (f _s) greater than or equal to the service at the same time the clock frequency (f _s).

That is, f _s ≤ f _ns ≤ 2f _s , and the frequency of the reference clock derived from the network clock for the integer k as the following expression always satisfies this condition.

[Equation 1]

The basic idea of the SRTS method is to transfer the difference information between the two frequencies f _nx and f _s to the receiving side and since the reference clock frequency f _nx can be obtained at the receiving side, The clock frequency (f _s ) can be determined. Therefore, the RTS period is defined as the time for measuring the frequency difference, which is defined as T seconds corresponding to N times the service clock frequency (f _s ).

If M represents the number of reference clocks during the RTS period,

&Quot; (2) "

to be. Therefore, M is not an integer in most cases, where Mq is an integer part of M, Mq is composed of a regular part and a remaining part which do not actually change, and a regular part is a normal part of the reference clock frequency (f _nx ) And the receiver knows this.

The remaining part has information on the frequency difference and the quantization effect as an unknown part on the receiving side, and the remaining part is information to be transmitted to the receiving side as synchronization information. Here, the remaining portion of Mq is transmitted through the RTS of the P-bit, the size P of the RTS is able to determine when to consider the tolerance of the service clock frequency (f _s).

On the other hand, when the tolerance of the service clock frequency f _s is x, it is found that the tolerance y of the reference clock frequency f _nx is given as follows.

&Quot; (3) "

In order to accommodate twice the maximum value of the frequency variation due to this tolerance, the size P of the RTS is set to a value that satisfies the following relation.

&Quot; (4) "

2 ^P > 2 [y]

Here, [y] represents a minimum integer equal to or larger than y.

2, C _T in the figure is a P-bit counter driven by a reference clock frequency f _nx , and the value of this counter C _T is equal to every RTS Is sampled periodically, and this RTS period is generated by the first counter 10 through a division N operation.

Therefore, if the remaining part of RTS and Mq is known, the value of Mq can be completely determined at the receiving side, and Mq is finally used to generate the reference synchronizing signal for the PLL for restoring the service clock. For example, for practical applications in a synchronized ATM network, the network clock frequency f _n is 155.52 MHz, N is 3008, which corresponds to the number of bits of eight SAR-PDUs, and the tolerance x is 200 × 10 ^-6 , and the size of RTS can be designated by 4 bits. Then, a 4-bit RTS is transmitted in series using 4 CSI bits in 8 consecutive SAR-PDUs.

3 is a block diagram illustrating a synchronous transmission apparatus of a synchronous residual time stamp (SRTS) using a state machine according to the present invention, in which the synchronous transmission apparatus includes third and fourth counters 10 and 12, a state machine 14 ), An RTS register 16, and a P-bit counter 18.

The third counter 10 outputs an n divided service clock frequency SRTS_cycle based on the service clock frequency f _s and the fourth counter 12 outputs n divided clocks based on the network clock frequency f _n , And outputs the frequency division reference clock frequency f _nx .

The state machine 14 may also be configured to compare the n frequency division service clock frequency SRTS_cycle from the third counter 10 and the n frequency division reference clock frequency f _nx from the fourth counter 12 And outputs the remaining time stamp load signal RTS_LD to the P bit counter 18. The P bit counter 18 outputs the time data C _T based on the reference clock frequency f _nx .

If the service clock frequency SRTS_cycle from the third counter 10 is a value of 1 and the reference clock frequency f _nx from the fourth counter 12 is a rising time, And outputs the stamp load signal RTS_LD as a value of 1.

The RTS register 16 outputs a synchronous remaining time stamp (SRTS) including the time data (C _T ) of the P bit counter 18 by the remaining time stamp load signal (RTS_LD). The P bit counter 18 is continuously driven by the network drive clock f _nx and the output of the P bit counter 18 is sampled every T seconds (e.g., N source clock cycles).

Further, the sampling pulse (SRTS_cycle), for example, n services division clock frequency is divided by the service clock frequency is N source clock (f _s) from the third counter 10 is to be calculated. Therefore, the sampling output of the P-bit counter 18 becomes complicated due to the asynchronous state of the service clock frequency f _s and the network drive clock f _nx .

Because of this, if you do not do a lot of circumstance, the state machine will produce the wrong result. The asynchronous clock is handled by designing an asynchronous FIFO buffer.

FIG. 4 is a diagram showing a configuration of a residual time stamp (RTS) value for a general transmission side clock reproduction. First, as a clock frequency recovery method, application of a synchronous residual time stamp (SRTS) For example, by transmitting the difference between the clock frequency at which the service actually operates and the clock frequency of the network, for example, the RTS value from the transmitting side to the receiving side.

The sequence number value SN is transmitted by an odd number of Convergence Sublayer Indication (CSI) bits, and the remaining time stamp (RTS) value is composed of 4 bits.

FIG. 5 is a timing chart illustrating operation timings of a synchronous transmission apparatus of a synchronous residual time stamp (SRTS) using a state machine according to the present invention, wherein f _s is a service clock frequency and f _nx is a network clock frequency f _n And SRTS_cycle is a sampling pulse formed based on the service clock frequency f _s .

RTS_LD is a remaining time stamp load signal formed based on the sampling pulse SRTS_cycle and the reference clock frequency f _nx and C _T is an output of the P bit counter operating in accordance with the reference clock frequency f _nx And RTS is the remaining time stamp (RTS) including the time data (C _T ) of the P bit counter by the remaining time stamp load signal (RTS_LD).

FIG. 6 is a flowchart illustrating an operation of a synchronous residual time stamp (SRTS) transmission method using a state machine according to the present invention. In the synchronous transmission method of a synchronous residual time stamp (SRTS) Is formed from a n-division reference clock frequency f _nx formed based on the network clock frequency f _n and a remaining time stamp load signal (n n) formed from an n-division service clock frequency SRTS_cycle formed based on the service clock frequency f _s (SRTS) state before the RTS_LD is output, that is, the 0th state.

The second step S2 determines whether or not the remaining time stamp load signal RTS_LD is a value of 1. If the remaining time stamp load signal RTS_LD is not 1, it determines that the state of the synchronous remaining time stamp SRTS is the 0th state (SRTS), i.e., the first state, if the remaining time stamp load signal RTS_LD is a value of 1 as a result of the determination of the second step S2 do

The fourth step S4 shows the state of the synchronous remaining time stamp SRTS including the time data C _T of the P bit counter by the remaining time stamp load signal RTS_LD, that is, the second state . In the fifth step S5, it is determined whether or not the service clock frequency SRTS_cycle is a value of 0. If the value is not 0, the second state of the fourth step S4 is maintained. Value, the 0th state of the first step S1 is maintained from the next clock of the reference clock frequency f _nx . The time data (C _T ) from the P-bit counter (18) is output to the RTS register (16) while the remaining time stamp load signal (RTS_LD) is a value of 1.

It should be noted that the drawings are not intended to limit the technical scope of the present invention to the embodiments shown in the drawings in order to facilitate understanding of the present invention.

As described above, according to the present invention, in the synchronous transmission device of the synchronous residual time stamp, the n-division reference clock frequency formed based on the network clock frequency and the remaining time stamp formed from the n-division service clock frequency formed based on the service clock frequency The remaining time stamp is outputted by the load signal, so that the synchronization information can be transmitted stably.

Claims (4)

A synchronous transfer method of synchronous residual time stamp (SRTS), comprising: a third counter (10) for outputting an n division service clock frequency (SRTS_cycle) based on a service clock frequency (f _s ); A fourth counter 12 for outputting an n-division reference clock frequency f _nx based on the network clock frequency f _n ; The remaining time stamp load signal RTS_LD is output based on the n-division service clock frequency SRTS_cycle from the third counter 10 and the n-division reference clock frequency f _nx from the fourth counter 12 A state machine 14; A P bit counter (18) for outputting time data (C _T ) based on the reference clock frequency (f _nx ); And an RTS register (16) for outputting a synchronous remaining time stamp (SRTS) including the time data (C _T ) of the P bit counter by the remaining time stamp load signal (RTS_LD) A synchronous transfer device of a Residual Time Stamp (SRTS). According to claim 1, wherein said state machine (14) is a value of the service clock frequency (SRTS_cycle) from the third counter 10 is 1, the reference clock frequency (f _nx) from the fourth counter (12) And outputs the remaining time stamp load signal (RTS_LD) as a value of 1 when the rising time stamp signal is a rising time. In the synchronous transfer method of the synchronous residual time stamp (SRTS), network clock frequencies (f _n) the n frequency division reference clock frequency formed of the base (f _nx) and the service clock frequency n frequency divider service clock is formed based on the (f _s) (S1) indicating the state of the synchronous remaining time stamp (SRTS), that is, the 0th state, before the remaining time stamp load signal (RTS_LD) formed from the frequency (SRTS_cycle) is outputted; A second step (S2) of determining whether the remaining time stamp load signal (RTS_LD) is a value of 1 and determining that the state of the synchronous remaining time stamp (SRTS) is a 0 state if the value is not 1; A third step (S3) indicating a state of the synchronous remaining time stamp (SRTS), that is, a first state when the remaining time stamp load signal (RTS_LD) is a value of 1 as a result of the second step (S2); A fourth step S4 of indicating the state of the synchronous remaining time stamp SRTS including the time data C _T of the P bit counter 18 by the remaining time stamp load signal RTS_LD, ; The second state of the fourth step S4 is maintained if the service clock frequency SRTS_cycle is not a value of 0 and the reference clock frequency f _nx is maintained when the value is 0, And a fifth step (S5) of maintaining the 0th state of the first step (S1) from the next clock of the synchronous remaining time stamp (SRTS) using the state machine. 4. The method of claim 3, wherein the time data (C _T ) from the P bit counter (18) is output to the RTS register (16) while the remaining time stamp load signal (RTS_LD) A synchronous transmission method of synchronous residual time stamp (SRTS) using.