JP2559237Y2 - Serial data sampling signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to serial data sampling for sampling a serial data signal at a constant interval in serial transmission and generating a sampling signal for giving a timing for converting to a parallel signal. The present invention relates to a signal generation circuit, and more particularly to a circuit capable of correcting a transfer rate on a receiving side in accordance with a transfer rate of serial data on a transmitting side and generating a sampling signal based on the corrected transfer rate.

[Conventional technology]

When a large amount of digital information is transmitted between a computer device and its input / output device, and between computer devices, a serial transmission system is generally used which requires a small number of signal lines.

The serial transmission method is classified into two types, a synchronous type and an asynchronous type, according to a method of obtaining a sampling timing when serial data is generally converted into parallel data inside a device.

In synchronous serial transmission, a transmitting side sends out a synchronizing signal giving sampling timing in parallel with a serial data signal, and a receiving side samples serial data based on the synchronizing signal and converts it into parallel data.

In asynchronous serial transmission, in a method currently generally used, a start bit and a stop bit having a predetermined length are placed before and after a predetermined interval, for example, every 8 bits, and synchronization is performed for each start bit. Thus, the sampling timing is obtained using 8 bits as one unit.

[Problems to be solved by the invention]

As described above, in the synchronous serial transmission, the number of signals increases because a synchronous signal must be sent together with the serial data signal, and this is crucial especially in the case of transmission to a remote place via a telephone line. It is a disadvantageous condition.

On the other hand, in the case of the asynchronous type, since the bit rate is set by a separate circuit on the transmission side and the reception side, a slight shift occurs between the two frequencies due to an error in the setting of circuit constants or a change in environment such as temperature. . Therefore, if the number of bits of information between the start bit and the stop bit is increased, a timing shift due to a slight frequency shift is accumulated, and erroneous reading occurs and communication becomes impossible. Therefore, the number of bits of information between the start bit and the stop bit cannot be increased, in other words, the ratio of bits other than the information to be transmitted cannot be reduced. And the transfer time for transferring a certain amount of information is prolonged.

Accordingly, an object of the present invention is to provide a serial data sampling signal generation circuit for generating a sampling signal for giving an appropriate sampling timing in order to overcome the above-mentioned drawbacks in asynchronous serial transmission, and in particular, to provide a transmission side signal generation circuit. It is an object of the present invention to provide a serial data sampling signal generation circuit that can automatically correct the transfer speed on the receiving side according to the data transfer speed.

[Means for solving the problem]

The serial data sampling signal generating device of the present invention is a serial data sampling signal generating device for generating a sampling signal for sampling a serial data signal starting from a predetermined number of start bits, the falling edge of the serial data signal. And a flip-flop means which is reset by the rising edge of the serial data signal, a measuring period determining means which determines a period for measuring the pulse width of the start bit and outputs a measurement enable signal, Pulse width measurement means for measuring a pulse width; and a gate for outputting a measurement signal to the pulse width measurement means while the flip-flop means is in a set state and the measurement period determination means is outputting a measurement permission signal. Means and the star measured by the pulse width measuring means Wherein the pulse width measurement results of the bit and a pulse generating means for generating a sampling signal having a period and a phase corresponding to the bits constituting the start bit.

[Action]

FIG. 2 shows an example of a serial data signal in asynchronous communication. Before the serial data, there is a start bit whose width is equal to the width of each data bit or an integer multiple of it.The time from the fall to the rise is measured, and the frequency corresponding to that time is measured. As a signal, a sampling signal that is accurately cycled with the bit width of the subsequent data signal is formed.

〔Example〕

FIG. 1 is a block diagram showing the principle of the present invention. In the figure,
The serial data sampling signal generating circuit according to the present invention is a serial data sampling signal generating device for generating a sampling signal for sampling a serial data signal starting from a predetermined number of start bits, and a falling edge of the serial data signal. And a flip-flop means 10 which is reset by the rise of the serial data signal, a measurement period determining means 16 which determines a period in which the pulse width of the start bit is to be measured and outputs a measurement enable signal, A pulse width measuring means 18 for measuring a pulse width, the flip-flop means 10 being in a set state, and a measuring period determining means
A gate means 20 for outputting a measurement signal to the pulse width measurement means while the 16 is outputting a measurement permission signal, and a period corresponding to the pulse width measurement value of the start bit measured by the pulse width measurement means 18 Pulse generating means 22 for generating a sampling signal.

FIG. 3 shows an embodiment of the serial data sampling signal generator according to the present invention.

In this embodiment, the flip-flop means 10 shown in FIG.
Is a one-shot multivibrator (hereinafter abbreviated as one-shot) 101 which receives a serial data signal and outputs a pulse having a time constant determined by a resistor R1 and a capacitor C1 at its falling edge. At the rise, a one-shot 102 that outputs a pulse with a time constant determined by the resistor R2 and the capacitor C2, and the output of the one-shot 101
It is realized by a circuit composed of a flip-flop 103 whose input is connected so as to be reset by the output of 2. 161
Represents a computer system that receives and uses a serial data signal, and includes a known central processing unit, an input / output device, a storage device, and a part of the software and an input / output unit described in detail later. A part implements the measurement period determining means 16 of FIG. The gate means (20) in FIG. 1 is realized by an AND gate 201 to which the output of the flip-flop 103, the 10 MHz clock from the computer system 161 and the measurement permission signal are input. counter
181 counts pulses output from the AND gate 201, and a digital-analog (D / A) converter 221 outputs a voltage corresponding to the counter output of the counter 181.
Both constitute pulse width measuring means in FIG. The voltage-frequency (V / F) converter 222 outputs a square pulse at a frequency proportional to the output voltage of the D / A converter 221 and constitutes the pulse generating means 22 shown in FIG.

FIG. 4 is a flowchart showing the processing of a part of the software in the computer system 161 for realizing the measurement period determining means 16 of FIG. First, when acceptance of serial data becomes possible, a state of measurement permission is output (step a), and when the end of the start bit is detected (step b), a state of measurement non-permission is output.
After that, the process shifts to a process for analyzing the input serial data signal, but this is not within the scope of the present invention, and a description thereof will be omitted.

Returning to FIG. 3, in parallel with the transmission of the above-described measurement permission signal from the computer system 161 to the AND gate 201, the fall S ₁ of the start bit (FIG. 2) falls in the one-shot 101. Is detected according to
A square pulse having a time constant determined by the resistor R1 and the capacitor C1 is output. This pulse sets the output of flip-flop 103. Then, the rising of the start bit S ₂
Is detected by the rise detection in the one-shot 102, a rectangular pulse having a time constant determined by the resistor R2 and the capacitor C2 is output, and the flip-flop 103 is reset. Since the AND gate 201 and the previously described output from the output and the computer system 101 of the flip-flop 103 measurement enabling signal and 10MHz clock is input, the falling edge S ₁ of the start bit S to the output rise A 10 MHz clock is output only during the period up to S ₂ (FIG. 2). This is counted by a counter 181, an analog voltage corresponding to the count value is output from the D / A converter 221, a square pulse having a frequency proportional to the voltage value is output from the V / F converter 222, and a computer Introduced into system 161.

One shots 101 and 102 are flip-flops 10
Although this is for ensuring the setting and resetting of 3, the configuration is not always necessary, and the flip-flop may be directly set and reset at the falling and rising edges of the serial data signal.

[Effect of the invention]

As described above, according to the present invention, a sampling signal accurately synchronized with the actual bit rate of the received serial data signal can be obtained, so that the bit length per unit can be increased, and the efficiency can be increased. Good asynchronous serial transmission becomes possible.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a principle configuration of a serial data sampling signal generator according to the present invention, FIG. 2 is a diagram showing an example of a serial data signal in asynchronous communication, and FIG. FIG. 4 is an example of a circuit diagram of a serial data sampling signal generator, and FIG. 4 is a flowchart showing a process of determining a measurement period. 101, 102 One-shot multivibrator 103 Flip-flop 181 Counter 201 AND gate 221 D / A converter 222 V / F converter

 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-45255 (JP, A) JP-A-63-50133 (JP, A) JP-A-61-169956 (JP, A)

Claims (1)

(57) [Scope of request for utility model registration] 1. A serial data sampling signal generator for generating a sampling signal for sampling a serial data signal starting from a start bit having a predetermined number of bits, wherein the serial data sampling signal generator is set at a falling edge of the serial data signal, and Flip-flop means reset by the rising edge of the data signal; measuring period determining means for determining a period for measuring the pulse width of the start bit and outputting a measurement enable signal; and a pulse for measuring the pulse width of the start bit. Width measurement means; gate means for outputting a measurement signal to the pulse width measurement means while the flip-flop means is in a set state and the measurement period determination means outputting a measurement permission signal; The start bit is measured from the pulse width measurement result of the start bit measured by the measuring means. Serial data sampling signal generator apparatus characterized by having a pulse generating means for generating a sampling signal having a period and a phase corresponding to the bits constituting the bit.