JP3451691B2 - Serial data transmission circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides parallel data of a fixed length with arbitrary transmission timing specified for each.
The present invention relates to a serial data transmission circuit that converts to serial data and outputs at a specified timing.

[0002]

2. Description of the Related Art A serial data transmission method that reads transmission data and transmission timing of the data as a pair of parallel data, converts the transmission data into serial data at a designated timing, and outputs the serial data is, for example, MIDI.
(Musical Instrument Digital Interface) Frequently used for data transmission. In this type of data transmission method, it is important to accurately realize the transmission interval as well as the content of the transmission data.
Conventionally, software is used to accurately manage the transmission interval and input / output data.

[0003]

However, in the conventional method of managing the transmission interval by software, there is a problem that the interrupt processing for measuring the transmission interval increases the load on the CPU. Also,
In the conventional method, even if the CPU accurately manages the transmission interval, the delay time generated in the processing on the transmission circuit side,
Due to the existence of a phase error between the transmission timing and the shift clock for serial transmission, it was not always possible to obtain an accurate and faithful data transmission interval.

The present invention has been made to solve the above problems, and reduces the load on the CPU and
An object of the present invention is to provide a serial data transmission circuit that can realize an accurate transmission interval.

[0005]

A serial data transmission circuit according to the present invention includes main data to be transmitted and a main data to be transmitted.
Data with the time data that specifies the interval of data transmission.
Read the parallel data, and use the time data
Serial data from the main data at fixed intervals
In a serial data transmission circuit that converts to and outputs
The time data and the predetermined system clock signal is input
It is, slave the time data to said system clock signal
And outputs a time-up signal,
A timer circuit for inputting the next time data by the time-up signal, to generate a transmit clock signal the system clock signal by dividing the transmission clock based on the time-up signal output from the timer circuit a transmission clock generation circuit for correcting the phase of the signal, the by time-up signal captures the main data, the serial data the main data according to the transmission clock signal output from the transmission clock generation circuit which is output from the timer circuit And an output circuit for converting and outputting to.

[0006] In a preferred embodiment of the present invention, when the serial data identifies whether the transmitting, the serial data is being transferred when said time-up signal from the timer circuit is outputted Is a control unit that delays the input timing of the next time data to the timer circuit, the phase correction timing of the transmission clock generation circuit, and the acquisition timing of the main data to the output circuit until the transfer of the serial data is completed. Further provided.

[0007]

According to the present invention, the timer circuit accurately measures the data transmission interval and outputs the time-up signal for giving the data transmission timing, and the phase of the transmission clock signal is also corrected by the time-up signal. Therefore, no time error occurs in the data transmission timing, and the serial data can be transmitted at the designated accurate timing. Further, the CPU does not need to manage the transmission interval, only needs to supply the time data and the main data at a relatively free timing, and the load thereof is significantly reduced.

When a time-up signal is generated during transmission of serial data, a control means for delaying the input timing of the next data and the phase correction timing of the transmission clock until the end of the transmission of the serial data is further provided. Even if the next data transmission request occurs during transmission of serial data, the data currently being transmitted is not destroyed and serial data can be continuously transmitted. The serial data transmission method according to the present invention is
Specified main data and the interval of transmission of this main data.
Read the parallel data paired with the time data
And at the interval specified by the time data,
Serial to convert main data to serial data and output
In the data transmission method, the time data is set to a predetermined system.
System clock signal to count and time up
Signal is output and the next
Start counting the time data of the
Generates a transmit clock signal by dividing the stem clock signal
And the transmission based on the time-up signal
The step of correcting the phase of the clock signal,
Acquire the main data by an up signal and send the data
The transmission clock signal output from the clock generation circuit
According to the above, the main data is converted to serial data and output
And a step of performing. Of this invention
In a preferred embodiment, the serial data is being transmitted
And whether the time-up signal is output.
If the serial data is being transferred when
Is the input timing of the next time data, the transmission clock
Phase correction timing of the signal and loading of the main data
Delay the timing until the transfer of the serial data is completed.
Delay.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings. 1 is a block diagram of a serial data transmission circuit according to an embodiment of the present invention. This circuit inputs time data and main data, converts the main data to parallel / serial at a transmission interval designated by the time data, and outputs the main data. The timer circuit 1, the counter circuit 2, the output circuit 3, and the two circuits are provided. The register circuits 4 and 5 are provided. The data input to this circuit is parallel data which is supplied from a CPU (not shown) and is a pair of time data and main data. The time data is data designating an interval until the transmission of the next main data, and the main data is parallel transmission data of a fixed length such as 1 word unit or 1 byte unit.

The time data and the main data are stored in the register circuits 4 and 5, respectively. The time data stored in the register circuit 4 is loaded into the timer circuit 1 every time the time-up signal b is input from the terminal L. When the time data is loaded, the timer circuit 1 down-counts the time data according to the system clock a input from the terminal CK. Then, when the count value becomes 0, the time-up signal b is output and the next time data is loaded. The time-up signal b is also given to the counter circuit 2 and the output circuit 3.

The counter circuit 2 constitutes a transmission clock generation circuit and, like the timer circuit 1, performs a counting operation in response to a high-speed system clock a. The counter circuit 2 is set or reset by the input of the time-up signal b, divides the system clock a at a desired timing, and outputs a shift clock c as a transmission clock. This shift clock c is supplied to the output circuit 3. The output circuit 3 is composed of, for example, a shift register or the like, loads the main data stored in the register circuit 5 in parallel in response to the time-up signal b supplied to its terminal L, and is supplied from the counter circuit 2. The main data loaded according to the shift clock c is output serially.

FIG. 2 is a timing chart showing the operation of this circuit in more detail. From the CPU (not shown)
Time data Δti + 1 (i = ..., n-1, n, n + 1,
...: same as below and main data di (i = ..., n-1, n,
n + 1, ...: Same as below) is supplied, but the input timing of this data is from the end of transmission of the serial data di-1 to the generation of the next time-up signal b. Such timing may be used. These data supplied from the CPU are held in the registers 4 and 5 until the next data is supplied. Meanwhile, when the time-up signal b is generated, the time data .DELTA.ti is loaded into the timer circuit 1 at the rising timing thereof, and at the same time, the count-down in the timer circuit 1 is started. The signal b is output and the next time data Δti + 1 is loaded into the timer circuit 1. Although the time data .DELTA.ti is defined as the transmission interval between the main data di-1 and the main data di, the time data .DELTA.ti is defined as the transmission interval between the main data di and the main data di + 1. If it is defined as a transmission interval, .DELTA.ti and di are loaded at the same time.

FIG. 3 is a timing chart showing the transmission timing of serial data. Time-up signal b
Both the shift clock c and the shift clock c are synchronized with the high-speed system clock a. However, since the shift clock c is a low-speed clock obtained by dividing the system clock a, the time-up signal b and the shift clock c are Are not necessarily in phase synchronization. Therefore, in this circuit, the shift clock c from the counter circuit 2 is reset by the leading edge of the time-up signal b and set by the trailing edge, so that the phase of the shift clock c immediately after the generation of the time-up signal b is forced. Is corrected so as to match the phase of the time-up signal b. As a result, an accurate and faithful data transmission interval can be realized without causing an uncertain processing delay or an asynchronous error.

FIG. 4 is a block diagram of a serial data transmission circuit according to another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. The circuit of this embodiment is different from the circuit of the previous embodiment as a control means for delaying loading of new parallel data and correction of shift clock until the end of transmission when serial data is being transmitted. The point is that a counter circuit 6 and a control circuit 7 are newly added. The counter circuit 6 is a circuit that turns on the gate signal e from the start of transmission of serial data to the end of transmission, and counts the shift clock c input to the terminal CK by the number of bits corresponding to, for example, one word. The control circuit 7 outputs control signals b0, b1, b2 based on the time-up signal b output from the timer circuit 1 and the gate signal e output from the counter circuit 6.

FIG. 5 is a flow chart showing the operation of the control circuit 7. The control circuit 7 outputs the time-up signal b
When it is detected (S1), ON / OFF of the gate signal e is determined (S2). Gate signal e is ON
If it is, wait until it turns off (S
3) When it is turned off, a pseudo time-up signal b'is generated (S4). At the same time, the control signal b1 for correcting the phase of the shift clock c is output to the counter circuit 2 (S5), and the control signal b2 for loading the main data is output to the output circuit 3 (S6). The control signal b1 for turning on the gate signal e is output to the circuit 6 (S
7) The control signal b0 for loading the next time data is output to the timer circuit 1 (S8). Also, step S
If it is determined in 2 that the gate signal e is OFF, the control signals b0 to b2 are immediately output in order to realize the same operation as in the previous embodiment (S5 to S8).

As a result, as shown in FIG. 6, even when the time-up signal bn is generated during the transmission of the serial data dn-1, the start of the transmission of the next serial data dn is the end of the transmission of the serial data dn-1. The transmission data is continuously transmitted without being destroyed.
At this time, the timer circuit 1 runs free-running and operates as shown by M in the figure because new data is not loaded.
When the transmission of the serial data dn-1 is completed, the gate signal is turned off and the next time data .DELTA.n + 1 is loaded by the control signal b0 as shown by L in the figure, so that there is no problem in operation.

Incidentally, such a phenomenon is caused by time data Δt.
This occurs when n is shorter than the 1-word transmission time of the serial data d. Such a case may occur due to a measurement error or the like in the time data generation process when transmitting continuous data, for example. Is. According to this embodiment, even if the given time data includes an error as described above, the transmission data does not become defective, and it is possible to always reproduce and transmit a normal time interval.

[0018]

As described above, according to the present invention,
Since the timer circuit accurately measures the data transmission interval to give the timing of data transmission, and the phase of the transmission clock signal is also corrected in accordance with the transmission timing, no time error related to the data transmission timing occurs, As a result, the serial data can be transmitted at the specified accurate timing, and the burden on the CPU can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a serial data transmission circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the circuit.

FIG. 3 is a timing chart showing the operation of the circuit.

FIG. 4 is a block diagram of a serial data transmission circuit according to another embodiment of the present invention.

FIG. 5 is a flowchart showing an operation of a control circuit in the same circuit.

FIG. 6 is a timing chart showing the operation of the circuit.

[Explanation of symbols]

1 ... Timer circuit, 2, 6 ... Counter circuit, 3 ... Output circuit, 4, 5 ... Register circuit, 7 ... Control circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 13/38 350 G06F 13/42 350 WPI (DIALOG)

Claims (4)

(57) [Claims] 1. Main data to be transmitted and this main data
Pair with time data that specifies the transmission interval
Parallel data is read and specified by the time data.
The main data is converted to serial data at
In serial data transmission circuit for outputting the changeover, the time data and the predetermined system clock signal is input
It is, slave the time data to said system clock signal
And outputs a time-up signal,
A timer circuit for inputting the next time data by the time-up signal, to generate a transmit clock signal the system clock signal by dividing, before being output from the timer circuit
A transmission clock generation circuit for correcting the phase of the transmission clock signal based on the serial time-up signal, takes in the main data by the time-up signal output from the timer circuit, the output from the transmission clock generation circuit An output circuit for converting the main data into serial data and outputting the serial data according to a transmission clock signal. Wherein identifying whether the or the serial data is being transmitted, wherein when the serial data from the timer circuit when said time-up signal is output is being transferred, to the timer circuit Further comprising control means for delaying the input timing of the next time data, the phase correction timing of the transmission clock generation circuit, and the acquisition timing of the main data to the output circuit until the transfer of the serial data is completed. Claim 1
The described serial data transmission circuit. 3. The main data to be transmitted and the main data
Pair with time data that specifies the transmission interval
Parallel data is read and specified by the time data.
The main data is converted to serial data at
In the serial data transmission method of converting and outputting, According to a predetermined system clock signal, the time data
While counting and outputting the time-up signal,
The next time data is counted by the time-up signal
The steps to start, Transmission clock signal by dividing the system clock signal
And generate based on the time-up signal
A step of correcting the phase of the transmission clock signal, Capture the main data by the time-up signal
Only the transmission output from the transmission clock generation circuit
The main data is converted to serial data according to the clock signal.
The step of converting and outputting It is characterized by having
Serial data transmission method. 4. Whether or not the serial data is being transmitted
When the time-up signal is output,
If the serial data is being transferred, the next time
Data input timing, phase of the transmission clock signal
Correction timing and acquisition timing of the main data
Is delayed until the transfer of the serial data is completed.
Item 3. The serial data transmission method according to item 3.