JPS6272241A - Frame synchronizing device - Google Patents

Abstract

PURPOSE:To decrease the synchronizing word even if noise exists in a transmission line by measuring the content of a shift register through which a transmission data passes and the intensity of correlation as the content of a synchronizing word generating circuit and using a digital integration circuit to compare the measured value a threshold value after the measured value is integrated in a digital integration circuit by one frame period. CONSTITUTION:The content of a shift register 6 through which a transmission data having a synchronizing word passes is compared and counted with the content of a synchronizing word generating circuit 7 by an exclusive OR circuit 8 and a measuring circuit 9 at each bit, the measured value representing the intensity of the correlation between the synchronizing word and the content of the shift register 6 is sent from the circuit 9 and inputted to a digital integration circuit 15. The integration circuit 15 consists of an adder circuit 10, a buffer memory 11 and an attenuation circuit 12, the own output is fed back to the adder circuit 10 through the attenuation circuit 12 while being subject to 1 frame delay, and the output of the circuit 9 is compared with a threshold value of a threshold value generating circuit 13 at a comparator circuit 14. Thus, even when the noise in a transmission line is large, the reduction in the accuracy is prevented and the synchronization by a short synchronizing word is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization device that detects a synchronization word in a frame of transmission data and generates a frame synchronization pulse.

[Conventional technology]

FIG. 2 is a block diagram of a conventional frame synchronization device. In the figure, ■ is a shift register with a number of bits equal to the synchronization word length of the transmission data, 2 is a synchronization word generation circuit, and 3 is a measurement of the number of matching bits between the contents of shift register 1 and the contents of synchronization word generation circuit 2. 4 is a comparison circuit, and 5 is a threshold generation circuit. Comparison circuit 4 compares the output of metering circuit 3 and the output of threshold generation circuit 5 to generate a frame synchronization pulse.

In this configuration, the transmission data passing through the shift register 1 is compared with each bit of the synchronization word for the number of synchronization word length bits including the bit in each bit of the frame, and exclusive OR is performed. - Calculate the number of political opponents i using the measuring circuit 3. Next, this measured value is compared with the threshold value generated by the threshold generation circuit 5 in the comparator circuit 4, and if the above-mentioned measured value is greater than the threshold value, that is, the correlation between the transmitted data and the synchronization word is determined. If the strength is above a predetermined level, it is determined that the contents of the shift register r are a synchronization word, and the comparator circuit 4 generates a frame synchronization pulse (frame start pulse).

[Problem that the invention seeks to solve]

As described above, the conventional frame synchronizer compares each bit of the synchronization word length bit number of the transmission data arriving through the transmission path with the synchronization word and directly compares the number of matching bits obtained with the threshold value, so that the transmission When the road noise is large, it is necessary to increase the synchronization word length, resulting in a problem of poor frame utilization.

This invention was made in order to solve the above-mentioned conventional problems, and an object of the present invention is to obtain a frame synchronization device that can shorten the synchronization word length of transmission data and increase the frame utilization rate compared to the conventional method. .

[Means to solve the problem]

In order to achieve the above object, the present invention includes an adder circuit whose one input is the strength of correlation with the synchronization word obtained by comparing incoming transmission data with the synchronization word; A buffer memory that stores frame bits, an attenuation circuit that attenuates the output of the buffer memory, and a digital integration circuit whose output is the other input of the addition circuit, and an output of the digital integration circuit. The configuration is such that a frame synchronization pulse is generated when the value is greater than or equal to a threshold value.

[Effect]

In this invention, the strength of the correlation between the contents of the shift register and the contents of the synchronization word generation circuit is measured, and the measured value is integrated in one frame period by a digital integration circuit and compared with a threshold value. It is possible to prevent a decrease in accuracy due to the synchronization word, and the synchronization word can be shortened.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention. In the figure, 6 is a shift register with a number of bits equal to the synchronization word length of the transmission data, 7 is a synchronization word generation circuit, and 8
is an exclusive OR circuit. This exclusive OR circuit 8 takes the exclusive OR of each bit of the output of the shift register 6 and the output of the synchronization word generation circuit 7. 9 is a measuring circuit that measures the output of the exclusive OR circuit 8. This measuring circuit 9
The output becomes the input of the digital integration circuit 15. The digital integration circuit 15 includes an adder circuit 10 to which the output of the weighing circuit 9 is coupled to one input, and a buffer memory 11 whose output bit string is one frame bit long and which outputs the output of the adder circuit 10 after being delayed by one frame time. , an attenuation circuit 12 that attenuates the output of the rA buffer memory 11 with an appropriate time constant.
The output of the attenuation circuit 12 becomes the other input of the addition circuit 10. The integrated output of the digital integration circuit 15 is compared with the contents of the threshold generation circuit 13 by a comparison circuit 14.

Next, the operation of this device will be explained.

The contents of the shift register 6 through which the transmission data with the synchronization word passes are determined by the exclusive OR circuit 8 and the weighing circuit 9.
Each bit is compared and counted with the contents of the synchronization word generation circuit 7 in the process described for the conventional example, and the measurement circuit 9 outputs a metric indicating the strength of the correlation between the synchronization word and the contents of the shift register 6. The measured value is sent to the digital integration circuit 15.

Now, if one frame time is T, the output of the metering circuit 9 starts at time t=Q with the synchronization word in the frame being the contents of the shift register 6, and the maximum metric value of the metering circuit 9 is n. Then, the output series X (nT
) is X(nT)=nxU(nT)...il
) However, U (nT): unit step function
It can be expressed as ゛. Furthermore, if the attenuation rate of the attenuation circuit 12 is a, then the transfer function H(z) of the digital integration circuit 15 is
is expressed as H(z) -z/ (z-a)...-121. The Z transformation of the output series of the digital integration circuit 15, Y (z), is Y (2, yo once -z, -1 and main, -1-1-a z-
11-az-a (3) The final value (NT-oo) of this series is n/(
It is expected that it will converge to 1-a).

When the contents of the shift register 6 are a data series, the output of the digital integration circuit 15 changes randomly depending on the statistical properties of the data. Therefore, threshold generation circuit 1
By setting the threshold level according to 3 to an appropriate level, the output of comparator circuit 14 will provide a frame synchronization pulse.

As described above, in this embodiment, the output of the measuring circuit 9 is passed through an attenuation circuit, and the output of the measuring circuit 9 is fed back to the adding circuit with a delay of one frame, and the output of the adding circuit 10 is compared with a threshold value. Therefore, the noise on the transmission path is large (although it is possible to prevent a decrease in accuracy due to this noise), and frame synchronization using a short synchronization word is possible.

〔Effect of the invention〕

As explained above, in this invention, the strength of the correlation between the synchronization word and the data is integrated by a digital integration circuit for each bit in one frame in one frame period, so that short bits can be integrated even on a noisy transmission path. Frame synchronization is possible with a long synchronization word, increasing frame utilization.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional frame synchronization device. In the figure, 6--Shift register, 7--Synchronization word generation circuit, 8--Exclusive OR circuit, 9--Measuring circuit, 10--Addition circuit, 11-Buffer memory, 1
2--Attenuation circuit, 13- Threshold generation circuit, 14-
...Comparison circuit.

Claims (1)

[Claims] The number of bits equivalent to the synchronization word length in one frame of the incoming transmission data is compared with the synchronization word for each bit to measure the degree of correlation between the two, and if the measured value is greater than a threshold value, a frame synchronization pulse is generated. A frame synchronization device for generating frames includes an adder circuit that receives the above-mentioned measured value as one input, a buffer memory that stores the output of the adder circuit for one frame, and an attenuation circuit that attenuates the output of the buffer memory. 1. A frame synchronization device, comprising: a digital integration circuit which is the other input of the adder circuit, and generates a frame synchronization pulse when the output of the digital integration circuit is equal to or higher than a threshold value.