JP2002162427A - Frequency-measuring circuit and digital signal processor using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency-measuring circuit, capable of accurately measuring the cycle of a sampling frequency Fs using a simple constitution, using a digital circuit suitable for use by incorporating it in a signal processor or the like. SOLUTION: This circuit is provided with a master counter clock 17 for counting clock signals inputted into a clock terminal CK; a sample number counter 25 for counting input-side or output-side Fs (sampling frequency) synchronizing clock signals inputted into the clock terminal CK, registers 30 and 33 for storing the measurement cycle of the counter 25; comparators 28 and 31 for comparing counts CNT2 of the counter 25 with the measurement cycle stored in the registers 30 and 33; a register group comprising a plurality of registers 19 and 20 or registers 34 to 38 for sequentially storing counts CNT1 of the counter 17, according to the outputs of the comparators 28 and 31; and subtracters 21 and 40 for finding variations in the counts CNT1 stored in the register group.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency measuring circuit suitable for comparing the frequencies of a plurality of different signals and a digital signal processing device using the same.

[0002]

2. Description of the Related Art In digital equipment such as digital audio equipment, various sampling frequencies such as 32 kHz, 44.1 kHz, and 48 kHz are used. When devices having different sampling frequencies are connected to each other, data is transmitted from a transmitting device. It is necessary to convert the sample sequence to the sampling frequency of the receiving device. For example, at a sampling frequency of 48 kHz, data stored on a DVD (digital video disk) is converted to a CD (compact disk).
When dubbing for
It is necessary to convert to kHz. Similarly, when connecting digital devices having the same sampling frequency but driven by different system clocks, the sample sequence sent from the sending device is also synchronized with the sampling frequency of the receiving device. Frequency conversion is required.

In such a digital signal processing apparatus for converting the sampling frequency, the sampling frequency on the input side and the sampling frequency on the output side are accurately measured, and the fluctuation of the sampling frequency is detected accurately and without delay. It is necessary. In the sampling frequency converter as described above, configurations for measuring the sampling frequency are described in JP-A-5-235698, "Sampling frequency converter", JP-A-5-259812, "Sampling frequency converter" and the like. Have been. The sampling frequency measuring devices described in these publications have attempted to measure the sampling frequency with high accuracy by measuring the sampling frequency using a bit clock or a system clock of about 256 times.

In the configuration for measuring the frequency in the conversion of the sampling frequency as described above, a general-purpose CPU is provided outside a digital signal processing circuit (DSP) for performing the frequency conversion, and a timer or the like in the general-purpose CPU is used. There has been an example in which the frequency is measured using the frequency, and the value is given to a signal processing circuit and used. Alternatively, when the sampling frequency Fs is changed during the signal processing, the signal processing circuit obtains information on the sampling frequency Fs from the outside by some method, and replaces or changes a program or a coefficient according to the information. . In addition, there is a signal processing circuit having a sample number counter in each signal processing circuit.

[0005]

SUMMARY OF THE INVENTION In the prior art,
In a configuration in which the sampling frequency is measured using a bit clock or system clock that is about 256 times, the measurement accuracy is about 8 bits, and sufficient accuracy may not be obtained in some cases. In addition, a high-speed clock may be required to obtain sufficient accuracy.

In a configuration in which frequency measurement is performed outside the signal processing circuit, a measurement value of the sampling frequency Fs is obtained from the outside of the signal processing circuit by handshaking, interruption, or the like. There was a problem of being late. Further, since the value is received via an external port or a data bus, the usage in the signal processing circuit may be limited. For example, there arises a problem that the value of the sampling frequency Fs cannot be used as an address index of a ROM (Read Only Memory) or a RAM (Random Access Memory), or that some extra processing time is required to use it. There was a case.

Further, in the conventional technology, in a configuration in which a sample number counter is provided in each signal processing circuit, a mechanism such that the sample number counter of each chip is simultaneously reset and the count operation can be performed in synchronization. Was not used.

The present invention has been made in view of the above circumstances, and has a simple configuration using a digital circuit suitable for use by being built in a signal processing device or the like. It is an object of the present invention to provide a frequency measurement circuit capable of performing measurement and a digital signal processing device using the same. It is another object of the present invention to provide a frequency measurement circuit having a similar configuration and capable of detecting a change in the sampling frequency Fs.

[0009]

According to a first aspect of the present invention, there is provided a first counter circuit for counting a first clock signal input to a clock terminal, and a first counter circuit for counting a first clock signal input to a clock terminal. A second counter circuit that counts a second clock signal, a first storage circuit that stores a measurement cycle of the second counter, a count value of the second counter, and a value that is stored in the first storage circuit. A first comparison circuit for comparing the measured period with the first measurement circuit; and a first storage circuit group including a plurality of storage circuits for sequentially storing the count value of the first counter circuit in accordance with the output of the first comparison circuit. , A first arithmetic circuit for determining a change in the count value stored in the first storage circuit group.

The invention according to claim 2 is characterized in that the first arithmetic circuit obtains a difference between stored values of any two storage circuits in the first storage circuit group. According to a third aspect of the present invention, a second counter for storing a measurement cycle of the second counter is provided.
Storage circuit, the count value of the second counter and the second
And a plurality of storage circuits for sequentially storing the count value of the first counter circuit in accordance with the output of the second comparison circuit. And a second arithmetic circuit for calculating a change in the count value stored in the second storage circuit group. According to a fourth aspect of the present invention, there is provided a third comparison circuit for comparing a count value of the first counter circuit with a predetermined set value, and a third storage circuit for storing a comparison result by the third comparison circuit. It is characterized by having.

According to a fifth aspect of the present invention, the first selection circuit selects the clock signal of the first counter circuit from a plurality of signals, or selects the clock signal of the second counter circuit from a plurality of signals. And at least one of the second selection circuits. According to a sixth aspect of the present invention, the apparatus further comprises a third selection circuit for selecting a reset signal of the first counter from a plurality of signals.
The invention according to claim 7 is characterized in that a fourth selection circuit for selecting a reset signal of the second counter from a plurality of signals is provided. The invention according to claim 8 is characterized in that the cycle of the first clock signal is shorter than the cycle of the second clock signal. According to a ninth aspect of the present invention, there is provided a first selection circuit for selecting a clock signal of the first counter circuit from a system clock, an input side bit clock, or an output side bit clock. According to a tenth aspect of the present invention, there is provided a second selection circuit for selecting a clock signal of the second counter circuit from an input-side sample synchronization signal or an output-side sample synchronization signal.

According to an eleventh aspect of the present invention, the third selection circuit outputs a reset signal of the first counter circuit to a plurality of signals including at least a first input-side sample synchronization signal and an output-side sample synchronization signal. It is characterized by selecting from. According to a twelfth aspect of the present invention, the fourth selection circuit outputs a reset signal of the second counter circuit to at least an output of the first comparison circuit, an output of the second comparison circuit, or a predetermined external signal. It is characterized by selecting from a plurality of included signals. The invention according to claim 13 is the invention according to claims 1 to 1
3. A frequency measurement circuit according to any one of 2 to 2, wherein a control signal for controlling at least one of the first to fourth selection circuits is supplied.

According to the above configuration, for example, the period of the sampling frequency Fs can be measured accurately by taking a long measurement time by using two types of counters, or can be generated in a relatively short time by taking a short measurement time. Of the sampling frequency Fs to be measured.
In addition, by providing a flag (third storage circuit) that stands when the cycle of the sampling frequency Fs exceeds the set value or interrupts the set value, it is possible to detect that there is a change by looking at the flag. it can. Alternatively, the change can be easily detected by comparing the value of the sampling frequency Fs measured in the long cycle with the value of the sampling frequency Fs measured in the short cycle. Furthermore, by controlling the start and stop of the count of the sample number counter (second counter circuit) by an external control signal, the number of samples can be synchronized between a plurality of signal processing device chips or the like. Can be provided with a function suitable for counting the numbers.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a frequency measuring circuit (frequency measuring device) according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of the present embodiment. The frequency measurement circuit according to the present embodiment is used by being built in a digital signal processing circuit (DSP) or the like that converts an input sample sequence into an output sample sequence that is asynchronous with a digital device such as a digital audio device. , The sampling frequency on the input side, the sampling frequency on the output side, the system clock frequency, and the like, and their absolute or relative changes can be measured. Signals I1 to I6 shown in FIG. 1 are signals input from a digital signal processing device including this circuit,
O2 and Fs (sampling frequency) measurement value 1, Fs
The measurement value 2 is a signal output to the digital signal processing device. Further, selectors 16, 18, 24, 27
And 39, select signals S1, S2, S
3, S4, and S5 are supplied from the digital signal processing device, respectively. Input Fs synchronization signal and output F
The s synchronization signal is a signal supplied from the outside, and
It has a frequency synchronized with each sampling signal of the input sample sequence and the output sample sequence. System Clock, Input Bit Cloc
k and an output bit clock are a clock signal having a cycle shorter than that of an input-side Fs synchronization signal and a cycle of an output-side Fs synchronization signal such as a system clock used in a digital signal processing device, and an input and an output, respectively. This is a clock signal corresponding to each bit of the sample sequence.

The frequency measurement circuit shown in FIG. 1 is roughly divided into a master clock counter 17 written in the upper part of the figure and registers (registers (hereinafter referred to as REGs) A (19) to B (REG) A for storing the value thereof. (20), REG 0 (3
4) to REG N (38)).
It is composed of two blocks consisting of a sample number counter 25 written in the lower part of the figure and comparators 28 and 31 for setting the averaging period. The master clock counter 17 is a counter circuit with a reset, and has a system clock selected by the selector 18.
System Clock (input terminal 1), input side bit clock In
put Bit Clock (input terminal 2), output side bit clock O
A count operation is performed using any signal of the output bit clock (input terminal 3) as a clock signal CK, and the count value is output as a signal CNT1. Further, the master clock counter 17 outputs the input-side Fs synchronization signal and the output-side Fs synchronization signal selected by the selector 16 and the fixed value “0”.
Is input as a reset signal RESET, and the input side Fs that repeatedly changes with “1” or “0” is input.
Reset is performed when the synchronization signal or the output side Fs synchronization signal is at “1” level, or operates as a free-run counter without resetting by inputting a fixed value “0”.

REG A (19) and REG 0 (3)
4) are registers for storing the count value CNT1 of the master clock counter 17 in synchronization with changes in the output signal C1 of the comparator 28 and the output signal C2 of the comparator 31, respectively. REG B (20) is REG A (1
9) a register which receives the output of 9) as an input,
At (20), the REG A (19) operates so that the value acquired in synchronization with the immediately preceding change of the signal C1 is acquired in synchronization with the next change. N (N is a natural number) REs
G 1 (35), REG 2 (36) to REG N (3
8) are REG 0 (34) and REG 1
(35) to REG N-1 (37) are registers which receive the output, and sequentially register in synchronization with the change of the signal C2.
It operates to transmit the value it holds. REG C
(22) is processed by the subtractor 21 in REG A (19).
Is a register for storing the result (Fs measurement value 1) obtained by subtracting the value held by REG B (20) from the value held by. REG X (41) is calculated by the subtractor 40 as RE
From the value of G 0 (34), the value of R
This register stores the result (Fs measurement value 2) obtained by subtracting the value held by any of EG1 (35) to REG N (38). Here, REG 1 (35) to REGN
The output of (38) is input terminal 1 of selector 39, respectively.
To N. The subtracter 21 and the subtractor 40
For example, not only the subtraction but also the function of measuring the characteristics of Fs, such as calculating the average value of Fs and measuring the maximum and minimum values of Fs, may be provided. The measurement results are REG C (22) and REG X as in the case of the subtractor.
Stored in (41).

REG L (30) and REG S (33)
Is a register for setting the averaging cycle specified according to the inputs I4 and I6. The averaging cycle is defined as the master clock counter 17
This is the cycle of taking in the counter value CNT1 of each of the registers. The comparator 28 and the comparator 31 respectively include the count value CNT2 of the sample number counter 25 and the REG L
The setting value of (30) and the setting value of REGS (33) are compared, and when they match, outputs C1 and C2 are output. That is, the count value C of the sample number counter 25
NT2 receives REG L (30) or REG S (3
When the period becomes equal to the set period set in 3), the count value C of the master clock counter 17 is set.
NT1 registers REG A (19) or REG
At the same time as being stored at 0 (34), the value of each register is sequentially taken in and stored in the next register. However, in this case, the comparator 28 and the comparator 31
It has a function of arbitrarily setting bits to be compared according to the values set in the registers 29 and 32, respectively.

Operation clock C of the sample number counter 25
K is an input Fs synchronization signal (input terminal 1) or an output Fs synchronization signal (input terminal 2) by the selector 27.
You can choose from. However, the output of the selector 27 is input to the clock terminal of the sample number counter 25 after being delayed by a predetermined time by the delay circuit 26. The reset signal RESET of the sample number counter 25 is output by the selector 24 from the output (input terminal 1) of the flag circuit (latch circuit) 2B set by a predetermined external signal, the output C1 (input terminal 2) of the comparator 28, “0”, that is, a signal (input terminal 3) for making it not always reset, or the output C2 of the comparator 31 (input terminal 4)
You can choose from. The latch circuit 23 is a set-reset flip-flop circuit that uses a predetermined external signal as a set signal SET and uses the output of the selector 27 as a reset signal RESET.

The comparator 14 written above the master clock counter 17 is the master clock counter 1.
7 and the set value P of REG P (11), and outputs a signal SET for setting the flag circuit FLAG A (10) if "CNT1 <P". The comparator 15 compares the count output CNT1 of the master clock counter 17 with the set value Q of the REG Q (12), and if "Q <CNT1," the flag circuit F
A signal SET for setting LAG B (13) is output. Flag circuit FLAG A (10) and FLAG
B (13) is a circuit configured in the same way as the flag circuit 23. The reset signal RESET supplied from the digital signal processing device or the like is used as a reset input, and the outputs of the comparators 14 and 15 are set signals. SET
And outputs the outputs O1 and O2. Each circuit written above the master clock counter 17 causes the value CNT1 of the master clock counter 17 to be lower than the predetermined value P or to exceed Q.
Each flag circuit FLAG A (10) and FLAGB
An operation is performed to set the flag set in (13). This can be used for detecting a change in the input side or the output side Fs.

The operation of the configuration shown in FIG. 1 will be described below. The master clock counter 17 is a counter used for measuring a sampling frequency (Fs) or the like, and operates a system clock System Clock, an input side bit clock Input Bit Clock, and an output side bit clock Out.
Select from put Bit Clock and count up.

When measuring Fs on the input side or output side, the master clock counter 17 is free-run without being reset and used. That is, the selector 16 selects the signal “0” (input terminal 3). As the clock CK of the master clock counter 17, the selector 18 selects the system clock System Clock (input terminal 1). The selector 27 selects the input-side Fs synchronization signal when measuring the input-side Fs (input terminal 1), and selects the output-side Fs synchronization signal when measuring the output-side Fs (input terminal 2). . The sample number counter 25 counts up every one sample period of the measured frequency. In this case, the selector 24 selects and inputs the output C1 of the comparator 28 to the reset input of the sample number counter 25 when the set value of REG L (30) is used as the averaging cycle (input terminal 2). REG S
When the set value of (33) is used as the averaging period, the output C2 of the comparator 31 is selected and input by the selector 24 (input terminal 4), and the value based on the set value of REGL (30) is averaged. REG the measurement result as the cycle
At the same time as obtaining at C (22) and obtaining at REG X (41) a measurement result with a value based on the set value of REG S (33) as another averaging cycle, the sample number counter 25 is set to free run. To operate as a counter, a fixed value “0” is input.

REG L (30), REG S (33)
Is set to a value indicating how many cycles to measure. The longer this cycle is, the higher the measurement accuracy is, but if Fs changes, the follow-up becomes poor. REG L (30), RE
The comparator 28 and 31 compare the cycle set in the GS (33) with the value of the sample number counter 25, and when they match, the value of the master clock counter 17 is taken into REG A (19) or REG 0 (34). At this time, the comparators 28 and 31 determine bits to be compared based on the data set in the registers 29 and 30. RE
G A (19), B (20) and REG 0 (34)-
N (38) is a FIFO (First-In First-O
ut). That is, REG
The value of A (19) is stored in REG B (20) and REG 0
The value of (34) is assigned to REG 1 (35) and REG 1 (3
The data of the value of 5) is transferred to REG 2 (36).

The comparator 28 determines the bit to be compared based on the mask bit set in the register 29, and the count value CNT2 of the sample number counter 25 is R
When the value becomes equal to the set value of EGL (30), the output C1
To “1”. When the output C1 of the comparator 28 becomes "1", a new value is taken into REG A (19),
Next, the data that had been in REG A (19)
B (20), at which point the subtractor 21 takes the difference between the two registers and the result is REG C (22)
Is stored in This represents the number of clock generations of the system clock System Clock during the occurrence of the input side or the output side Fs for the period of the value set in REGL (30), and becomes the measured value 1 of Fs.

On the other hand, the comparator 31 determines a bit to be compared on the basis of the mask bit set in the register 32, and determines the count value CNT2 of the sample number counter 25.
Becomes equal to the set value of REG S (33), the output C2 is set to "1". The output C2 of the comparator 31 is "1"
, The new value is taken into REG 0 (34), and then REG 0 (34) to REG N-1
The data in (37) is REG 1 (35), respectively.
REG N (38), at which point the subtractor 40
Are the values of the registers REG 0 (34) and the registers REG 1 (35) to REG N selected by the selector 39.
The difference between the values of any of the registers in (38) is obtained, and the result is stored in REG X (41). This is the measured value 2 of Fs.

The averaging cycle is REG L
When the measurement value is obtained in REGC (22) by setting to (30), the output C1 of the comparator 28 is input to the reset input of the sample number counter 25, and the count value of the sample number counter 25 is It is reset every time it matches the value of REG L (30). When the averaging cycle is set to REG S (33) and the measured value is obtained in REG X (41), the output C2 of the comparator 31 is input to the reset input of the sample number counter 25. The sample number counter 25 is reset every time the count value matches the value of REGS (33). Furthermore, the averaging cycle is set to REG.
L (30) and set the measured value in that cycle to REG
In the case where the other averaging cycle is set to REG S (33) and the measured value according to the cycle is obtained in REG X (41) at the same time as obtaining at C (22), it is fixed to the reset input of the sample number counter 25. A value "0" is input to operate as a free counter, and mask data is set in the registers 29 and 32 to determine bits to be compared by the comparators 28 and 31, and based on the set values of different averaging periods. "1" is output to the outputs C1 and C2.

Next, the operation for obtaining the ratio of Fs between the input side and the output side will be described. In the frequency measuring circuit of FIG. 1, the ratio of input / output Fs can be obtained in a system in which Fs is different between the input side and the output side by selecting the operation clocks of the two counters 17 and 25. For example, if the master clock counter 17 is operated with the input bit clock and the sample number counter 25 is operated with the output side Fs synchronization signal, the ratio of Fs is obtained in REGC (22) and REG X (41). In this case, the master clock counter 17 selects the “0” input by the selector 16 and operates as a free-run counter.
5, the output of the comparator 28 or the comparator 31 or the fixed value "0" is input to the reset input.

The cycle setting registers REG L (30) and REGs A (19) and B (20) are used when the averaging cycle is relatively long. On the other hand, REG S (33)
And REGs 0 (34) to N (38) are used when the averaging period is short and a follow-up property to the fluctuation of Fs is required. For example, when the operation clock of the master clock counter 17 is about 256 divisions of Fs (8 bits) and a 24-bit precision Fs measurement value is required, REG L (30)
Should be set to 2 ¹⁶ (= 65536). However, the Fs that occurred during 65536 samples
Will not be able to keep up with the changes. One of the methods for improving the followability is to shorten the averaging period. For example, if one wants to know the value of Fs for each sample, the value of Fs can be obtained only with an accuracy of about 8 bits in the above example. You will not be able to get. Every sample F
If you want to know the value of s and want a little more precision, REG S (33) and REG 0 (34)-N
Use (38). For example, N = 32 (storage register RE
Considering the case where G1 to REGN are equivalent to 32 words), when the master clock is also about 256 times the frequency of Fs (8 bits), REG S (33 ) Is set to 8
Bits + 5 bits = Fs per sample with 13-bit precision
Can be obtained. The number of words to be stored can be selected by the selector 39, and the measurement accuracy of Fs is determined by the number of words and the averaging cycle. It should be noted that the selector 2 receives the register fetch instruction signal.
7 may be used.

As described above, by comparing two measured values having different averaging periods, a change in Fs can be known from the Fs measured value 2 having good tracking performance, and if there is a change, an accurate Fs measured value can be obtained. For example, a method of finding 1 and using it in a signal processing application is conceivable.

The fluctuation of Fs is FLAG A (1
0) and B (13). In this case, the master clock counter 17 is reset and used according to the Fs cycle. That is, the selector 16 selects the input-side Fs synchronization signal (input terminal 1) when detecting a change in the input-side Fs synchronization signal, and selects the input-side Fs synchronization signal by using the selector 16 when detecting the change in the output-side Fs synchronization signal. The output side Fs synchronization signal (input terminal 2) is selected. The selector 18 selects and inputs a system clock System Clock (input terminal 1) as the clock CK of the master clock counter 17. If the counter value CNT1 is REG P (1
If reset before reaching the value set in 1), FL
If AG A (10) rises and is reset beyond the value set in REG Q (12), FLAG B (13)
Stands. The digital signal processor sees this flag and
Can be determined whether or not has changed. In addition, FLA
The timing for resetting GA (10) and B (13) can be set at an arbitrary timing by the digital signal processing device.

As described above, the sample number counter 25
Can be set to free-run or a reset signal can be selected from a comparator output and an external signal (set input of the flag circuit 23). When the free run is performed without using the reset signal, the input terminal 3 is selected by the selector 24.
When the reset signals are output C1 and C2 of the comparators 28 and 31, the selector 24 selects the input terminals 2 and 4, respectively. When the reset signal is an external signal, the input terminal 1 is selected. In the case of the free run, the bits other than the comparison target bit of the output of the sample number counter 25 are masked by the MASK registers 29 and 32 so that the comparison output is output with the value set in the cycle setting registers 30 and 33. The reset by an external signal is used when, for example, it is desired to simultaneously start sample counting in a plurality of chips. For example, first, an external signal that changes from “0” → “1” → “0” is input as one pulse to the set input SET of the flag circuit 23, the flag circuit 23 is set, and the sample number counter 25 is reset. Next, when the input side or output side Fs synchronizing signal becomes “1” level, the flag circuit 23 is reset and the sample number counter 25 is reset.
"0" is input to the reset input RESET of, and the count operation becomes possible. Next, the input-side or output-side Fs synchronization signal delayed by a predetermined time by the delay circuit 26 is input to the clock input CK and counted. In this case, after the input of the external signal, the next input side or output side F
With the s synchronization signal as the first clock, the sample number counter 25 starts the counting operation. Then, after the sample number counter 25 starts the counting operation,
For example, the selection of the selector 24 is switched to the input terminal 2 or the input terminal 4, and the sample number counter 25 is reset according to the output of the comparator 28 or 31.

FIG. 2 shows a list of setting examples of each circuit in the various operations described above and circuits for outputting the measurement results. In the chart of FIG. 2, for example, the measurement item is the input side Fs
, The averaging cycle is REG L (30)
Setting method and averaging cycle to REG
The setting method to be set in S (33) and the two types of averaging periods are REG L (30) and REG S
It is shown that there are three types of setting methods (33). In the table of FIG. 2, for each measurement item, the terminal number of the input terminal to be selected by the selectors 16, 18, 24, 27, and 39 in each setting method, the averaging period setting destination register, and the measurement result output destination Register and F
The lower limit and the upper limit register of the detection value when the measurement result is obtained using the LAGs A (10) and B (13) are shown. In the remarks column, the case where the MASK registers 29 and 32 are used and the case where the FLAGs A (10) and B (13) are used are described among a plurality of measurement methods.

In FIG. 2, for example, there are three types of measurement methods for measuring the input side Fs, and when the averaging cycle is set to REG L (30), the inputs of the selectors 16, 18, 24, and 27 are required. It is shown that they are set to the input terminals 3, 1, 2, and 1, respectively, and that an output corresponding to the cycle of the input side Fs is obtained at the REG C (22). When the averaging cycle is set to REGS (33) when measuring the input side Fs,
The inputs of the selectors 16, 18, 24, 27, and 39 are set to any of the input terminals 3, 1, 4, 1, 1 to N, and the output corresponding to the cycle of the input side Fs is REG.
X (41) shows that it is obtained. When the averaging cycle is set to REGL (30), the setting of the selector 39 and the setting of the cycle as the lower limit and the cycle as the upper limit for detecting the frequency fluctuation are not necessary. Is indicated by entering a "-" mark in the column, or leaving the corresponding column blank. As another example, when a value corresponding to the frequency ratio between the input side Fs and the output side Fs is obtained (measurement item: output side Fs / input side Fs), the averaging cycle is set to REGL (30). Sometimes, the inputs of selectors 16, 18, 24, 27 are set to input terminals 3, 3, 2, 1 respectively,
The output corresponding to the frequency ratio between the input side Fs and the output side Fs is RE.
GC (22) shows that it is obtained.

As described above, according to the present embodiment, the following operation can be obtained. A master clock counter 17 capable of counting a plurality of bits in one sample period and a sample counter 25 that counts up by one for each sample are combined to perform averaging over a plurality of sample periods, thereby obtaining a highly accurate Fs value without increasing the clock frequency. Can be obtained.

The averaging period is determined by the registers 30 and 3
3 can be set to any value. When the values of the registers 30 and 33 match the value of the sample number counter 25, the value of the master clock counter 17 is sampled and subtracted from the previous value to obtain F at arbitrary accuracy.
It is possible to measure the value of s. When a high-precision value is required, the period may be set long. On the contrary, when the accuracy is not so much required or when it is desired to know the variation of Fs in detail, the period may be set short.

The variation of Fs can be known by the following two methods. One is that by having a plurality of averaging cycle setting registers 30 and 33, the Fs is compared by comparing the Fs with the one with a longer period and the one with the shorter period.
The variation of s can be known. Second, the variation can be known by using the flags 13 and 10 that are set when the period of the sample synchronization signal exceeds or interrupts the values of the setting registers 12 and 11. Knowing the variation of Fs by either of these two methods can be used to change the processing amount or processing content, or to switch the value of coefficient data according to the measured Fs value.

Since the buffer for storing the sample value of the master clock counter 17 has a plurality of words (REG 1 (35) to N (38)), even if the averaging cycle is short, the precision of the number of words in the buffer is added. Thus, the latest Fs value can be obtained for each sample.

The clock input of the master clock counter 17 can be selected from the system clock input side bit clock and the output side bit clock. The clock input of the sample number counter 25 is selected from the input side sample synchronization signal and the output side sample synchronization signal. It is possible to obtain the ratio of input and output Fs. By using this, as described in, for example, Japanese Patent Application Laid-Open No. Hei 5-235698, “Sampling Frequency Converter”, upper bits are assigned to a reference address of a data RAM, lower bits are assigned to input data to an interpolator, and the like. , F
An s conversion function can be realized.

The count start and stop operations of the sample number counter 25 can be controlled by an internal signal or an external signal, so that a process synchronized with the sample can be performed by a plurality of chips.

Next, the function of each circuit constituting the above embodiment will be described with reference to FIG. FIG. 3 is a functional block diagram showing components of the above-described embodiment collectively for each function. Master clock counter 100 of FIG.
Performs a counting operation using a clock signal having a frequency M times the sampling frequency Fs (M is a real number), such as a system master clock signal, as a clock, and corresponds to the master clock counter 17 in FIG. For example, when counting the sampling frequency Fs of the system, M
Indicates the resolution of the master clock with respect to the sampling frequency Fs. Fs measurement circuit 1 (101)
Are REG A (19), REG B (20),
It corresponds to the subtractor 21 and the REG C (22), and the storage circuit 1 (101a) stores the REG A (1
9) and REG B (20) are added to arithmetic circuit 1 (101b)
Corresponds to the subtractor 21 and the REG C (22). The storage circuit 1 (101a) is constituted by a shift circuit having a storage number of 2 and a word length L (L is a natural number), and synchronizes with a cycle of an output signal of the measurement cycle designation circuit 1 (103) to generate a master clock counter. The counter value of 100 is taken in and shifted in the shift circuit. That is, the storage circuit 1 (101
In a), a set of counter values including a current value and a value one cycle before is stored. The arithmetic circuit 1 (101b) performs a predetermined arithmetic process using one set of stored values stored in the storage circuit 1 (101a) to calculate an Fs measurement value 1 that is a measurement value according to the sampling frequency Fs. I do. Examples of the arithmetic processing include a subtraction processing for obtaining a difference between a set of stored values, and an arithmetic processing for obtaining an average value, a maximum value, and a minimum value.

The Fs measurement circuit 2 (102) uses the RE
G 0 (34) to REG N (38), selector 39,
It corresponds to the subtractor 40 and REG X (41), and the storage circuit 2 (102a) stores REG 0 (3
4) to REG N (38) and selector 39, and arithmetic circuit 2 (102b) corresponds to subtractor 40 and REG X (41). The storage circuit 2 (102a) includes a shift circuit having a storage number N and a word length S (S is a natural number),
In synchronization with the cycle of the output signal of the measurement cycle designating circuit 2 (104), the counter value of the master clock counter 100 is fetched and sequentially shifted in the shift circuit. That is,
The storage circuit 2 (102a) stores the current value and N counter values of the past value 1 to N-1 cycles ago.
The arithmetic circuit 2 (102b) uses the N stored values stored in the storage circuit 2 (102a) to determine, for example, the difference between the current value and any value 1 to N-1 cycles ago. An arithmetic process such as a subtraction process is performed to calculate an Fs measurement value 2 which is a measurement value corresponding to Fs.

The measurement cycle designating circuit 1 (103) outputs a signal indicating a measurement cycle when the count number of the sample number counter 105 reaches a value corresponding to the value of the cycle A. REG L (3
0), corresponding to the register 29. Measurement cycle specification circuit 2
(104) outputs a signal indicating a measurement cycle when the count number of the sample number counter 105 reaches a value corresponding to the value of the cycle B.
1, REG S (33), corresponds to the register 32. The sample number counter 105 counts the number of occurrences of a signal synchronized with the sample frequency signal Fs on the input side or the output side and outputs the count number, and corresponds to the sample number counter 25 in FIG.

In the above configuration, the word length S of the storage circuit 2 is usually shorter than that of the storage circuit 1 (S <L) in order to reduce the scale of hardware. The longer the word length S, the greater the number of storages N is required. The storage number N is the word length S
The longer the is, the more is needed. N and S are determined by the cycle B and the resolution M of the master clock.
The Fs measuring circuit 1 can be omitted if N and S can be made large enough to satisfy the required accuracy and followability.

[0043]

According to the present invention, a first counter circuit for counting a first clock signal input to a clock terminal and a second counter for counting a second clock signal input to a clock terminal A first storage circuit that stores a measurement cycle of the second counter; a first comparison circuit that compares a count value of the second counter with the measurement cycle stored in the first storage circuit; A first storage circuit group including a plurality of storage circuits for sequentially storing the count value of the first counter circuit in accordance with an output of the first comparison circuit; and a count value stored in the first storage circuit group. And a first arithmetic circuit for calculating the variation of the clock signal, so that the clock signal to be measured is counted by the first counter circuit using two types of counter circuits,
The second counter circuit counts a clock signal serving as a reference of the measurement cycle, and the first storage circuit allows the measurement cycle generated based on the count to be arbitrarily set. Since the counter value is transferred to the first storage circuit group and the arithmetic circuit calculates the change in the count value stored in the first storage circuit group, a measurement result corresponding to the frequency can be obtained. The effect of being able to accurately measure the period of the sampling frequency Fs with a desired accuracy with a simple configuration using a digital circuit, which is a configuration suitable for being incorporated in a device, etc., and increasing the degree of freedom in changing the setting of measurement conditions. Can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a frequency measurement circuit according to the present invention.

FIG. 2 is a diagram showing a list of settings and operations of the circuit shown in FIG. 1;

FIG. 3 is a functional block diagram collectively showing functions of respective circuits constituting the frequency measurement circuit shown in FIG.

[Explanation of symbols]

10, 13, 23 ... Flag circuit, 11, 12, 19, 2
0, 30, 33, 34, 36, 37, 38 ... registers,
14, 15, 28, 31 ... comparators, 16, 18, 22,
41, 24, 27, 39 ... selector, 17 ... master counter clock, 21, 40 ... subtractor, 25 ... sample number counter.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuo Nakamura 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Corporation (72) Inventor Takaaki Makino 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Corporation F Terms (reference) 2G029 AA01 AA02 AA04 AB05 AC02 AD01 AD08 AE08 AE10 AF03 AF07 AH00 5K029 AA01 HH27 KK22 LL14 LL19

Claims (13)

[Claims] A first counter circuit that counts a first clock signal input to a clock terminal; a second counter circuit that counts a second clock signal input to a clock terminal; A first storage circuit for storing the measurement cycle of the counter, a first comparison circuit for comparing the count value of the second counter with the measurement cycle stored in the first storage circuit, and a first comparison circuit A first storage circuit group consisting of a plurality of storage circuits for sequentially storing the count value of the first counter circuit in accordance with the output of the first counter circuit; and a first storage circuit group for determining a change in the count value stored in the first storage circuit group. A frequency measuring circuit comprising: 2. The frequency measurement circuit according to claim 1, wherein said first arithmetic circuit calculates a difference between values stored in any two storage circuits in a first storage circuit group. 3. A second storage circuit for storing a measurement cycle of a second counter, and a second comparison for comparing a count value of the second counter with a measurement cycle stored in the second storage circuit. A second storage circuit group including a circuit, a plurality of storage circuits that sequentially store the count value of the first counter circuit in accordance with an output of the second comparison circuit, and a second storage circuit group. 2. The frequency measuring circuit according to claim 1, further comprising a second arithmetic circuit for calculating a change in the count value. 4. A semiconductor device comprising: a third comparison circuit for comparing a count value of the first counter circuit with a predetermined set value; and a third storage circuit for storing a comparison result by the third comparison circuit. The frequency measurement circuit according to claim 1, wherein: 5. A first selection circuit for selecting a clock signal of the first counter circuit from a plurality of signals, or a second selection circuit for selecting a clock signal of the second counter circuit from a plurality of signals. The frequency measurement circuit according to claim 1, further comprising at least one of the following. 6. The frequency measurement circuit according to claim 1, further comprising a third selection circuit that selects a reset signal of the first counter from a plurality of signals. 7. The frequency measurement circuit according to claim 1, further comprising a fourth selection circuit that selects a reset signal of the second counter from a plurality of signals. 8. The frequency measurement circuit according to claim 1, wherein a cycle of the first clock signal is shorter than a cycle of the second clock signal. 9. The apparatus according to claim 1, further comprising a first selection circuit for selecting a clock signal of said first counter circuit from a system clock, an input side bit clock, or an output side bit clock. The frequency measurement circuit according to claim 1. 10. The apparatus according to claim 1, further comprising a second selection circuit for selecting a clock signal of the second counter circuit from an input-side sample synchronization signal or an output-side sample synchronization signal. 2. The frequency measurement circuit according to claim 1. 11. The third selection circuit selects a reset signal of the first counter circuit from a plurality of signals including at least a first input-side sample synchronization signal and an output-side sample synchronization signal. The frequency measuring circuit according to claim 6, wherein 12. The fourth selection circuit outputs a reset signal of the second counter circuit to a plurality of signals including at least an output of a first comparison circuit, an output of a second comparison circuit, or a predetermined external signal. The frequency measurement circuit according to claim 7, wherein the frequency measurement circuit is selected from signals. 13. A frequency measuring circuit comprising: the frequency measuring circuit according to claim 1; and supplying a control signal for controlling at least one of the first to fourth selecting circuits. Digital signal processing device characterized by the following.