JP4032929B2 - Frame synchronization method and apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for specifying a frame synchronization position of received data in a digital communication system such as a disaster prevention system that performs communication between a master station and a slave station.
[0002]
[Prior art]
In recent years, as the DSP processing speed has improved, the end of a synchronization word has been detected in the DSP. FIG. 4 is a timing chart of the operation, Ssw is a signal indicating the end of the synchronization word to be detected, D1 is serial data that has been received and converted into an IF signal and then A / D converted, and Sit is For example, Sa is a synchronous position detection notification signal that is generated every time the data D1 is loaded into the DSP buffer by 128 samples. A technique for storing data in a memory in units of 128 samples is described in paragraph “0009” of Patent Document 1.
[0003]
Conventionally, when the data D1 stored in the DSP buffer reaches 128 samples, an interrupt notification signal Sit is generated, and the data D1 is read into the DSP core unit of the DSP for reception processing, and this is repeated. In this reception process, first, frame synchronization is performed based on the end Ssw of the synchronization word, and then each symbol data is demodulated.
[0004]
The end of the synchronization word at this time is specified by, for example, storing the same synchronization word as the 10 synchronization words to be received in the memory in advance, and comparing all the 10 synchronization words with the received synchronization word. It is assumed that the end of the synchronization word of the received data has been detected.
[0005]
When the end of the synchronization word is detected in this way, the notification of the detection is as follows: (1) immediately after the detection, or (2) the 128 samples after the detection, as shown in FIG. This can be done after demodulating data for the minute or when (3) fetching the next data from the buffer into the DSP core unit (when the next interrupt notification signal Sit). Times T1, T2, and T3 are elapsed times from the end Ssw of the synchronization word at the notification timings (1), (2), and (3). A frame synchronization position is set after a predetermined time has elapsed from the timing of the synchronization position detection notification signal Sa.
[0006]
[Patent Document 1]
JP 2001-177588 A
[Problems to be solved by the invention]
However, if the notification signal Sa is generated at any one of the notification timings (1) to (3) as shown in FIG. 4 (a), the next time the synchronization position is detected, The notification timing Sa may be any one of the notification timings (1) to (3) as shown in b). The elapsed times T1, T2, and T3 from the end Ssw of the synchronization word depend on the position of the interrupt notification signal Sit. It will be mixed. In particular, when the end of the synchronization word spans 128 samples previously read into the DSP core and 128 samples read next, the elapsed times T1, T2, and T3 may be shifted by the time interval of the interrupt notification signal Sit. . This is because the synchronization word end Ssw and the interrupt notification signal Sit are not in a synchronous relationship.
[0008]
As a result, there arises a problem that the synchronization position cannot be detected accurately even though the frame synchronization position coming after a predetermined time has elapsed from the end Ssw of the synchronization word as described above.
[0009]
An object of the present invention is to provide a frame synchronization method and apparatus capable of accurately detecting a frame synchronization position.
[0010]
[Means for Solving the Problems]
The invention according to claim 1 performs demodulation processing by reading the data from the DSP buffer into the DSP core unit of the DSP by an interrupt notification signal generated every predetermined number of samples of the received and A / D converted data. In the frame synchronization method for generating a frame synchronization signal in accordance with the slot timing when the first time has elapsed from the time when the synchronization word end is detected by the demodulation processing, the DSP core unit When a synchronization word end is detected, a second time from the previous interrupt notification signal to the detection point of the synchronization word end is detected, and the second time from the next occurrence of the interrupt notification signal is detected. The third time when measuring and subtracting twice the period of the interrupt notification signal from the first time from the end point of the measurement of the second time Was measured, the end point of time of the measurement of the third and the frame synchronization method which is characterized in that said slot timing.
[0011]
The invention according to claim 2 is the frame synchronization method according to claim 1, wherein the frame synchronization method is applied to the slave station of a communication system including a master station and a slave station that perform transmission and reception synchronously, and the received signal is the master station The frame synchronization method is characterized in that the slot timing is set on the master station side.
[0012]
The invention according to claim 3 is the frame synchronization method according to claim 1 or 2, wherein the processing in the DSP core unit is performed by interpolating n times the A / D converted data, and the second time The frame synchronization method is characterized in that the measurement is performed at a time interval of 1 / n of the sampling interval of the A / D converted data.
[0013]
The invention according to claim 4 is the frame synchronization method according to claim 1, 2, or 3, wherein the slot timing is replaced with a frame timing to directly generate a frame synchronization signal.
[0014]
The invention according to claim 5 reads the received and A / D converted data and performs a demodulation process, and the time when the first time has elapsed from the time when the synchronization word end is detected by the demodulation process is the slot timing, In a frame synchronization apparatus that generates a frame synchronization signal according to the slot timing, the data is fetched into a buffer, and the buffer data is received by an interrupt notification signal that is generated each time the data is fetched into the buffer by a predetermined number of samples. A DSP that reads and performs demodulation processing in the DSP core unit, and when the synchronization word end is detected by the demodulation processing in the DSP core unit, from the generation time of the immediately preceding interrupt notification signal to the detection time of the synchronization word end Is counted from the next occurrence of the interrupt notification signal. An initial position counter and a third time obtained by subtracting twice the period of the interrupt notification signal from the first time, starting from the time when the synchronous position counter finishes counting the second time. A frame synchronizer characterized by comprising a slot timing counter that generates the slot timing signal as a slot timing signal.
[0015]
The invention according to claim 6 is the frame synchronization apparatus according to claim 5, wherein the frame synchronization apparatus is applied to the slave station of a communication system including a master station and a slave station that perform transmission and reception synchronously, and the received signal is the master station The frame synchronization apparatus is characterized in that the slot timing is set on the master station side.
[0016]
According to a seventh aspect of the present invention, in the frame synchronization method according to the fifth or sixth aspect, the DSP core unit performs processing by interpolating n times the A / D converted data, and the synchronous position counter is The frame synchronization method is characterized in that the counting is performed at a time interval of 1 / n of the sampling interval of the A / D converted data.
[0017]
The invention according to claim 8 is the frame synchronization device according to claim 5, 6 or 7, wherein the slot timing is replaced with a frame timing, and the slot timing counter is replaced with a frame timing counter. The device.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, the demodulation processing performed by the DSP core unit starts with an interrupt notification signal generated when a certain number of data is input to the DSP buffer, and the sample position where the DSP detects the end of the synchronization word is Focusing on the fact that it is grasped, that the sampling clock is operating independently, etc., the time from the generation of the interrupt notification signal to the sample position where the DSP core section detected the end of the synchronization word is detected. When the next interrupt notification signal is generated, the time is measured, and the time from the end of the measurement to the frame synchronization position is measured to identify the frame synchronization position.
[0019]
FIG. 1 is a block diagram showing a schematic configuration of a frame synchronization position detection apparatus (slave station) according to one embodiment of the present invention. An RF unit 10 includes a frequency conversion unit 11 that converts a signal from a master station received by an antenna into an IF signal, and an A / D converter 12 that converts the IF signal into digital serial data D1. .
[0020]
Reference numeral 20 denotes a DSP, which takes in the serial data D1 transmitted from the RF unit 10 from the serial port and temporarily stores it, and reads and demodulates each time 128 samples of data D1 are accumulated in the buffer 21. A DSP core unit 22 that performs processing and synchronization detection processing is provided. The DSP core 22 also performs an operation of interpolating the read data 9 times.
[0021]
Reference numeral 30 denotes an FPGA control unit having a timing generator 31, a synchronization position counter 32, and a slot timing counter 33. The timing generator 31 sends to the A / D converter 11 and the buffer 21 a sampling clock Ssc and a data clock Sdc when one sample is represented by serial number bits, and has a frequency nine times that of the sampling clock Ssc. Clock Ssc 'is generated. When the synchronization word end Ssw is detected by the demodulation processing and the synchronization detection in the DSP core unit 22, the synchronization position counter 32 detects the detection flag Sfl and the number of samples P up to that point (the number of samples of 9 times interpolation (second number Time)), the clock Ssc 'is counted by the number of samples P from the time when the next interrupt notification signal Sit is generated. The slot timing counter 33 receives a flag Sf2 generated when the synchronization position counter 32 counts the clock Ssc 'by the number of samples P, and counts a predetermined number of times (counts the system clock) from the slot Sf2. The timing signal Ssl is output.
[0022]
As described above, the data D1 input from the serial port of the DSP 20 is sent to the buffer 21. The buffer 21 outputs an interrupt notification signal Sit to the DSP core unit 22 every time data D1 for 128 samples is accumulated. Send it out. Each time there is an interrupt notification signal Sit from the buffer 21, the DSP core unit 22 reads the data for 128 samples, performs 9 times data interpolation, and performs demodulation processing and synchronization detection processing. When the synchronization word end signal Ssw is detected, the number P of samples from the time when the immediately preceding interrupt notification signal Sit is generated to the data at the end Ssw of the synchronization word and the detection flag Sf1 thereof are used as the next interrupt notification signal Sit. At this time, the data is sent to the synchronous position counter 32.
[0023]
The synchronous position counter 32 counts 9 times the sampling clock Ssc ′ from the timing generator 31 from the time of the next interrupt notification signal Sit, and outputs the flag Sf2 to the slot timing counter 33 when the number of samples P is counted. To do. The slot timing counter 33 starts counting the system clock when it receives the flag Sf2, and outputs a slot signal Ssl when it reaches a predetermined count value. Since the frame signal is generated every predetermined number of slot signals, the frame synchronization position is specified by the slot signal Ssl.
[0024]
FIG. 2 shows a timing chart of the above operation, and FIG. 3 shows a processing timing chart. As described above, the flag Sf1 is generated when the next interrupt notification signal Sit is generated when the DSP core unit 22 detects the end Ssw of the synchronization word. The flag Sf2 is counted when the synchronization position counter 32 counts the number of samples P, that is, when a time (2To) that is twice the period To of the interrupt notification signal Sit has elapsed from the end Ssw of the synchronization word in the data D1. appear. Further, it is set on the master station side that the time point when the time X (first time) has elapsed from the time point of the synchronization word end signal Ssw is set on the master station side and is known in advance.
[0025]
Accordingly, if the slot signal Ssl is generated by measuring the time (third time) of “X-2To” by the slot timing counter 33 by counting the system clock, the synchronization word end signal Ssw is generated. No matter what timing relationship there is between the interrupt notification signal Sit and the interrupt notification signal Sit, the slot signal Ssl is always generated when the time X elapses from the synchronization word end Ssw. As described above, the frame synchronization position is detected based on the timing of the slot signal Ssl. The time X varies depending on the standard.
[0026]
In this apparatus, taking a 16QAM modulation method (one symbol is 4 bits) as an example, the IF signal frequency is 455 KHz, the sampling clock Ssc frequency is 140 KHz (period is 7.14 μsec), and the communication format is 1 symbol frequency. The rate is 11.25 KHz (88.88 μsec), 150 symbols are set to 1 slot (13.3 msec), and 6 slots constitute 1 frame (80 msec). In this case, 10.28 symbols are included in 128 samples of the interval of the interrupt notification signal Sit. That is, 12.5 samples per symbol, which is 9 times interpolated, and demodulation processing and synchronization detection are performed in the DSP core unit 22 at 1125 samples per symbol. The system (main) clock is 19.44 MHz, and the slot timing counter 33 is counted.
[0027]
The sampling clock Ssc ′ for performing the 9-times interpolation is generated by preparing a counter that counts the system clock up to the sampling clock Ssc. Under the above conditions, 19.44 MHz / 140 KHz = 138.86, so an 8-bit counter is prepared and reset by the interrupt notification signal Sit. Since this count number is not divisible, a jitter of one system clock is actually generated, but an error that can be ignored in one frame (80 msec).
[0028]
Further, since the period To of the interrupt notification signal Sit is 128 × 7.14 μsec = 913 μsec, the slot timing counter 33 that counts “X-2To” can count “X−1.82 msec” with the system clock. Use bit digits.
[0029]
In the above, the slot timing is detected and the frame synchronization position is specified. However, in the format using only the frame without using the slot, the frame timing position is directly used by using the frame timing counter instead of the slot timing counter 33. Can be specified. The clock of the slot counter 33 and the frame timing counter is not limited to the system clock, and a 9-times sampling clock Ssc ′ may be used.
[0030]
In the above, the DSP core unit 22 interpolates the data by 9 times with the clock Ssc 'which is 9 times the sampling clock Ssc, but this interpolation multiple is not essential and can be set to any n times. It is. Further, it is not always necessary to interpolate.
[0031]
【The invention's effect】
As described above, according to the present invention, an accurate frame synchronization position can be detected regardless of the timing relationship between the position of the end of the synchronization word and the interrupt notification signal. Also, if the processing in the DSP core unit is performed by interpolating the data n times and the second time is measured accordingly, the frame synchronization error is reduced to 1 / n of the sampling clock in the A / D conversion. Can be made.
[Brief description of the drawings]
FIG. 1 is a block diagram of a frame synchronization apparatus according to an embodiment of the present invention.
FIG. 2 is a timing chart of the operation of the apparatus of FIG.
FIG. 3 is a timing chart of processing of the apparatus of FIG.
FIG. 4 is a timing chart of a conventional frame synchronization operation.
[Explanation of symbols]
10: RF unit, 11: frequency conversion unit, 12: A / D converter 20: DSP, 21: buffer, 22: DSP core 30: control unit, 31: timing generator, 32: synchronous position counter, 33: slot Timing counter

Claims (8)

The data is read from the DSP buffer into the DSP core unit of the DSP by an interrupt notification signal generated every predetermined number of samples of the received and A / D converted data, and demodulated. In a frame synchronization method for generating a frame synchronization signal in accordance with the slot timing when the first time has elapsed from the time at which the frame is detected,
When the end of the synchronization word is detected in the DSP core unit, a second time from the time of the previous interrupt notification signal to the detection point of the synchronization word end is detected, and from the next generation time of the interrupt notification signal. Measuring the second time, measuring a third time obtained by subtracting twice the period of the interrupt notification signal from the first time from an end point of the measurement of the second time, and measuring the third time A frame synchronization method, wherein an end point of time measurement is the slot timing. The frame synchronization method according to claim 1,
Applied to the slave station of a communication system consisting of a master station and a slave station that perform synchronous transmission and reception, the received signal is transmitted from the master station, and the slot timing is set on the master station side A featured frame synchronization method. The frame synchronization method according to claim 1 or 2,
The processing in the DSP core unit is performed by interpolating n times the A / D converted data, and the second time measurement is performed at a 1 / n time interval of the sampling interval of the A / D converted data. A frame synchronization method characterized by comprising: In the frame synchronization method according to claim 1, 2, or 3,
A frame synchronization method comprising generating a frame synchronization signal directly by replacing the slot timing with a frame timing. The received and A / D converted data is read and demodulated, and when the first time elapses from the time when the synchronization word end is detected by the demodulation processing, the slot timing is set, and frame synchronization is performed according to the slot timing. In a frame synchronizer for generating a signal,
A DSP that fetches the data into a buffer, reads the data in the buffer by an interrupt notification signal generated each time the data is fetched into the buffer by a predetermined number of samples, and performs demodulation processing in the DSP core unit;
When the synchronization word end is detected by the demodulation processing in the DSP core unit, a second time from the generation time of the previous interrupt notification signal to the detection time of the synchronization word end is determined as the next interrupt notification signal. A synchronous position counter that counts from the occurrence of
The operation starts from the time when the synchronization position counter finishes counting the second time, and the time when the third time obtained by subtracting twice the period of the interrupt notification signal from the first time is counted as a slot. A frame synchronization apparatus, comprising: a slot timing counter that generates a timing signal. The frame synchronization apparatus according to claim 5, wherein
Applied to the slave station of a communication system consisting of a master station and a slave station that perform synchronous transmission and reception, the received signal is transmitted from the master station, and the slot timing is set on the master station side A frame synchronizer characterized by the above. The frame synchronization method according to claim 5 or 6,
The DSP core unit performs processing by interpolating n times the A / D converted data, and the synchronous position counter performs counting at a 1 / n time interval of the sampling interval of the A / D converted data. A frame synchronization method characterized by the above. The frame synchronization apparatus according to claim 5, 6 or 7,
A frame synchronization apparatus, wherein the slot timing is replaced with a frame timing, and the slot timing counter is replaced with a frame timing counter.

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