JPH04319756A - Start-stop synchronization type serial interface - Google Patents

Abstract

PURPOSE:To make it unnecessary to previously set up the data bit width of transfer data on the receiving side and to occasionally transmit/receive the transfer data by providing this serial interface with a register for setting up a value measured by a pulse width measuring counter in a shift clock counter. CONSTITUTION:Transfer data are inputted from a receiving terminal 1, the data bit width of the transfer data is measued and correct transfer data are transmitted/received by generating shift clocks having the same width to a shift register 3. At that time, equality between start bit width and data bit width in the transfer data is remarked. The start bit widt is measued by detecting the level change of the start bit by an edge detecting circuit 4 and measuring an interval between the start edge and stop edge of a start bit pulse width measuring counter 5 and the measured value is set up in a register 7. A shift clock for the shift register 3 is generated from a shift clock counter 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous serial interface capable of transmitting and receiving transfer data at any time.

0002

[Background Art] In recent years, single-chip microcomputers have become highly integrated and highly functional, and as the proportion of a single control microcomputer being involved in the application equipment has increased, it has become necessary to The use of serial interfaces has become essential.

A conventional asynchronous serial interface will be explained below. FIG. 3 shows the configuration of a conventional asynchronous serial interface. Figure 3
, 1 is a receiving terminal for receiving transfer data,
2 is a start detection circuit for detecting the start of reception of transfer data; 3 is a shift register for converting serially received transfer data into parallel; 14 is a shift clock generator for generating a shift clock for shift register 3. It is a circuit.

FIG. 4A is a timing chart of transfer data received from the receiving terminal 1, where 15 is a start bit and 16 is a data bit. Also, Figure 4(B)
is a timing chart of the shift clock generated by the shift clock generation circuit 14. The operation of the asynchronous serial interface configured as described above will be described below.

First, transfer data as shown in FIG. 4(A) is input from the reception terminal 1 in FIG. 3, and reception is started by detecting the start bit 15 of the transfer data by the start detection circuit 2. Store the transfer data in register 3. At that time, the width t of data bit 16 of the transfer data
6 is set in advance in the shift clock generation circuit 14 as transfer data information, a shift clock for the shift register 3 is generated, and correct data transfer using an asynchronous serial interface becomes possible.

[0006]

[Problems to be Solved by the Invention] However, the conventional configuration described above has a drawback in that, in order to correctly receive the transfer data, the width t6 of the data bit 16 of the transfer data must be set in advance on the receiving side. Ta. An object of the present invention is to solve the above-mentioned conventional problems, and to provide an asynchronous serial interface that does not require setting the data bit width of transfer data on the receiving side in advance and allows transfer data to be sent and received at any time. It is to provide.

[0007]

[Means for Solving the Problems] The asynchronous serial interface of the present invention includes a reception terminal for receiving transfer data, a start detection circuit for detecting the start of reception of transfer data, and a parallel connection for serially received transfer data. a shift register for conversion, an edge detection circuit for detecting a level change in transfer data, a pulse width measurement counter for measuring an interval between edges detected by the edge detection circuit;
It includes a shift clock counter that generates a shift clock for the shift register, and a register that sets the value measured by the pulse width measurement counter in the shift clock counter.

[0008]

[Operation] According to the configuration of the present invention, the start detection circuit detects the start of reception of transfer data received from the reception terminal, and the width of the data bit of the transfer data is measured by the edge detection circuit and the pulse width measurement counter. By setting this measured value in a shift clock counter using a register and generating a shift clock for the shift register using this shift clock counter, it is necessary to set the data bit width of the transfer data on the receiving side in advance. It disappears.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an asynchronous serial interface according to an embodiment of the present invention. In FIG. 1, 1 is a reception terminal for receiving transfer data, 2 is a start detection circuit for detecting the start of reception of transfer data, 3 is a shift register for converting serially received transfer data into parallel, Reference numeral 4 denotes an edge detection circuit for detecting level changes in transfer data, 5 a pulse width measurement counter for measuring the interval between edges detected by the edge detection circuit 4, and 6 a shift register 3.
A shift clock counter 7 is a register for setting the value measured by the pulse width measuring counter 5 in the shift clock counter 6.

FIG. 2A is a timing chart of transfer data received from the receiving terminal 1, where 8 is a start bit and 9 is a data bit. 2(B) is a start edge detected by the edge detection circuit 4, 12 in FIG. 2(C) is a stop edge detected by the edge detection circuit 4, and FIG. 2(D) is a start edge detected by the shift clock counter 6. 5 is a timing chart of generated shift clocks.

The operation of the asynchronous serial interface configured as described above will be explained below. First, transfer data as shown in FIG. 2(A) is input from the receiving terminal 1 in FIG. 1, the width t2 of data bit 9 of the transfer data is measured, and a shift clock of the same width for the shift register 3 is generated. This allows correct transmission and reception of transfer data. At this time, the width t1 of the start bit 8 of the transfer data
Noting that the width t2 of data bit 9 is equal to the width t2 of data bit 9, the level change of start bit 8 is detected by edge detection circuit 4, and the start edge 11 of start bit 8 is detected.
The width t1 of the start bit 8 is determined by measuring the interval between the start bit 8 and the stop edge 12 using the pulse width measurement counter 5.
is measured, the value is set in register 7, and the shift clock of shift register 3 is transferred to shift clock counter 6.
generated by.

In this case, for example, in the transfer data as shown in FIG. 4(A), data bit 16 is "L (low level)".
In this case, the width t5 of the start bit 15 cannot be measured because the boundary between the start bit 15 and the data bit 16 is not determined. Therefore, in this embodiment, as shown in FIG. 2A, the measured value of start bit 8 is set in register 7 between start bit 8 and data bit 9, and the shift clock of shift register 3 is By providing a period t3 long enough to convert the start bit 8 into a width t1, it is possible to measure the width t1 of the start bit 8, and by using the measured value to generate a shift clock for the shift register 3 using the shift clock counter 6, the asynchronous type A serial interface can be used to enable correct data transfers to be sent and received.

Note that in this embodiment, two counters 5
, 6 are used, but by using a single counter having a pulse width measurement function and a shift clock generation function instead of these, an asynchronous serial interface that can operate equivalent to this embodiment can be realized. be able to. Furthermore, the above embodiment can be realized by simply adding an edge detection circuit 4, a pulse width measurement counter 5, and a counter 6 having a function of providing a shift clock to a conventional asynchronous serial interface. Since the parts that can be used can be used from other circuits, it can be realized with a relatively small increase in hardware.

[0014]

[Effects of the Invention] The asynchronous serial interface of the present invention measures the data bit width of transfer data using an edge detection circuit and a pulse width measurement counter, and uses a register to input this measured value to a shift clock counter. By setting the shift clock and generating a shift clock for the shift register using this shift clock counter, it is not necessary to set the data bit width of the transfer data on the receiving side in advance, and the transfer data can be transmitted and received at any time.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an asynchronous serial interface according to an embodiment of the present invention.

FIG. 2(A) is a timing chart of transfer data in the same embodiment. (B) is the start edge detected by the edge detection circuit. (C) is a stop edge detected by the edge detection circuit. (D)
is a timing chart of a shift clock generated by a shift clock counter.

FIG. 3 is a configuration diagram of a conventional asynchronous serial interface.

FIG. 4A is a timing chart of conventional transfer data. (B) is a timing chart of the shift clock generated by the shift clock generation circuit.

[Explanation of symbols]

1 Receiving terminal 2 Start detection circuit 3 Shift register 4 Edge detection circuit 5 Pulse width measurement counter 6 Shift clock counter 7 Register

Claims (1)

[Claims] [Claim 1] A reception terminal that receives transfer data, a start detection circuit that detects the start of reception of transfer data, a shift register that converts serially received transfer data into parallel data, and a shift register that detects level changes in transfer data. an edge detection circuit, a pulse width measurement counter that measures the interval between edges detected by the edge detection circuit, a shift clock counter that generates a shift clock for the shift register, and a pulse width measurement counter that measures the interval between edges detected by the edge detection circuit; and a register for setting a value in the shift clock counter.