JP2844567B2 - Signal level measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal level measuring device for measuring a signal level of a data pulse signal transmitted to a data communication line.

[0002]

2. Description of the Related Art In the measurement of the signal level of a data pulse, particularly the measurement of a double-flow signal in the opening, maintenance, field inspection, etc. of a data communication line, the current and current of the signal are fixed to 0 or 1 while the signal is fixed to 0 or 1. The voltage is measured to estimate the signal level. In addition, digital measuring instruments for measuring an AC voltage or a positive / negative rectangular wave current are already on the market, but these are limited to the measurement of positive / negative continuous waveforms having a constant period, and the display values thereof are also limited. It depends on the waveform. Therefore, in the case of a double-current signal of the 0 or 1 type constituted by a format in which the period of the waveform is not constant, such as a data signal, the measuring instrument as described above cannot be used.

[0003]

The means for measuring the signal level described above is an indirect means for measuring the average value. Not only is the measurement result not sufficient, but also the transmission side and the reception side are required to measure the average value. There was a drawback that workers had to be arranged. Further, there is a fatal drawback that there is no measuring instrument capable of directly measuring the double-flow type signals of the 0, 1 type.

The present invention has been made in view of the above-mentioned problems of the signal level measuring means, and has solved the problems of these measuring means. It is an object of the present invention to provide a signal level measurement device capable of obtaining desired measurement results by efficient means.

[0005]

The above object can be attained by adopting the following novel characteristic constitution means of the present invention. That is, the first feature of the present invention is that the data communication line is connected to a terminal device side or a station device side,
A signal detection circuit for detecting a data pulse signal, an edge detection circuit for generating an edge pulse when the output signal of the signal detection circuit rises and falls, and a comparison circuit for comparing the level of the output signal with a reference level. A synchronous circuit that generates a predetermined sampling pulse based on the edge pulse, and controlled by the sampling pulse,
A comparison result display circuit for displaying a comparison result output by the comparison circuit, wherein the signal level measurement device detects a data pulse signal level of a data communication line by controlling the sampling pulse generated based on the edge pulse. It is.

A second feature of the present invention is that a signal detecting circuit connected to a terminal device or a station device side of a data communication line for detecting a data pulse signal, and a double current type analog value of the signal detecting circuit are provided. An edge detection circuit that generates an edge pulse when the output signal rises or falls, and an A / D that converts the analog value output signal into a digital value and measures it
A signal level measuring circuit including a conversion circuit; a synchronizing circuit for generating a predetermined sampling pulse based on the edge pulse; and a signal level for displaying a digital value output from the signal level measuring circuit under the control of the sampling pulse. A signal level measuring device comprising a display circuit and detecting a data pulse signal level of a data communication line by controlling the sampling pulse generated based on the edge pulse.

[0007]

According to the present invention, the above-described means are adopted. The edge detecting circuit detects the rising edge and the falling edge of the data pulse signal transmitted to the data communication line by the signal detecting circuit. Generate a pulse,
The synchronization circuit generates a sampling pulse based on the edge pulse. In the case of the comparison circuit, the output signal of the signal detection circuit is received and compared with a reference level, and the signal level is output to the comparison result display circuit in, for example, a "good / bad" format.

On the other hand, when using a signal level measuring circuit,
The analog value output signal in the double flow format is converted into a digital value by an A / D conversion circuit, and is generally output to the signal level display circuit as a numerical value with a polarity display. These display circuits display the comparison results of the signals output by the comparison circuit,
The digital value output from the signal level measurement circuit is controlled and displayed by a sampling pulse generated by the synchronization circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram of a signal level measuring device according to the present embodiment. In the figure, A is a signal level measuring device of the present embodiment, and 1 is a signal detection circuit for detecting a data pulse signal. Reference numeral 1a denotes an element for detecting a signal, which is a resistor having a small resistance value when measurement is performed using a current value.

Reference numeral 2 denotes an edge detection circuit which receives an output of the signal detection circuit 1 and generates a signal S1 when the signal S1 rises and falls.
A pulse is generated at each edge of the signal. 2a is a differentiating circuit that generates an edge pulse EP when the pulse rises, and 2b is a differential circuit that generates the edge pulse EP when the pulse falls. 2c
Is an OR circuit that outputs any edge pulse EP generated by the differentiating circuits 2a and 2b. An inverter circuit 2d inverts the phase of the output pulse of the differentiating circuit 2b and makes the input phase to the OR circuit 2c coincide with that of the differentiating circuit 2a.

A comparison circuit 3 receives the output of the signal detection circuit 1 and sends out a signal S2 obtained by comparing the level of the signal S1 with a reference level. Reference numeral 3a denotes a reference voltage display terminal, which supplies various reference voltages V1, V2, V3, and V4 for the comparison circuit 3 to compare the output signal S1 of the signal detection circuit 1. Reference numerals 3b, 3c, 3d and 3e denote comparison elements, respectively, and a reference voltage V generated from the reference voltage display terminal 3a together with the circuits of the OR elements 3f and 3g and the AND element 3h.
1, V2, V3, and V4 are compared with the output voltage of the signal detection circuit 1. In the circuit of the comparison circuit 3, for example, only one type of display of “good / bad” is displayed, but by increasing the number of the comparison elements 3 b to 3 e, the “high / bad” is displayed.
Good / low] can be displayed.

Reference numeral 4 denotes a synchronization circuit which generates a predetermined sampling pulse SP based on the edge pulse EP output from the edge detection circuit 2. The generation of the sampling pulse SP is performed after a predetermined time from the edge pulse EP. When the signal pulse length is 1 bit, it is generated substantially at the center of the positive and negative signal pulses. When the signal pulse length is a plurality of bits, it is generated. , The first sampling pulse SP is generated in the same manner, but the second and subsequent pulses are generated at intervals of approximately one bit length. Therefore, the signal level is extracted almost at the center of the positive / negative signal pulse, and the value of the peak level portion can be extracted. 4a is a clock signal oscillator, and 4b is a sampling pulse generation circuit.

Reference numeral 5 denotes a comparison result display circuit.
The data extracted at the time of the sampling pulse SP of the synchronizing circuit 4 is displayed among the comparison results of the signal S2 output by the control circuit 4. 5a is a display driving circuit, and 5b is a display element such as an LED. Reference numeral 6 denotes a data signal transmitting circuit for transmitting a data signal at the time of a test, which can be used as a substitute for a data terminal device at the time of a facing test of only a line. The TC and TD terminals are terminals for connecting the data signal transmission circuit 6 to the data communication line.

Second Embodiment A second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 is a schematic configuration diagram of a signal level measuring device according to the present embodiment. The same elements as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals. In the figure, B is a signal level measuring device of the present embodiment, 7 is a signal level measuring circuit, which is provided in place of the comparing circuit 3 of the signal level measuring device A of the first embodiment, and is output by the signal detecting circuit 1. A function of directly converting and measuring the level of the analog value output signal Sa in the double-flow format is provided. Reference numeral 7a denotes an A / D conversion circuit which sends out a signal Sb which is obtained by sampling, encoding and measuring the double-current type analog value output signal Sa output from the signal detection circuit 1 and converting it into a digital value. The digital value signal Sb digitally indicates the peak value of the double-flow analog value output signal Sa.

A signal level display circuit 8 is provided in place of the comparison result display circuit 5 of the first embodiment, and detects a signal Sb output from the signal level measurement circuit 7 at a sampling pulse of the synchronization circuit 4. The displayed numerical value is displayed. The numerical value to be displayed is displayed as a numerical value with polarity. Further, the signal level measuring circuit 7 can output both serial and parallel formats. Reference numeral 8a denotes a display driving circuit, and 8b denotes a control circuit, which controls the display driving circuit 8a when the end of the conversion operation of the A / D conversion circuit 7a coincides with the output of the synchronization circuit 4. Reference numeral 8c denotes a display element such as an LCD and an LED.

It should be noted that an absolute value circuit is used and a signal detection circuit 1 is used.
Converts the double-current signal Sa output by the A / D converter into an absolute value display.
Either input it to the conversion circuit 7a or, if the A / D conversion circuit 7a is controlled by a CPU, take in the numerical value output from the A / D conversion circuit 7a into this CPU and process it;
The signal level display circuit 8 can display an absolute value by outputting the signal level to the signal level display circuit 8 or performing other operations. Of course, unless a signal display circuit is added to the signal level display circuit 8, the signal level is displayed as an absolute value in any case.

Since the time point at which the sampling pulse SP is generated is set to be approximately at the center of the signal pulse based on the edge pulse EP, the numerical value output to the signal level display circuit 8 is generally Shows the peak value of the data pulse signal at the time of one sampling pulse SP. When the CPU can be used, the CPU displays the average value of the peak values of the data pulse signal at the time of a plurality of sampling pulses SP using the CPU. It is also possible to make it.

Since the respective specifications of the first and second embodiments are such specific embodiments, FIGS. 3 and 4 show a system for connecting to a data communication line prior to each operation. It will be described with reference to FIG. In the figure, L
1, L2 are terminals for connecting the terminal devices DE1, DE2 and the data communication line, and in FIG. 3, L1 is a signal transmitting terminal,
L2 is a signal receiving terminal, and LE is a ground terminal connected to the ground. In FIG. 4, the communication is performed with the partner terminal devices DE1, D
Since the operation is performed in a loop circuit configuration between E2, L1 on the transmitting terminal devices DE1 and DE2 side becomes a signal transmitting terminal terminal, and L2 on the receiving terminal devices DE1 and DE2 side becomes a signal receiving terminal terminal.

A1a, A1b, B1a and B1b are signal level measuring devices for measuring the signal level based on the current value of the data pulse signal.
B2a and B2b are devices for measuring the voltage value of the data pulse signal. When these devices are connected to a line, the locations to which the devices are connected differ depending on the measurement location or the measurement purpose.

When the measurement is performed using the current value of the data pulse signal, a signal level measuring device A1a, B1a or A1b, B1b is used. Signal level measuring device A1
“a” and “B1a” indicate the case of measurement at the transmitting end, and FIG. 3 shows the case where the terminal device DE2 is the transmitting terminal device, and FIG. 4 shows the case where the terminal device DE1 is the transmitting terminal device. Signal level measuring device A1b,
B1b is the case of the measurement at the receiving end, and is the case where the terminal device DE2 of FIGS. 3 and 4 is the receiving terminal device.

When the measurement is performed based on the voltage value of the data pulse signal, a signal level measuring device A2a, B2a or A2b, B2b is used. Signal level measuring device A2
a and B2a are signal level measuring devices A2
b and B2b are the cases of the receiving end, and FIG. 3 shows the case where the terminal device DE1 is the transmitting terminal device. In the signal level measurement devices A2a and B2a shown in FIG. 4, the measurement location changes depending on the connection location, and if the connection is made on the terminal device DE1 side as the transmission terminal device, the measurement at the transmission end of the terminal device DE1 is performed. Thus, if the connection is made on the terminal device DE2 side as the receiving terminal device, the measurement will be at the receiving end of the terminal device DE2.

Signal level measuring devices A1a, B1a and A1
Terminals TA and TB of b, B1b and A2a, B2a and A2b, B2b are for connecting these devices to a line. L1 'and L2' connect signal level measuring devices A1a and B1a and A1b and B1b to terminals TA and T1.
When the line is disconnected by B and inserted and connected to the line, L
1 and terminals corresponding to L2.

Next, the operation of the first and second embodiments A and B will be described. In this description, a case will be described in which the signal level measuring devices A1b and B1b of FIG. 3 are connected between the receiving terminals L2 and L2 'of a data communication line to detect and measure a data pulse signal as a current value. That is, FIG. 4 shows an example in which the signal detection circuit 1 in each of the signal level measuring devices A and B measures the level of the data pulse signal by the current value and measures the signal received by the terminal device DE2. Connected between the receiving sides L2 and L2 'of the data communication line.

First, in the first embodiment A, the partner terminal device D
When a data pulse signal is sent from E1 and DE2 to the terminal L2, this current generates a terminal voltage at the resistor 1a of the signal detection circuit 1 in FIG. This terminal voltage is sent to the edge detection circuit 2, and when the signal S1 rises and falls, an edge pulse EP is generated for each edge of the signal S1 by the differentiating circuits 2a and 2b, and the synchronous circuit 4 is controlled to control the sampling pulse SP. Generate. Further, the comparison circuit 3 compares the signal S1 voltage generated by the signal detection circuit 1 with a reference voltage,
The result is output to the comparison result display circuit 5. The comparison result display circuit 5 displays the result at the time of the sampling pulse SP among the comparison results of the signal S2 output from the comparison circuit 3 as the level of the data pulse signal.

On the other hand, in the second embodiment B, as shown in FIG. 2, even when a signal level measurement circuit 7 is provided instead of the comparison circuit 3 in the first embodiment A, the A / D conversion circuit 7
“a” outputs the double-current type analog value output signal Sa generated by the signal detection circuit 1 to the signal level display circuit 8 as a digital measurement value. The output signal Sb is output from the control circuit 8b to the end of the conversion operation of the A / D conversion circuit 7a and the synchronization circuit 4b.
Is output to the display drive circuit 8a at the time when the output signals of the two signal lines coincide with each other, and the measured signal level is displayed on the signal level display circuit 8 as a numerical value. Even when the terminal devices DE1 and DE2 are not provided, a test of the data communication line can be performed by transmitting a required data pulse from the data signal transmission circuit 6.

In the above description, the sampling pulse SP is supplied to the signal level display circuit 8, but it is also possible to supply this sampling pulse SP to the comparison circuit 3 or the signal level measurement circuit 7. ,
In this case, the comparison circuit 3 or the signal level measurement circuit 7
Can output the processing result at the time of the sampling pulse SP to the comparison result display circuit 5 or the signal level display circuit 8.

[0027]

Thus, in the measurement using the conventional ammeter and voltmeter, it is possible to measure a continuous AC waveform having a constant period including a rectangular wave, but it is possible to measure a data pulse train,
The measurement of a double-pulse data pulse train was not possible. According to the present invention, since the measurement is performed by controlling the sampling pulse based on the edge pulse, there is an advantage that not only these measurements can be performed but also the peak value can be measured.
In addition, the device configuration is simple, and it is possible to directly measure the transmission / reception level of the data pulse signal transmitted / received to the data communication line by an easy operation, especially the double-flow type analog value signal pulse. There is an excellent effect that not only the test but also the measurement of the double flow type pulse during the communication can be performed.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a signal level measuring device according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a signal level measuring device according to a second embodiment of the present invention.

FIG. 3 is a system diagram when the signal level measuring device according to the embodiment of the present invention is connected to a data communication line, in which a ground circuit is used.

FIG. 4 shows a case where a loop circuit is used in the above embodiment.

[Explanation of symbols]

A, A1a, A1b, A2a, A2b, B, B1a, B
1b, B2a, B2b ... signal level measuring device 1 ... signal detection circuit 1a ... signal detection element 2 ... edge detection circuit 2a, 2b ... differentiation circuit 2c ... OR circuit 2d ... inverter circuit 3 ... comparison circuit 3a ... reference voltage display terminal 3b 3e, comparison element 3f, 3g, OR element 3h, AND element 4, synchronization circuit 4a, clock signal oscillator 4b, sampling pulse generation circuit 5, comparison result display circuit 5a, 8a, display drive circuit 5b, 8c, display element 6 Data signal transmission circuit 7 Signal level measurement circuit 7a A / D conversion circuit 8 Signal level display circuit 8b Control circuit S1, S2, Sa, Sb output signal EP edge pulse SP sampling pulse DE1, DE2 … Terminal device

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takashi Sengoku 6-20-23 Shimomeguro, Meguro-ku, Tokyo Inside Miyagawa Seisakusho Co., Ltd. (72) Fumikatsu Ono 6-20 Shimomeguro, Meguro-ku, Tokyo No. 23 Inside Miyagawa Seisakusho Co., Ltd. (56) References JP-U 2-81477 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G01R 19/00-19/32 H04B 17 / 00 H04L 25/02

Claims (2)

(57) [Claims] 1. A signal detection circuit connected to a terminal device or a station device side of a data communication line for detecting a data pulse signal, a rising edge of an output signal of the signal detection circuit,
An edge detection circuit that generates an edge pulse at the time of falling; a comparison circuit that compares the level of the output signal with a reference level; a synchronization circuit that generates a predetermined sampling pulse based on the edge pulse; And a comparison result display circuit for displaying a comparison result output from the comparison circuit, and controlling a sampling pulse generated based on the edge pulse to detect a data pulse signal level of a data communication line. A signal level measuring device, characterized in that: 2. A signal detection circuit connected to a terminal device or a station device side of a data communication line for detecting a data pulse signal, and a rise and fall of a double current type analog value output signal of the signal detection circuit. Sometimes, an edge detection circuit that generates an edge pulse, a signal level measurement circuit that includes an A / D conversion circuit that converts and measures the analog value output signal into a digital value, and generates a predetermined sampling pulse based on the edge pulse A data communication line which is controlled by the sampling pulse and comprises a signal level display circuit for displaying a digital value output by the signal level measurement circuit, and which controls the sampling pulse generated based on the edge pulse. A signal level measuring device characterized by detecting a data pulse signal level of: