JP2003309542A - Interface converting apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface converting apparatus capable of easily confirming the phase relationship between a data signal to be received and a transmission timing clock. <P>SOLUTION: The interface converting apparatus is equipped with a sampling clock CK for inspecting a change point of a data signal 4, a clock generating means 16 for generating a transmission timing clock ST, a data determining means 17 for inspecting the data signal 4 at a predetermined point of time before and after a level change point of the transmission timing clock ST to determine matching/mismatching of phases. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface conversion device for detecting a phase difference between a data signal received from a terminal device and a transmission timing clock, and more particularly to a transmission timing clock using a sampling clock faster than the transmission timing clock. The present invention relates to an interface conversion device that detects data before and after the sampling point.

[0002]

2. Description of the Related Art In a conventional interface conversion device, when a data signal sent from a terminal device is taken in in synchronization with a transmission timing clock supplied to the terminal device, the phase of sampling the data signal is at the change point of the transmission timing clock. The fixed one is known.

[0003]

However, in the conventional interface conversion device, when the transmission timing clock becomes high speed or when the distance between the terminal device and the interface conversion device becomes long, the transmission from the terminal device is performed. When the received data signal is taken into the interface conversion device, the phase of sampling the data signal may coincide with the change point of the transmission timing clock due to the influence of the transmission delay. This situation will be described with reference to FIG.

FIG. 6 is a diagram showing the timings of the transmission timing clock and the data signal. Normally, the terminal device that receives the transmission timing clock sends a data signal for one cycle of the transmission timing clock to the interface conversion device at the falling timing of the transmission timing clock, and the interface conversion device transmits this data signal to the transmission timing clock. Is read at the rising timing of. This is because the purpose is to capture data at a stable location (middle) of the data signal sent from the terminal device. However, as described above, if the transmission timing clock is high speed or the distance between the terminal device and the interface conversion device is long, a delay occurs in the received data signal, making it difficult to capture the data at a stable location. Come on. Data signal a in the figure
Shows the case where the transmission delay is small, and the data signal b is the case where the transmission delay is large.

In the case of the data signal a having a small transmission delay, the data signal a near the sampling point is constant, while the data signal b having a large transmission delay, for example, a transmission delay of about a half cycle of the transmission timing clock. Then
The data signal b near the sampling point is changing. In this case, the interface conversion device cannot correctly receive the data signal sent from the terminal device. Therefore, when the phases of the transmission timing clock and the data signal are not appropriate, it is necessary to shift the phase of the transmission timing clock for sampling the received data signal by a half cycle.

For this purpose, it is important to understand the phase relationship between the received data signal and the transmission timing clock for sampling the data signal, which is confirmed using a waveform display device such as an oscilloscope. However,
In this case, it is difficult for the person who can use the waveform display device to perform the confirmation work, and further, the confirmation work inside the interface conversion device is required, and therefore the confirmation work is troublesome.

The present invention has been made to solve the above problems, and an object thereof is to provide an interface conversion device capable of easily confirming the phase relationship between a received data signal and a transmission timing clock.

[0008]

In order to solve the above problems, an interface conversion device according to the present invention comprises a transmission timing clock supplied to a terminal device and a data signal received from the terminal device in synchronization with the transmission timing clock. A phase difference detecting means for detecting a phase difference between the two is provided, and the phase difference is displayed on an external display.

The interface conversion device according to the present invention comprises a phase difference detecting means for detecting a phase difference between a transmission timing clock supplied to the terminal device and a data signal received from the terminal device in synchronization with the transmission timing clock. Since the phase difference is displayed on the external display, the phase relationship between the received data signal and the transmission timing clock can be easily recognized, and the work of adjusting the phase of the transmission timing clock can be facilitated.

The phase difference detecting means according to the present invention is
A clock generating means for generating a sampling clock and a transmission timing clock for checking the change point of the data signal,
It is characterized by further comprising data determining means for examining the data signal at a predetermined time point before and after the level change point of the transmission timing clock to determine whether the phases match or mismatch.

The phase difference detecting means according to the present invention detects a sampling clock for checking a change point of a data signal and a clock generating means for generating a transmission timing clock, and a data signal at a predetermined time point before and after the level change point of the transmission timing clock. Since the data determination means for checking the phase matching / mismatching is provided, the sampling clock is used to detect the data before and after the sampling point of the transmission timing clock, and whether the phase difference is proper due to the data matching or mismatching. Can be easily determined.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a system diagram of a data communication system to which an interface conversion device according to the present invention is applied. In FIG. 1, the data communication system includes a terminal device 2 for performing data communication and a network 5 for performing data exchange.
And an interface conversion device 1 arranged between the terminal device 2 and the network 5 and serving as an interface between them.

The interface conversion device 1 is a terminal device 2.
To the data signal 4 from the terminal device 2 in synchronization with the transmission timing clock 3
Is received, the received data signal 4 is subjected to speed conversion and protocol conversion, and the data signal 6 adapted to the network 5 is transmitted.

FIG. 2 is a block diagram of an embodiment of the interface conversion apparatus according to the present invention. In FIG. 2, the interface conversion device 1 includes a phase difference detection means 7,
A phase adjusting unit 9, a protocol / speed conversion unit 10, and a line interface unit 11 are provided.

The phase difference detecting means 7 supplies the transmission timing clock 3 to the terminal device 2, receives the data signal 4 from the terminal device 2 in synchronization with the transmission timing clock 3, and transmits the transmission timing clock 3 and the data signal 4. And a phase difference data 12 of the detected phase difference is displayed on an external display device 8 such as a personal computer. Also,
An output signal 13 equivalent to the transmission timing clock 3 is sent to the phase adjusting means 9 to sample the data signal 4.

The phase adjusting means 9 samples the data signal 4 with the output signal 13 at an appropriate position, and outputs the sampled output signal 14 to the protocol / speed converter 10.
Supply to.

The protocol / speed converter 10 speed-converts the output signal 14 supplied from the phase adjusting means 9 into data suitable for the network 5 and then protocol-converts the converted signal, and outputs the converted data as an output signal 15 to the line interface unit 11. To provide.

The line interface section 11 interfaces with the network 5 and transmits a data signal 6 to the network 5.

FIG. 3 is a circuit diagram of an embodiment of the phase difference detecting means according to the present invention. In FIG. 3, the phase difference detecting means 7 includes a clock generation circuit 16 for generating a sampling clock CK and a transmission timing clock ST for checking a change point of the data signal 4, and a predetermined time point before and after a level change point of the transmission timing clock ST. Data determining means 17 for determining whether the phases match or mismatch by checking the data signal 4 in FIG.

The data judging means 17 includes a 2-bit counter 18, a 4-bit shift register 19, a 4-bit flip-flop 20, a coincidence detection circuit 21, and an AND circuit 2.
2 is provided.

FIG. 4 is a timing chart of the phase difference detecting means according to the present invention. The operation of the phase difference detecting means shown in FIG. 3 will be described with reference to FIG. The clock generation circuit 16 generates the transmission timing clock ST and supplies it to the terminal device 2 as the transmission timing clock 3. The clock generation circuit 16 also generates a sampling clock CK,
It is supplied to the counter 18, the shift register 19, and the flip-flop 20. The sampling clock CK is
The clock signal is sufficiently faster than the transmission timing clock ST. The data signal 4 received from the terminal device 2 is
It is supplied to SD of the shift register 19 and is shifted at the rising timing of the sampling clock CK.
The data signal 4 shifted at each rising timing of the sampling clock CK is output to the outputs A0, A1, A2, and A3 of the shift register 19.

On the other hand, the counter 18 is in the reset state by the input R while the transmission timing clock ST is at L level (0), and when the transmission timing clock ST becomes H level (1), the rising timing of the sampling clock CK. To count. When the counter 18 becomes 2, that is, C0 = L level and C1 = H level, AN
The output of the D circuit 22 becomes H level, that is, the EN of the flip-flop 20 becomes H level, and the outputs A0, A of the shift register 19 at the rising edge of the sampling clock CK.
The contents of 1, A2 and A3 are taken into the flip-flop 20, and the outputs B0, B1, B2,
It is output to B3.

The match detection circuit 21 includes a flip-flop 2
The output of B0, B1, B2, and B3 of 0 is detected. For example, when the outputs B0, B1, B2, and B3 all match (“1111” or “0000”), the phase matching data 12 Is displayed on the external display device 8. In the case of phase matching, since there is no change in the data signal SD (dashed line) before and after the rising timing of the transmission timing clock ST, the data signal SD is correctly sampled by sampling the data signal SD at the rising timing of the transmission timing clock ST. Show what you can do.

The output B0 of the flip-flop 20,
When some of B1, B2, and B3 do not match, the phase mismatch data 12 is displayed on the external display device 8. In the case of a phase mismatch, there is a change in the data signal SD (solid line) before and after the rising edge of the transmission timing clock ST, and the data signal SD changes at the rising edge of the transmission timing clock ST.
Indicates that the data signal SD cannot be correctly sampled. For example, in the example of FIG. 4, B0,
B1, B2, and B3 are "0011", and the data signal S near the rising edge of the transmission timing clock ST.
D changes as shown by the solid line, indicating that the rising edge of the transmission timing clock ST is not appropriate as the sampling point of the data signal SD.

Therefore, by displaying the phase data 12 supplied from the coincidence detection circuit 21 on the external display device 8, it is possible to easily discriminate whether or not the sampling position of the transmission timing clock ST is appropriate. The external display device 8 can be used for displaying a message on a personal computer, lighting an LED, or the like.

FIG. 5 is a circuit diagram of an embodiment of the phase adjusting means according to the present invention. In FIG. 5, the phase adjusting means 9 includes an inverter circuit 24, a switch 25, and a flip-flop 23. Output signal 1 of phase difference detection means 7
3 (transmission timing clock ST) is logically inverted by the inverter circuit 24 and is selected by the switch 25 from either logical inversion or logical inversion.
It is input to the input T of the flip-flop 23. The switch 25 is composed of a mechanical switch or a logic circuit.

The data signal 4 is input to the input D of the flip-flop 23, captured by the flip-flop 23 at the rising edge of the input T, and output from the output 14. That is, when the switch 25 is switching to the solid line side, the data signal 4 is taken in by the flip-flop 23 at the rise of the output signal 13 (transmission timing clock ST), and when the switch 25 is switching to the broken line side. The data signal 4 is taken into the flip-flop 23 at the fall of the output signal 13 (transmission timing clock ST). Therefore, by observing the external display device 8, it is possible to discriminate whether or not the sampling position of the transmission timing clock ST is appropriate, and switch 2 according to the result.
By switching 5 the data signal 4 sent from the terminal device 2 can be correctly received.

[0028]

As described above, the interface conversion device according to the present invention provides the phase difference between the transmission timing clock supplied to the terminal device and the data signal received from the terminal device in synchronization with the transmission timing clock. Since the phase difference is detected on the external display by the phase difference detecting means for detecting the phase difference, it is possible to easily recognize the phase relationship between the received data signal and the transmission timing clock, and adjust the phase of the transmission timing clock. Can be facilitated.

The phase difference detecting means according to the present invention is
A clock generating means for generating a sampling clock and a transmission timing clock for checking the change point of the data signal,
Since the data determination means for checking the data signal at a predetermined time point before and after the level change point of the transmission timing clock to determine the phase match / mismatch is provided, the data before and after the sampling point of the transmission timing clock is sampled using the sampling clock. It is possible to easily detect whether or not the phase difference is appropriate by detecting and matching the data.

[Brief description of drawings]

FIG. 1 is a system diagram of a data communication system to which an interface conversion device according to the present invention is applied.

FIG. 2 is a block configuration diagram of an embodiment of an interface conversion device according to the present invention.

FIG. 3 is a circuit configuration diagram of an embodiment of phase difference detection means according to the present invention.

FIG. 4 is a timing chart of the phase difference detecting means according to the present invention.

FIG. 5 is a circuit configuration diagram of an embodiment of a phase adjusting means according to the present invention.

FIG. 6 is a diagram showing timings of a transmission timing clock and a data signal.

[Explanation of symbols]

1 Interface conversion device 2 terminal devices 3 Transmission timing clock 4, 6 data signal 5 mesh 7 Phase difference detection means 8 External display device 9 Phase adjustment means 10 Protocol / speed converter 11 Line interface section 12, 13, 14, 15 output signals 16 clock generation circuit 17 Data judgment means 18 counter 19 shift registers 20 flip-flops 21 Match detection circuit 22 AND circuit

Continued front page    F term (reference) 5K034 AA06 AA19 GG06 MM08                 5K047 AA05 AA12 GG05 GG43 MM38                       MM60

Claims (2)

[Claims] 1. A phase difference detecting means for detecting a phase difference between a transmission timing clock supplied to a terminal device and a data signal received from the terminal device in synchronization with the transmission timing clock is provided. An interface conversion device characterized by displaying on an external display. 2. The phase difference detecting means examines a data signal at a predetermined time point before and after a level change point of the transmission timing clock, and a clock generating means for generating a sampling clock and a transmission timing clock for checking the change point of the data signal. 2. The interface conversion device according to claim 1, further comprising a data determination unit that determines whether or not the phases match.